GB2215498A - Expandable reconfigurable memory circuit - Google Patents

Abstract

An expandable, reconfigurable memory circuit has a central processing unit 3, an interfaces and a physical memory space 7. The physical memory space is adapted to receive various sizes and configurations of dynamic random access memory chips. The interface has decoding logic for decoding addresses in memory from the central processing unit to produced strobe signals for each of the various chips. The interface also has an address multiplexing unit and a data buffer which are selected according to need through the decoding logic to lessen power consumption and decrease electromagnetic emissions. <IMAGE>

Description

EXPANDABLE, RECONFIGURABLE MEMORY CIRCUIT This invention relates to electronic memories and interfaces therefor. More particularly it relates to memories which are reconfigurable.

Often it is necessary to expand the memory of an electric circuit or to reconfigure the memory. Expansion may be necessitated by larger programs or greater amounts of data. Reconfiguration may be necessary because of such expansion and/or because memory chips are unavailable for a given configuration. For example, 64K words of memory may be made up of 8 64K x 1 chips or be 2 64K x 4 chips.

The ability to expand or reconfigure is desirable to meet customer needs with available supply.

In some products all of the semiconductor chips for controlling that product are contained on one board. This board is typically termed a mother/board. For products having their memory chips located on such a mother/board memory reconfiguration has typically meant the replacement of the mother/board with a new mother/board having the desired memory capability.

Such replacement is expensive as new manufacturing lines may be necessary for the board and replacement requires dismantling of the old board from the product and installation of the new board.

To avoid replacing whole mother/boards systems have been developed to allow for interchange of boards containing only the memory portion of the circuit for the product. Such memory boards are attached to the mother/board through connectors typically termed expansion slots.

It is still necessary to change the whole memory even though it is smaller than a memory/board when reconfiguration of the memory circuit is desired. This wastes both time and expense constructing the new boards. Additionally, the connection to the expansion slots is often not as secure as a chip soldered directly to a board or connected thereto through a chip socket.

Manners of addressing fixed implementation as opposed to the expandable reconfiguration implementations of physical memory as is being described here of employing DRAM's from a central processing unit are known. Typically the addresses from the CPU are fed through an address bus which is connected to all chips in a product. The addresses are decoded by a multiplexing unit to gate the row addresses then the column addresses from the address bus.

The multiplexing unit is always enabled and constantly gates the addresses whether or not they belong to addresses in physical memory or to another non-memory semiconductor chip. Multiplexor having almost zero power consumption when not switching are known in the art. Such constant gating of the addresses when not required wastes power.

Additionally DRAM memory chips are susceptible to soft errors due to electronic fields in the vicinity of the DRAM chips. Switching of address lines can cause electromagnetic fields to be emitted. Unnecessary switching is undesirable.

SUMMARY OF THE INVENTION In an aspect the present invention provides a memory circuit comprising: a CPU producing primary address signals; an interface connected to the CPU comprising decoding logic for decoding the primary address signals to produce a plurality of first strobe signals according to the primary address signals; a physical memory space connected to the interface and having a plurality of sockets, each socket being adapted to receive a memory chip and receiving one of the first strobe signals.

BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, which show a preferred embodiment of the present invention, and in which: Fig. 1 is a block diagram of a memory circuit according to the preferred embodiment of the present invention; Fig. 2 is a block diagram of a physical memory space employed in the memory circuit of Fig. 1; Fig. 3 is a portion of an interface employed in the memory circuit of Fig. 1; Fig. 4 is a block diagram of the rest of the interface employed in the circuit of Fig. 1; Fig. 5 is a timing diagram for the memory circuit of Fig. 1; and Fig. 6 is a diagram of the memory map for the memory circuit of Fig. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 1 there is shown a memory circuit 1.

The memory circuit 1 has three separate areas; a central processing unit (CPU) 3, a memory interface 5, and a physical memory space 7.

The CPU 3 controls the operation of the physical memory space 7 through the memory interface 5 to read and write data at given addresses in the physical memory space 7.

As shown in Fig. 2 the physical memory space 7 has a number of memory sockets 9. Each socket 9 is capable of holding a semiconductor memory chip 11. The sockets 9 provide a means through which the chips 11 take their connection. A connection to a chip 11 is actually connected through a socket 9. The sockets 9b, 9c are each adapted to receive a 64K x 4 chip ii, while each socket 9a is adapted to receive a 64K x 1 chip 11.

The type of memory chip 11 used in the preferred embodiment was a dynamic random access memory (DRAM) 11. The DRAM's 11 may be accessed by reading from or writing to them.

DRAM's 11 typically comprise a memory array, not shown, divided into rows and columns. To address a specific address in a chip 11 the row address and the column address must be specified separately and the chip 11 must be informed as to which is being specified at any one time.

The row and column addresses and the row and column specifiers are taken from a memory address bus 13 as M1, M2, CAS -and RAS inputs 15, 17, 19, 21.

The data is then read from or written to a RAM data bus 23 according to read and write signals from the memory address bus 13 on inputs 25 and 27 of the chip 11.

DRAM chips 11 may come in many different arrangements.

Examples of these arrangements which we will deal with here are 64K x 1, and 64K x 4 chips 11. A 64K x 1 chip 11 will store approximately 64,000 bits of information one bit at a time. A 64K x 4 chip 11 will store 6.4,000 bites of information 4 bits at a time.

The information is transferred in the form of data from or to the RAM data bus 23 as discussed previously. A 64K x 4 chip 11 will have four data line connections 29 from the RAM data bus 23, while a 64K x 1 chip 11 will only have a single input from the RAM data bus 23.

In order to store 64K words of information, every word being 8 bits long, two 64K x 4 chips 11 are necessary while eight 64K x 1 chips 11 may be used. The only chips 11 in which have been shown in Fig. 2 are chips llc. Chips 11c are two 64K x 4 chips lic.

One first 64K x 4 chip 11c will pick up or send the first four bits of a word on the RAM data bus, while the second 64K x 4 chip 11c will pick up the second four bits of a word on the RAM data bus 23. For discussion purposes the first chip 11c will be the upper chip lic of Fig. 2, while the other chip lic is the lower chip lic. Thus the upper chip lic has four data line connections 29a for the first 4 bits of each word, while the lower chip 11c has four data line connections 29b for the second 4 bits of each word from the RAM data bus 23.

The sockets 9b as discussed previously are adapted to each receive a 64K x 4 chip 11. The upper and lower sockets 9b provide for similar connections to those of upper and lower sockets Sc.

When employing eight 64K x 1 chips 11 each chip 11 must pick up one bit of a word on the RAM data bus 23 and each socket 9a has only a single connection 31 to the RAM data bus 23.

In order to address various configurations of chips 11 it will be necessary-to address the chip sockets 9a, 9b, 9c in differing manners. In the preferred embodiment the desired memory configuration was to have available memory of either 64K or 128K words. The 64K must be implementable by either using eight 64K x 1 chips 11 or two 64K x 4 chips 11, while the 128K is to be implemented using four 64K x 4 chips 11. Therefore the twelve memory sockets 9a, 9b, 9c are necessary. These sockets 9a, 9b, 9c are only adapted to contain the number of chips 11 required by the specific memory implementation, but the principles of the invention may be used for other desired memory implementations.

Memory sockets Sa are each adapted to contain 64K x 4 chips 11 for a total of 64K words, similarly sockets 9b are adapted to hold two 64K x 4 chips 11, while sockets 9c are each adapted to hold one 64K x 1 chip 11 for a total storage amount of 64K words.

To implement 64K words using 64K x 4 chips 11 sockets 9b will be filled, to implement 64K words using 64K x 1 chips 11 sockets 9a will be filled and to implement 128K words using 64K x 4 chip 11 sockets 9b and 9c will be filled.

In order to address the sockets 9b and 9c similar connections to the memory address bus 13 are provided.

Referring to Fig. 3 and 4 , the memory interface 5 has a multiplexing unit 41, a data buffer 43, and decoding logic 45. Portions of the decoding logic are shown in both Fig. 3 and Fig. 4 The multiplexor unit 41 and the decoding logic 45 have primary address inputs 47, 49 for primary addresses in the physical memory space 7 from a primary address bus 51 shown in Fig. 1.

As shown in Fig. 1 the primary address bus 51 is also connected to the primary address outputs in the CPU 3.

The interface 5 also has read and write inputs 53, 55 for read and write control lines 57, 59 from the CPU 3 as shown in Figs. 1 and 3. The data buffer 43 is connected through a primary data bus 61 to the CPU 3.

The outputs of the decoding logic are RAS and CAS lines 63 and a multiplexor and buffer strobe line 65. The multiplexor and buffer strobe line 65 is connected to the strobe input 67 of the multiplexing unit 41 and inverted and connected to the strobe input 69 of the data buffer 43. The output of the multiplexing unit 41 is a memory address line 70. The read control line 57 is further connected to the direction input 71 of the data buffer 43.

The read and write control lines 57, 59, the RAS and CAS lines 63 and the memory address line 70 together are connected to the memory address bus 13 of the physical memory space 7 of Figs 1 and 3. The other connection to the data buffer 43 is-the RAM data bus 23 of Figs. 1 and 3.

The primary address bus 51 has 19 address lines and can address up to 512K of memory. The first 128K of addresses have been taken up by memory spaces, not shown, for purposes other than to address the physical memory space 7. Thus we are only dealing with addresses between 128K and 512K for a total of 384K.

The detail of the decoding logic 45 is best shown in Fig. 3. The last three address lines from the primary address bus 51 are lines A18, A17 and A16. A refresh (RFSH) line is an output from the CPU 3 and is an input to the decoding logic 45.

A16 is connected through an inverter 80 to an OR gate 82. A17 and A18 are inputs to an OR gate 84 whose output is an input to another OR gate 86. A16 is also an input to an OR gate 88.

The RFSH line is inverted by an inverter 90 and is an input to each of the OR gates 82, 86, 88. The RFSH line is also an input to a NAND gate 92. The other input to the NAND gate 92 is the output of the OR gate 84. The output of the NAND gate 92 is inverted by inverter 94 and input to a NAND gate 96. The other input to the NAND gate 96 is an enable line (E) from the CPU 3. The output of the NAND gate 96 is the multiplexor and data buffer strobe line 65, also known as MUX.

The output of the OR gate 86 is inverted by the inverter 98 and input to an OR gate 100. The output of the OR gate 86 is also an input to each of the NAND gates 102, 104. The other inputs to the NAND gates 102, 104 are the outputs of the OR. gates 82, 88 respectively. The outputs of the NAND gates 102, 104 are inputs to OR Gates 106, 108 respectively.

The other inputs to the OR gate 100, 106, 108 are a memory enable line (ME).

The OR gates 100, 106, 108 output the RAS lines 63; individually known as RAS 0, RAS1 and RAS2 respectively.

RASO, RAS1 and RAS2 are fed through resistors 110, 112, 114 to produce signals RASa, RASb, RASc respectively. These signals are connected to the memory address bus 13. In Fig. 2 it is evident that RASc is connected to inputs 21c of sockets 9c, while RASb and RASa are connected to inputs 21b and 21a of sockets 9b and 9a respectively.

Referring to Fig. 4 an E signal from the CPU 3 is inverted and connected to a preset input 116 of a D flip flop 118. The MUX line 65 is connected to the D input 120 of the D flip flop 118. A phase signal is connected from the CPU 3 and inverted to the input to the clock input 124 of the D flip flop 118. The clear input 126 at the flip flop 118 is inverted and connected through a resistor 128 to a logic high voltage represented by the symbol +5.

The output of the flip flop 118 is a CAS signal are from the Q output 132.

A write (WR) signal line is connected from the CPU 3 through a resistor 132 to become a write enable (WE) signal connected to the memory address bus 13. The WE signal is further connected from the memory address bus 13 to each of the sockets 9a, 9b, 9c. Similarly a READ (Rd) signal line is connected from the CPU 3 to the memory address bus 13 through a resistor 133.

The CAS signal is connected through a resistor 134 to produce a CASO signal to be connected to the memory address bus 13. The CASO signal is further connected from the memory address bus 13 to each of the sockets 9a, 9b, 9c.

Reference will now be made to Fig. 5 in describing the operation of the memory circuit 1. The chips 11 have four different cycles of operation. These are a DRAM read cycle, a DRAM write cycle, a DRAM refresh cycle and a non-DRAM access cycle.

The waveforms on the various signals shown in Fig. 5 will now be defined: Phase - Phase clock generated from the CPU 3 RFSH - Refresh signal active low indicates CPU 3 is in a DRAM refresh cycle and the low order bits on the primary address bus 51 contain the refresh address E - Synchronous clock from the CPU 3 A0-A18 - 19 bit primary addresses generated by the CPU 3 ME - Memory enable generated from the CPU 3 indicating read or write operations from or to the physical memory space 7;; A) When fetching instructions and operands B) When reading or writing memory data C) During memory access cycles of DMA D) During DRAM refresh cycles MUX - Multiplexing and buffer strobe line to multiplex the lower order and higher order primary addresses to the DRAM RD - Read active low generated by the CPU 3 WR - Write active low generated by the CPU 3 RASO - Row address strobe 0 strobes the DRAM row address for addressing the sockets 9a during read, write and refresh operations RAS1 - Row address strobe 1 strobes DRAM row address for low order sockets 9b during read, write and refresh operations RAS2 - Row address strobe 2 strobes DRAM row address for high order sockets 9c during read, write and refresh operations CAS - Column address strobe strobes DRAM column addresses for all memory configurations Referring to the timing diagram of Fig. 6 it is shown that during a DRAM read cycle the RD signal will go low then the E signal will go high from the CPU 3. Upon the transition of the E signal if A17 or A18 are active and it is not a refresh cycle the MUX signal will go low.

The MUX signal will go high again when the enable signal goes low.

The RAS0-2 signals will go low if A17 or A18 are high and it is not a refresh cycle when the memory enable signal goes low.

The CAS signal will go low if MUX is active and the phase goes low. The CAS signal will go high when the enable signal goes high.

A similar situation will happen during a DRAM write signal but the transitions will occur after a WR active.

The only transitions which will occur during a refresh cycle are RASC, RAS1 and RAS2 will be active when the memory enable signal goes low. The MUX signal is inhibited as the E signal is not generated therefore no CAS signal transitions occur.

During non-memory access cycles the memory enable signal will inhibit the transition of RAS0-2.

The inhibiting of the transitions both of the multiplexing unit 41 and the RAS0-2 signals creates lower electromagnetic emissions. Additionally the multiplexing unit 41 in most instances will draw substantial amounts of power only when transitions occur. Thus power is saved by inhibiting the MUX signal approximately half of the time.

The memory circuit 1 results in a memory map of the form shown in Fig. 6. The addresses to the right preceded by a $ sign are hexadecimal. Thus each $10,000 block is 64K. The lower two 64K blocks are reserved for other memory spaces.

The $20,000 - $60,000 blocks are reserved for stack A and stack B areas. The $40,000 - $60,000 blocks are reserved for RAM a and RAM b areas.

As discussed previously, memory configurations using 8 64K x 1 chips 11, 2 64K x 1 chips 11, 4 64K x 4 chips 11 are available. With the memory circuit 1 described herein the following configurations for the memory map are available: A) Using 8 64K x 1 chips 11 the areas stack B, RAM a and RAM b will each be mapped into the same physical chips.

B) Using 2 64K x 4 chips 11 stack area A will be mirrored in RAM area A and stack area B will be mirrored in RAM area B. Either Ram area A or RAM area B will be present but not both.

C) Using 4 64K x 4 chips 11 producing 128K. Stack A will be mirrored in RAM a and stack B will be mirrored in RAM b. RAM a and RAM b will each be present.

As long as a programmer using this memory circuit 1 knows the type of memory configuration being used the memory circuit 1 is both expandable and reconfigurable. The programmer must be aware of the location and existence of each RAM and stack area so as not to lose data or overwrite valid data.

Notwithstanding these constraints the memory circuit 1 allows for simple and inexpensive expansion and reconfiguration of the physical memory space 7.

The principles described herein may be employed for lesser or greater memory sizes. For instance, the addition of an address line to the memory address bus 13 in each of the sockets 9a would increase the available memory capacity for those sockets 9a to 256K.

It is to be understood that other embodiments will fall within the spirit and scope of this invention as defined by the following claims.

Claims (8)

1. A memory circuit comprising: a CPU producing primary address signals; an interface connected to the CPU comprising decoying logic for decoding the primary address signals to produce a plurality of first strobe signals according to the primary address signals; a physical memory space connected to the interface and having a plurality of sockets, each socket being adapted to receive a memory chip and receiving one of the first strobe signals.

2. A memory circuit according to claim 1, wherein the interface further comprises; a multiplexing unit connected to the CPU and to the physical memory space for receiving the primary address signals and producing memory addresses, the memory addresses being produced by selecting the lower bits of an address than the upper bits of an address according to an enable signal from the CPU.

3. A memory circuit according to claim 2, wherein the decoding logic receives the enable signal from the CPU and the multiplexing unit is further connected to the decoding logic, and the decoding logic further produces a multiplexor signal according to the primary address signals and the multiplexing unit selects the lower bits then the upper bits of an address according to the multiplexor signal.

4. A memory circuit according to claim 2, wherein the physical memory space is connected to the CPU, and the physical memory space receives the enable signal to determine when the upper bits have been selected.

5. A memory circuit according to claim 3, wherein the decoding logic further receives a phase signal from the CPU and further produces a second strobe signal according to the enable signal, the multiplexor signal and the phase signal, the second strobe signal being connected to each of the sockets of the physical memory space to determine when the upper bits of an address have been selected.

6. A memory circuit according to claim 5, wherein the interface further comprises a data buffer connected to the CPU and to each of the sockets of the physical memory space by a primary data bus and a memory data bus respectively.

7. A memory circuit according to claim 6, wherein the data buffer receives the multiplexor signal and gates data from one of the primary data bus and the memory data bus to the other according to the multiplexor signal.

8. A memory circuit substantially as herein described with reference to the accompanying drawings.