GB2211325A - DMA controller - Google Patents
DMA controller Download PDFInfo
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- GB2211325A GB2211325A GB8824093A GB8824093A GB2211325A GB 2211325 A GB2211325 A GB 2211325A GB 8824093 A GB8824093 A GB 8824093A GB 8824093 A GB8824093 A GB 8824093A GB 2211325 A GB2211325 A GB 2211325A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Description
221 [,-25 A DMA CONTROLLER The invention relates to an 8-bit DMA
controller that finds application in 8-bit and 16-bit microprocessor systems.
There is a well known 8-bit DMA controller with several channels for data transfer, which comprises in common for all channels, temporary address register, temporary byte count register, output address buffer, address adjustment,circuit, byte count adjustment circuit, priority encoding circuit and terminal count recognising circuit. Each channel comprises a current address register, a current byte count register and a data transfer mode register. The address outputs of the temporary address register are connected to the data inputs of the output address buffer. Its outputs are the address bus of the 8-bit DMA controller. The block size data outputs of the temporary byte count register are connected to the corresponding inputs of the terminal count recognising circuit. Its terminal count output is a control output of the 8-bit DMA controller. The channel enable control output of the priority encoding circuit is connected to the corresponding inputs of the current address register, current byte count register and data transfer mode register. The byte count adjustment input of the temporary byte count register is connected to the corresponding output of the byte count adjustment circuit. The address adjustment input of the temporary address register is connected to the corresponding input of the address adjustment circuit.
The reset input, the clock input, the address strobe output, the transfer control outputs and the address enable output of the internal control circuit are inputs and outputs of the 8-bit DMA controller. The alignment enable output of the internal control circuit is connected to the corresponding inputs of the address adjustment circuit and the byte count adjustment circuit.
When a microprocessor system initialises the 8-bit DMA controller it writes a control word in the data transfer mode register by means of which it defines the data transfer mode of the channel in direct memory access, an initial address in the current address register and a size of the memory buffer in the current byte count register. When there is a request for DMA access by an input-output device, the priority encoding circuit accepts it and the 8-bit DMA controller asserts a request to the microprocessor system for control of the system bus. When the microprocessor system relinquishes the bus, the 8-bit DMA controller executes a data transfer operation. The internal control circuit activates its address enable output and the priority encoding circuit sends a request acknowledge signal to the input-output device.
The internal control circuit executes the data transfer operation between the input-output device and the memory, in the beginning of which the content of the current address register and current byte count register is written in the temporary address register and temporary byte count register. The internal control circuit activates its address strobe output.
The temporary address register asserts the memory cell address with which the input-output device will exchange data. Before activating its transfer control outputs, the internal control circuit deactivates its address strobe output. As a result the input-output device and the memory exchange data. At the end of the data transfer operation the internal control circuit deactivates its transfer control outputs, the address adjustment circuit and the byte count adjustment circuit modify the content of the temporary address register and the temporary byte count register. The internal control circuit writes back the content of the temporary address register and the temporary byte count register in the current address register and the current byte count register before the deactivating of the transfer control outputs.
A disadvantage of the described device is that the adjustment of the address in the temporary address register and the byte count in the temporary byte count register is implemented only by one. As a result of this, the described 8-bit DMA controller executes only byte-sequential transfer operations. This reduces the performance of the 16-bit microprocessor systems in which it is applied.
The aim of the invention is to design an 8 bit DMA controller, in which the address and byte count adjustment in the temporary address register and temporary byte count register is implemented by one or two. This will allow the DMA transfer in a 16-bit microprocessor system to be byte(l byte)- or word(2 bytes)-sequential.
According to the present invention there is provided an 8-bit DMA controller with several channels for data transfer, which comprises in common for all channels, temporary address register, temporary byte count register, address adjustment circuit, byte count adjustment circuit, output address buffer, terminal count recognising circuit, internal control circuit and priority encoding circuit, and each channel comprises a current address register, a current byte count register and a data tansfer mode register, where the address outputs of the temporary address register are connected to the data inputs of the output address buffer, the data outputs of which are the output address bus of the 8-bit DMA controller, the channel enable output of the priority encoding circuit is connected to the enable inputs of the current address register, current byte count register and data transfer mode register, the block size data outputs of the temporary byte count register are connected to the data inputs of the terminal count recognising circuit, the terminal count output of which is a control output of the 8-bit DMA controller, the transfer control outputs, address strobe output, address enable output, clock input and the reset input of the internal control circuit are control outputs of the 8-bit DMA controller, the adjustment enable output of the internal control circuit is connected to the enable inputs of the address adjustment circuit and byte count adjustment circuit, the byte count adjustment output of the byte count adjustment circuit is connected to the adjustment input of the temporary byte count register, and the address adjustment output of the address adjustment circuit is connected to the adjustment input of the temporary address register, wherein: the channel enable output of the priority encoding circuit, the block size data outputs of the temporary byte count register, the terminal count output of the terminal count recognising circuit, the least significant address output of the temporary address register address outputs, data transfer mode definition inputs of the data transfer mode register, the transfer control outputs, address strobe output and address enable output of the internal control circuit are connected to the control inputs of the data transfer type definition circuit, the clock input, the reset input and the word transfer definition control input-output of which are control inputs and outputs of the 8-bit DMA controller, and its word sequential alignment Control output and byte-sequential adjustment control output of the circuit are connected to the corresponding inputs of the address alignment circuit and byte count adjustment circuit.
According to one embodiment there is provided an 8-bit DMA controller with several channels for data transfer which comprises in common for all channels, temporary address register, temporary byte count register, address adjustment circuit, byte count adjustment circuit, output address buffer, terminal count recognising circuit, internal control circuit, priority encoding circuit and data transfer type definition circuit. Each channel comprises a current address register, a current byte count register and a data transfer mode register. The address outputs of the temporary address register are connected to the data inputs of the output address buffer, the data outputs of which are the output address bus of the 8 bit DMA controller. The channel enable output of the priority encoding circuit is connected to the enable inputs of the current address register, current byte count register, data transfer mode register and data transfer type definition circuit. The block size data outputs of the temporary byte count register are connected to the data inputs of the data transfer type definition circuit and terminal count recognising circuit, the terminal count output of which is connected to the corresponding input of the data transfer type definition circuit and is a control output of the 8-bit DMA controller. The least significant address output of the temporary address register address outputs is connected to the corresponding input of the data transfer type definition circuit. The word-sequential adjustment control output and the byte-sequential adjustment control output of the transfer type definition circuit are connected to the corresponding inputs of the address adjustment circuit and byte count alignment circuit. Its word transfer definition control input output is an input-output of the 8-bit DMA controller, data transfer mode definition inputs are connected to the corresponding inputs of the data transfer mode register. The transfer control outputs, address strobe output and address enable output of the internal control circuit are connected to the control inputs of the data transfer type definition circuit and are control outputs of the 8-bit DMA controller. The clock input and the reset input of the data transfer type definition circuit are control inputs of the 8-bit DMA controller and are connected correspondingly to the is clock and reset inputs of the internal control circuit, the adjustment enable output of which is connected to the enable inputs of the address adjustment circuit and byte count alignment circuit. The byte count adjustment output of the byte count adjustment circuit is connected to the adjustment input of the temporary byte count register. 'The address adjustment output of the address adjustment circuit is connected to the adjustment input of the temporary address register.
Preferably, the data transfer type definition circuit comprises a word transfer recognition control block, a word transfer definition input-output line control block and an adjustment control block. The block size data outputs and the least significant address input of the data transfer type definition circuit are control inputs of the word transfer recognition control block. The data transfer mode definition inputs of the word transfer definition input-output line control block are control inputs of the data transfer type definition circuit. The clock input, the terminal count input and the address enable input are control inputs of the data transfer type definition circuit, and other inputs are control inputs of the word transfer definition input-output line control block. The transfer control inputs and the reset input of the data transfer type definition circuit are connected to the corresponding inputs of the word transfer definition input-output line control block and an adjustment control block. The word sequential transfer enable output and the byte sequential transfer enable output of the adjustment control block are control outputs of the data transfer type definition circuit. The transfer type definition input of the adjustment control block is an output of the word transfer definition input-output line control is block. The address strobe input of the word transfer definition inputoutput line control block is a control input of the data transfer type definition circuit.
The compressed operation word transfer recognition input and normal operation word transfer recognition input of the word transfer definition input-output line control block are outputs of the word transfer recognition control block. The word transfer definition control input-output of the word transfer definition input-output line control block is connected to the corresponding inputs of the word transfer recognition control block and adjustment control block and is an input-output of the data transfer type definition circuit.
The advantage of the present invention is that the adjustment of the temporary address register and temporary byte count register is implemented by one or two. This allows the DMA transfer in a 16-bit microprocessor system to be byte- or word-sequential.
As a result of this the performance of the 16-bit microprocessor system is increased.
A preferred embodiment of the present invention is shown by way of example in the accompanying drawings, wherein:
Figure 1 is a block diagram of the 8-bit DMA controller; Figure 2 is a block diagram of the transfer type definition circuit; Figure 3 is a waveform of the single mode DMA transfer; Figure 4 is a waveform of the block mode DRA transfer.
The 8-bit DMA controller with several channels for data transfer (Fig.1) comprises in common for all channels, temporary address register 1, temporary byte is count register 2, address adjustment circuit 3, byte count adjustment circuit 4, output address buffer 5, terminal count recognising circuit 6, internal control circuit 7, priority encoding circuit 8 and data transfer type definition circuit 9. Each channel comprises a current address register 10, a current byte count register 11 and a data transfer mode register 12.
The address outputs 13 of the temporary address register 1 are connected to the data inputs of the output address buffer 5, the data outputs of which are the output address bus 14 of the 8-bit DMA controller.
The channel enable output 15 of the priority encoding circuit 8 is connected to the enable inputs of the current address register 10, current byte count register 11, data transfer mode register 12 and data transfer type definition circuit 9. The block size data outputs 16 of the temporary byte count register 2 are connected to the data inputs of the data transfer type definition circuit 9 and terminal count recognising circuit 6, the terminal count output 17 of which is connected to the corresponding input of the' data transfer type definition circuit 9 and is a control output of the 8-bit DMA controller.
The least significant address output 18 of the temporary address register 1 address outputs 13 is connected to the corresponding input of the data transfer type definition circuit 9. The word sequential adjustment control output 19 and the byte sequential adjustment control output 20 of the transfer type de ' finition circuit 9 are connected to the corresponding inputs of the address adjustment circuit 3 and byte count adjustment circuit 4. Its word transfer definition control input-output 21 is an input-output of the 8-bit DMA controller, and data transfer mode definition inputs 22 are connected to the corresponding inputs of the data transfer mode register 12. The transfer control outputs 23, address strobe output 24 and address enable output 25 of the internal control circuit 7 are connected to the control inputs of the data transfer type definition circuit 9 and are control outputs of the 8-bit DMA controller. The clock input 26 and the reset input 27 of the data transfer type definition circuit 9 are control inputs of the 8 bit DMA controller and are connected correspondingly to the clock and reset inputs of the internal control circuit 7, the adjustment enable output 28 of which is connected to the enable inputs of the address adjustment circuit 3 and byte count adjustment circuit 4. The byte count adjustment output 29 of the byte count adjustment circuit 4 is connected to the adjustment input of the temporary byte count register 2. The address adjustment output of the address adjustment circuit 3 is connected to the adjustment input of the temporary address register 1.
The data transfer type definition circuit 9 comprises a word transfer recognition control block 31, a word transfer definition input-output line control block 32 and an adjustment control block 33. The block size data outputs 16 and the least significant address input 18 of the data transfer type definition circuit 9 are control inputs of the word transfer recognition control block 31. The data transfer mode definition inputs 22 of the word transfer definition input-output line control block 32 are control inputs of the data transfer type definition circuit 9. The clock input 26, the terminal count input 17 and the address enable input 25 are control inputs of the data transfer type definition circuit 9 are control inputs of the word transfer definition input-output line control block 32.
The transfer control inputs 23 and the reset input 27 of the data transfer type definition circuit 9 are connected to the corresponding inputs of the word transfer definition input-output line control block 32 and the adjustment control block 33. The word sequential transfer enable output 19 and the byte sequential transfer enable output 20 of the adjustment control block 33 are control outputs of the data transfer type definition circuit 9. The transfer type definition input 34 of the adjustment control block 33 is an output of the word transfer definition input output line Control block 32. The address strobe input 24 of the word transfer definition input-output line control block 32 is a control input of the data transfer type definition circuit 9. The compressed operation word transfer recognition input 35 and normal operation word transfer recognition input 36 of the word transfer definition input-output line control block 32 are outputs of the word transfer recognition control block 31. The word transfer definition control inputoutput 21 of the word transfer definition input output line control block 32 is connected to the corresponding inputs of the word transfer recognition control block 31 and adjustment control block 33 and is an input-output of the data transfer definition circuit 9.
The operation of the 8-bit DMA controller is as follows: When the microprocessor system initialises the 8-bit DMA controller it activates the reset input 27. After a time period equal to the reset pulse width the microprocessor system deactivates the 8-bit DMA controller reset input 27 and writes in the current address register 10 the initial address of the memory buffer, in the current byte count register 11 the size of the memory buffer, in the priority encoding circuit 8 the priority.discipline code for DMA requests service is (fixed priority or rotating priority) and in the data transfer mode register 12 of each channel a control word by means of which it defines the data transfer mode of the channel in direct memory access. The 8-bit DMA controller operates in two main data transfer modes - single transfer and block transfer, and all other transfer modes are their derivatives. The main difference between these two data transfer modes are that, in a single transfer mode, on each request for direct memory access only one data unit (byte) is transferred, the data transfer operation is normal (during each of them the address strobe output 24 is activated) and the whole address is stored in an external latch. In block transfer mode on each request for direct memory access one data block is transferred, all transfer operations are compressed with one clock period and only the first transfer operation is normal and only in it the address strobe output 24 is activated, whereupon the most significant half of the 8-bit DMA controller address outputs 14 are stored in an external latch and the least significant half of the 12- address outputs 14 are directly maintained by the 8-bit DMA controller and sequentially changed on each transfer cycle.
After finishing the initialization procedure, the 8-bit DMA controller may be a master of the microprocessor bus by a request from an input-output device for DMA transfer, when it receives an acknowledgement from the microprocessor system for relinquishing the bus. The transfer operation on the bus in DMA mode is controlled by the internal control circuit 7, which activates its address enable output 25 and enables the data transfer type definition circuit 9. If the DMA channel, on which there is a request for data transfer, is with highest priority, the priority is encoding circuit 8 activates its channel enable output 15. As a result of that in single transfer mode, in the beginning of each transfer operation and in block transfer mode, in the beginning only of the first transfer operation, the contents of the channel's current address register 10 and current byte count register 11 are stored correspondingly in the temporary address register 1 and temporary byte count register 2.The temporary address register 1 contains the address of the memory cell, with which the DMA data transfer is realised. The temporary byte count register 2 contains the immediate number of bytes which remain to be transferred in DMA transfer mode. Besides, the temporary address register 1 activates its address outputs 13, the output address buffer 5 activates the output address bus 14, the temporary byte count register 2 activates its block size data outputs 16, the word transfer recognition control block 31 of the data transfer type definition circuit 9 checks the state of the least significant address output 18 of the temporary address register 1 and the state of the block size data outputs 16 of the temporary byte count register 2. When in the beginning of each normal transfer operation the least significant address output 18 of the temporary address register 1 is active (the address of the selected memory cell is odd), regardless of the temporary byte count register 2 content, the word transfer recognition control block 31 of the data transfer type definition circuit 9 does not activate its normal operation word transfer recognition input 36. In the beginning of a normal transfer operation the internal control circuit 7 activates its address strobe output 24 and the word transfer definition input-output line control block 32 switches the word transfer definition control input-output 21 from three is state into inactive state. After a time period equal to the address strobe time, the internal control circuit 7 deactivates its address strobe output 24 and the word transfer definition input-output line control block 32 switches the word transfer definition control input-output 21 from inactive state into three state.
The same sequence of operations is realised when in the beginning of a normal transfer operation the least significant address output 18 of the temporary address register 1 is inactive (the address of the selected memory cell is even) and the block size data outputs 16 of the temporary byte count register 2 indicate that the number of bytes that remain to be transferred to or from the memory is equal to one.
When in the beginning of a normal transfer operation the least significant address output 18 of the temporary address register 1 is inactive and the block size data outputs 16 of the temporary byte count register 2 indicate that the number of bytes that remain to be transferred to or from the memory is greater than one, the word transfer recognition'control block 31 of the data transfer type definition circuit 9 activates its normal operation word transfer recognition input 36. In the beginning of a normal transfer operation the internal control circuit 7 activates its address strobe output 24, and word transfer definition input-output line control block 32 switches the word transfer definition control output 21 from three state into active state. After a time p(riod equal to the address strobe time, the internal control circuit 7 deactivates its address strobe output 24 and the word transfer definition input-output line control block 32 switches the word transfer definition control input-output 21 from active stat:e into three state.
The data transfer between the memory and an input-output device in DMA mode is realised when the internal control circuit 7 activates its transfer control outputs 23, whereupon the word transfer definition input-output line control block 32 enables its the word transfer definition control input 21 activates its transfer type definition output 34.
When during the active state of the transfer control outputs 23 of the internal control circuit 7, the input-output device activates the word transfer definition control input 21, then the adjustment control block 33 activates its word-sequential adjustment control output 19, whereupon the address adjustment circuit 3 and the byte count adjustment circuit 4 adjust the content of the temporary address register 1 and the temporary byte count register 2 by two.
When during the active state of the transfer control outputs 23 of the internal control circuit 7, the input-output device does not activate the word transfer definition control input 21, then the adjustment control block 33 activates its byte sequential adjustment control output 20, whereupon the address adjustment circuit 3 and the byte count adjustment circuit 4 align the content of the temporary address register 1 and the temporary byte count register 2 by one.
In DMA block transfer mode all transfer operations, after the first one, are compressed and the internal control circuit 7 does not activate its address strobe output 24. With regards to the adjustment moment of the temporary address register 1 and temporary byte count register 2 in block transfer mode the 8-bit DMA controller operates in different manners. When the adjustment of the temporary registers 1 and 2 is during the current transfer operation, the 8-but DMA controller operates in block transfer mode as described hereinbefore. When the adjustment of the temporary registers 1 and 2 is accomplished after the end of the current transfer operation, the 8-bit DMA controller operates in block transfer mode by means of a prediction algorithm, described hereinafter. At the end of the first (normal) transfer operation, before the internal control circuit 7 to activate its transfer control outputs 23, the word transfer recognition control block 31 checks the state of its least significant address input 18, the word transfer definition control input 21 and the block size data inputs 16. When the least significant address input 18 is inactive (the address of the selected memory cell is even), the word transfer definition control input 21 is active (the temporary registers will be adjusted by two) and the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are greater than three, in the next compressed transfer operation the word transfer definition input-output line control block 32 activates its word transfer definition control output 21 for time period equal to the clock period high time of the clock input 26 before the internal control circuit 7 to activate its transfer control outputs 23.
When the least significant address input 18 is inactive (the address of the selected memory cell is even), the word transfer definition control input 21 is inactive (the temporary registers will be adjusted by one) and the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are greater than three, in the next compressed transfer operation the word transfer definition input-output line control block 32 does not activate its word transfer definition control output 21 for time period equal to the clock period high time of the clock input 26 before the internal control circuit 7 to activate its transfer control outputs 23.
When the least significant address input 18 is active (the address of the selected memorv cell is odd), the word transfer definition control input 21 is active (temporary registers will be adjusted by one) and the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are greater than three, in the next compressed transfer operation the word transfer definition input-output line control block 32 activates its word transfer definition control output 21 for a time period equal to the clock period high time of the clock input 26 before the internal control circuit 7 to activate its transfer control outputs 23._ When the least significant address input 18is inactive (the address of the selected memory cell is even), the word transfer definition control input 21 is active (the temporary registers will be aligned by two) and the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are greater than three, in the next compressed transfer operation the word transfer definition input-output line control block 32 does not activate its word transfer definition control output 21 for time period equal to the clock period high time of the clock input 26 before the internal control circuit 7 to activate its transfer control outputs 23.
When the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are equal to three and the least significant address input 18 is inactive and the word transfer definition control input 21 is active (the temporary registers will be adjusted by two) or the least significant address input 18 is active and the word transfer definition control input 21 is inactive (the temporary registers will be aligned by one) or the least significant address input 18 is active and the word transfer definition control input 21 is active (the temporary registers will be aligned by two), in the next (the last) compressed transfer operation the word transfer definition input-output line control block 32 does not activate its word transfer definition control output 21 for time period equal to the clock period high time of the clock input 26 before the internal control circuit 7 to activate its transfer control outputs 23.
When the least significant address input 18 is active, the word transfer definition control input 21 is inactive (the temporary registers will be adjusted by one) and the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are equal to three, in the next (the last) compressed transfer operation the word transfer definition input-output line control block 32 activates its word transfer definition control output 21 for time period equal to the clock period high time of the clock input 26 before the internal control circuit 7 to activate its transfer control outputs 23.
In DMA block transfer mode when the block size data inputs 16 indicate that the number of bytes that remain to be transferred to or from the memory are less than three, in the next (the last) compressed transfer operation the word transfer definition input-output line control block 32 does not activate its word transfer definition control output 21 for time period equal to the clock period high time of the clock input is 26 before the internal control circuit 7 to activate its transfer control outputs 23 or at setting the temporary byte count register 2 to zero, the terminal count recognising circuit 6 activates its terminal count output 17 and the word transfer definition input output line control block 32 does not control its word transfer definition cc;ntrol input-output 21 until the microprocessor system does not write a new value in the current byte count register 11.
This invention relates to an 8-bit DMA controller that finds application in 8-bit and 16-bit microprocessor systems. The invention provides an 8 bit DMA controller, providing byte- or word-sequential DMA transfer operations. As a result of this the -performance of the 16-bit microprocessor system is increased. This may be achieved by providing a DMA controller, wherein a data transfer type definition circuit (9) controls-the adjustment of temporary registers (1,2). The transfer operation size is distinguished by means of word transfer definition control input-output line (21). An advantage of the present invention is that the adjustment of the temporary address register (1) and temporary byte count register (2) is implemented by one or two, as well as means for byte- or word-sequential DMA transfer. s 1
Claims (3)
1. An 8-bit DMA controller with several channels for data transfer, which comprises in common for all channels, temporary address register, temporary byte count register, address adjustment circuit, byte count adjustment circuit, output address buffer, terminal count recognising circuit, internal control circuit and priority encoding circuit, and each channel comprises a current address register, a current byte count register and a data transfer mode register, where the address outputs of the temporary address register are connected to the data inputs of the output address buffer, the data outputs of which are the output address bus of the 8-bit DMA controller, the channel enable output of the priority encoding circuit is connected to the enable inputs of the current address register, current byte count register and data transfer mode register, the block size data outputs of the temporary byte count register are connected to the data inputs of the terminal count recognising circuit, the terminal count output of which is a control output of the 8-bit DMA controller, the transfer control outputs, address strobe output, address enable output, clock input and the reset input of the internal control circuit are control outputs of the 8-bit DMA controller, the adjustment enable output of the internal control circuit is connected to the enable inputs of the address adjustment circuit and byte count adjustment circuit, the byte count adjustment output of the byte count adjustment circuit is connected to the adjustment input of the temporary byte count register, and the address adjustment output of the address adjustment circuit is connected to the adjustment input of the temporary address register, wherein: the channel enable output 15 of the priority encoding circuit 8, the block -21 size data outputs 16 of the temporary byte count register 2, the terminal count output 17 of the terminal count recognising circuit 6, the least significant address output 18 of the temporary address register 1 address outputs 13, data transfer mode definition inputs 22 of the data transfer mode register 12. the transfer control outputs 23, address strobe output 24 and address enable output 25 of the internal control circuit 7 are connected to the control inputs of the data transfer type definition circuit 9. the clock input 26, the reset input 27 and the word transfer definition control input-output 21 of which are control inputs and outputs of the 8-bit DMA controller, and its word-sequential alignment control is output 19 and byte-sequential adjustment control output of the circuit 9 are connected to the corresponding inputs of the address alignment circuit 3 and byte count adjustment circuit 4.
2. An 8-bit DMA controller according to claim 1, wherein: the data transfer type definition circuit 9 comprises a word transfer recognition control block 31, a word transfer definition input-output line control block 32 and an adjustment control block 33, where the block size data outputs 16 and the least significant address input 18 of the data transfer type definition circuit 9 are control inputs of the word transfer recognition control block 31, the data transfer mode definition inputs 22 of the word transfer definition input-output line control block 32 are control inputs of the data transfer definition circuit 9, the clock input 26, the terminal count input 17 and the address enable input 25 are control inputs of the data transfer type definition circuit 9 are control inputs of the, word transfer definition input-output line control block 32, the transfer control inputs 23 and the reset input 27 of which are control inputs of the data transfer type definition circuit 9 and are connected to the corresponding inputs of the adjustment control block 33, the word-sequential transfer enable output 19 and the byte-sequential transfer enable output 20 of the adjustment control block 33 are control outputs of the data transfer type definition circuit 9, the transfer type definition input 34 of the adjustment control block 33 is an output of the word transfer definition input-output line control block 32, the address strobe input 24 of the which is a control input of the data transfer type definition circuit 9, the compressed operation word transfer recognition input 35 and normal operation word transfer recognition input is 36 of the word transfer definition input-output line control block 32 are outputs of the word transfer recognition control block 31, the word transfer definition control input-output 21 of the word transfer definition input-output line control block 32 is connected to the corresponding inputs of the word transfer recognition control block 31 and adjustment control block 33 and is an input-output of the data transfer type definition circuit 9.
3. An 8-bit DMA controller substantially as hereinbefore described with reference to the accompanying drawings.
Published 1989 atThe Patent Ofnee, State House, 66171 Holborn, London WC1R 4TP. Further copies maybe obtainedfromThentOffLce. Sales Branch, St Mary Cray, Orpington, Rent BM 3RD. Printed by Multiplex techniques ltd, St Mary Cray, Kent, Con. 1187
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| BG8145587A BG45675A1 (en) | 1987-10-16 | 1987-10-16 | Controlling device for direct access |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8824093D0 GB8824093D0 (en) | 1988-11-23 |
| GB2211325A true GB2211325A (en) | 1989-06-28 |
Family
ID=3919643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8824093A Withdrawn GB2211325A (en) | 1987-10-16 | 1988-10-14 | DMA controller |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH01236342A (en) |
| BG (1) | BG45675A1 (en) |
| DE (1) | DE3835125A1 (en) |
| GB (1) | GB2211325A (en) |
| HU (1) | HUT48761A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0540206A2 (en) * | 1991-10-15 | 1993-05-05 | International Business Machines Corporation | Information handling apparatus allowing direct memory access |
| WO1993023810A1 (en) * | 1992-05-12 | 1993-11-25 | Seiko Epson Corporation | Scalable coprocessor |
| US5465332A (en) * | 1992-09-21 | 1995-11-07 | International Business Machines Corporation | Selectable 8/16 bit DMA channels for "ISA" bus |
| EP0730235A1 (en) * | 1995-03-03 | 1996-09-04 | Compaq Computer Corporation | Improved direct memory access controller having programmable timing |
| EP0797150A2 (en) * | 1996-03-21 | 1997-09-24 | Sharp Kabushiki Kaisha | DMA controller |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5892025A (en) * | 1981-11-26 | 1983-06-01 | Hitachi Ltd | Data processing system |
| US4530053A (en) * | 1983-04-14 | 1985-07-16 | International Business Machines Corporation | DMA multimode transfer controls |
-
1987
- 1987-10-16 BG BG8145587A patent/BG45675A1/en unknown
-
1988
- 1988-10-12 HU HU527388A patent/HUT48761A/en unknown
- 1988-10-14 GB GB8824093A patent/GB2211325A/en not_active Withdrawn
- 1988-10-14 DE DE19883835125 patent/DE3835125A1/en not_active Withdrawn
- 1988-10-17 JP JP26129988A patent/JPH01236342A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0540206A2 (en) * | 1991-10-15 | 1993-05-05 | International Business Machines Corporation | Information handling apparatus allowing direct memory access |
| EP0540206A3 (en) * | 1991-10-15 | 1993-05-12 | International Business Machines Corporation | Information handling apparatus allowing direct memory access |
| US5381538A (en) * | 1991-10-15 | 1995-01-10 | International Business Machines Corp. | DMA controller including a FIFO register and a residual register for data buffering and having different operating modes |
| WO1993023810A1 (en) * | 1992-05-12 | 1993-11-25 | Seiko Epson Corporation | Scalable coprocessor |
| US5465332A (en) * | 1992-09-21 | 1995-11-07 | International Business Machines Corporation | Selectable 8/16 bit DMA channels for "ISA" bus |
| EP0730235A1 (en) * | 1995-03-03 | 1996-09-04 | Compaq Computer Corporation | Improved direct memory access controller having programmable timing |
| US5603050A (en) * | 1995-03-03 | 1997-02-11 | Compaq Computer Corporation | Direct memory access controller having programmable timing |
| US5692216A (en) * | 1995-03-03 | 1997-11-25 | Compaq Computer Corporation | Direct memory access controller having programmable timing |
| EP0797150A2 (en) * | 1996-03-21 | 1997-09-24 | Sharp Kabushiki Kaisha | DMA controller |
| EP0797150A3 (en) * | 1996-03-21 | 1998-01-21 | Sharp Kabushiki Kaisha | DMA controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01236342A (en) | 1989-09-21 |
| BG45675A1 (en) | 1989-07-14 |
| GB8824093D0 (en) | 1988-11-23 |
| DE3835125A1 (en) | 1989-05-03 |
| HUT48761A (en) | 1989-06-28 |
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| Date | Code | Title | Description |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |