GB2205019A - Electronic alarm unit - Google Patents

Abstract

The alarm device is arranged to sense an electrical interface signal between two items of equipment; and comprises a timer means arranged to be started by a change in the signal and to delay the indication of an alarm, and a latch means arranged to reset the timer before the indication of an alarm upon reversal of such change, so that transient changes, do not trigger the alarm. The alarm senses voltage levels at (A,B Fig 2) on, for example a carrier detect line, data receive line, or a signal quality line. A plurality of alarms may be associated. The device may reset automatically upon cessation of the alarm condition, or may require manual resetting. LED's, an audible source and a relay provide the alarm indication (Fig 2). <IMAGE>

Description

TITLE: ELECTRONIC ALARM UNIT This invention relates to an electronic alarm unit, particularly but not solely for use in the data communications field. Alarm units are commonly used for indicating to a human operator that a particular event has taken place within or between certain pieces of equipment.

More specifically, within the data communications field te specification of a computer interface (known as CCITT V24 or R5232 conventions) lists a set of interface signals which connect the Data Communications Equipment (DCE) to the Data Terminal Equipment (DTE).

It may be desirable to bring to the attention of someone if any of these interface signals change state from an 'on' condition to an 'off' condition and vice versa or even fail completely.

An object of the present invention is to provide an alarm unit having means whereby these interface signals may be monitored in order to give an audible and/or visual indication if they change state. The alarm unit is preferably capable of alarming from an 'off' condition to an 'on' condition, from an 'on' condition to an 'off' condition and from either an 'on' or 'off' condition to a 'fail' condition.

It is desirable that the alarm unit can delay its alarm indication for a period of time which is set manually within the unit. The alarm unit can automatically or manually reset itself once the fault condition which caused it to alarm is cleared. The alarm unit will trigger a relay once the alarm has been given which can be used for an external purpose.

According to the invention there is provided an alarm unit, capable of sensing a change in state of an interface signal between two pieces of equipment, cczisi a timer which will delay the indication of an alarm, a latch which will enable the timer to reset before its elapsed time without indication of an alarm, and means to allow for the automatic reset of the alarm by the input signal or manual reset by means of a switch. The indicators of the alarm unit are preferably a visual indicator, an audible indicator and a relay contact operating.

The alarm unit is preferably capable of sensing voltage changes in CCITT V24 interface signals.

A number of units may be joined together without affecting each other's performance but have a common audible alarm, an addition of a common relay and a common manual reset switch.

The audible alarm may be disabled on any individual alarm channel without affecting the operating conditions of any other alarm channel within tbe group.

The invention will now be described by way of example with reference to the accompanying drawings in which: FIGURE 1 is a block circuit diagram of the alarm circuit shown connected to a line from the Data Communications Equipment to the Data Terminal Equipment, and FIGURE 2 shows the alarm unit circuit in greater detail.

In general terns the DCE is connected to the DTE according to the CCITT V24 specification. Within that specification, pin 8 of the connector is designated as 'Data Carrier Detect' (DCD), which informs the DIE that the DCE is still in communication with the remote DCE.

Th~e alarm unit's sensor is connected to this pin and will remain 'off' as long as the DCD signal is still present, i.e. 'on'. When the DCD signal is no longer present, the sensor will turn 'on' which starts the timer.

The timer is manually adjustable so as to last longer or shorter times as required. Once the timer's time has elapsed, the latch is set 'on' and the driver sets the indicators and relay 'on'. The alarm has thus been given. However if DCD came back to an 'on' condition before the elapse of the timer, the latch would be forced 'off' by the sensor and the timer would be reset without any indication of an alarm. Once the alarm has been raised the audible alarm can be turned off by means of a switch, leaving the visual indicator on. The alarm can be reset in two ways. One is automatically when the sensor senses the 'on' condition at pin 8. The other is manually, when the sensor senses the 'on' condition at pin 8 and the reset switch (not shown) is pressed.

This alarm circuit is designed to cause a buzzer to alarm a visual indicator to light and a relay contact to switch when either a) The I/P voltage becomes less than + 5v.

b) The I/P voltage becomes less than - 5v.

A practical form of the circuit (see Figure 2) comprises for the purpose of description five blocks an an input stage, a tier, a latch, indicators and a reset.

1) INPUT STAGE The I/P stage is made up of the following components: Ri & R3 form a potential divider between I/F pin A and the +5v rail.

R2 & R4 form a potential divider between I/P pin B and the Ov rail.

D1 & D2 limit the negative voltage on IC 1 I/P pins 4 & BR< 5.

IC 1 is a voltage comparator.

R5 is a pull up resister for open collector O/P IC 1.

a) I/P voltage less than + 5v condition I/P pin A is held at Ov then the potential divider R1 & R3 would hold IC1 pin 5 at + 2.5v.

Then with I/P pin B at greater than +5v 'e'.g.

~6V then the potential divider of R2 & R4 would hold IC1 pin 4 at +3v i.e. more positive than IC1 pin 5, which would produce a logical 0 at IC1 O/P pin 2.

With I/P pin B at less than +5v e.g. +4v then the potential divider of R2 & R4 would hold IC1 pin 4 at +2v i.e. less positive than IC1 pin 5, which would produce a logical 1 at 1C1 O/P pin 2.

b) I/P voltage less than -5v condition I/P pin B is held at Ov then the potential divider R2 & R4 would hold IC1 pin 4 at Ov.

Then with I/P pin A at greater than -5v e.g. 6v then the potential divider of R1 & R3 would hold IC1 pin 5 at -0.5v i.e. more negative than 1C1 pin 4, which would produce a logical 0 at IC1 O/P pin 2.

With I/P pin A at less than -5v e.g. -4v then the potential divider of R1 & R3 would hold IC1 pin 5 at + 0.5v i.e. less negative than IC1 pin 4, which would produce a logical 1 at IC1 O/P pin 2.

2) Timer The timer stage is made up of the following components: 1C2 is an inverter.

R6 & C1 form a differentiater circuit.

VR7 & C1/C2 form the timing components for IC3.

1C3 is the timer.

S1 puts C2 in parallel with C3.

a) IC1 O pin 2 at logical 0 (Idle Condition i) 1C3 reset pin 10 is held at a 0 disabling the timer from detecting a trigger on pin 8.

ii) 1C2 inverts the 0 to a 1 which ensures C1, of differentiater circuit R6 & C1, is fully charged which holds the trigger pin of 1C3 pin 8 at a 1.

b) 1C1 O/P pin 2 at a logical 1 (Active Condition) i ) IC3 reset pin 10 is held at a 1 enabling the timer to detect a trigger on pin 8.

ii) IC2 inverts the 1 to a 0 which ensures C1, of differentiater circuit R6 & C1, is discharged which produces a 0 pulse on the trigger pin 1C3 pin 8 of the time duration set up by R6 & C1.

This 0 pulse triggers the timer IC3, which raises O/P pin 9 from a O to a 1 for the time duration set by VR7 and C2/3. When the time period has expired IC3 O/P pin 9 drops to a O.

3) Latch The latch stage is made up of the following components: 1C5 is a J-K flip-flop.

a) Idle Condition After 1C5 clear pin 2 changes from a O to a 1 as described under the 'Reset Stage' and when IC5 clock pin 1 is held at a 0 the state of Q would be at a 0 and Q would be at a 1 which puts a 1 on IC5 J pin 124.

b) Set Condition When IC5 clock pin 1 raises to a 1 the state of Q and Q do not change c) Active Condition When IC5 clock pin drops to a 0 the state of Q would change to a 1 and Q would change to a 0 which would put a 0 on 1C5 J pin 14 and with both J & K at 0 any further clock pulses would not change the state of Q or Q.

4) Indicators The indicator stage is made up of the following components: 1C7 is a Darllngton driver TR1 supplies current to LED 1, red TR2 supplies current to LED 1, green R8 limits the current through LED 1, red and green LS1 is a buzzer D3 is necessary in the multi-channel alarm unit S5 switches between the green LED and the buzzer RL1 is a single pole, single throw, normally open, relay S3 disables the indicators from displaying an alarm condition a) IC5 Q pin 12 at O (Idle Condition) With S3 closed the base of TR1 will be at O which will turn TR1 off and not allow any current to flow through LED 1 red which will not illuminate. IC7 will not be switched on from the 0 condition on IC5 Q pin 12 which causes its O/P to remain in an open circuit state.With S5 positioned towards D3 both LS1 & RL1 will remain inactive as there is no current path, which will cause LS1 to remain silent and RL1 contacts to remain open. With S5 positioned towards TR2, LS1 will remain silent as there is no current path, but the base of TR2 will draw a small amount of current through the coil of RL1. The current will not be large enough te activate RL1 but will be large enough to turn TR2 on and allow current to flow through LED1 green with R8 limiting the current which will cause LED1 green to illuminate.

b) IC5 Q pin 12 at 1 (Active Condition) With S3 closed the base of TRI will be at a 1 which will turn TR1 on and allow current to flow through LED1 red with R8 limiting the current which will cause LED1 red to illuminate.

IC7 will be switched on from the 1 condition on IC5 Q pin 12 which will cause its O/P to go short circuit to OV-. With S5 positioned towards D3 both LS1 and RL1 will be active as there is a current path via IC7 which will cause LS1 to alarm and RL1 contact to close.

With S5 positioned towards TR2, LS1 will become silent as there is no current path and the base of TR2 will be at OV from IC7; which will turn TR2 off and not allow any current to flow through LED1 green which will not illuminate.

With S3 open TR1 and IC7 can not be turned on so the condition will be the same as if IC5 Q pin 12 was at a 0 (Idle Condition).

5) Reset The reset stage is made up of the following components: IC3 is the timer IC4 is a OR gate .:hitch compares the I/P and Latch stages IC6 is a AND gate which compares the Latch stage and the Master Reset switch S4.

IC5 is a J-K flip-flop S2 changes from Auto-Reset to Manual-Reset S4 is the Master Reset switch a) Automatic Reset When S2 is in position A and IC1 O/P pin 2 is at a 0, then IC5 clear pin 2 will be at a 0 which inhibits IC5 from changing state. When IC1 O/P pin 2 changes to a 1 then IC5 clear pin 2 will be at a 1 and will allow 1C5 to change state once it detects a drop from a 1 to a O on IC5 clock pin 1. Once IC5 has changed state it is in a latched position. The only way IC5 can be cleared is by IC5 clear pin 2 to go to a O. This will happen when ICi O/P pin 2 drops to a 0.

Thus the condition from the I/P stage sets and resets the latch automatically which in turn clears the alarm condition from the indicator stage.

b) Manual Reset When S2 is in position B, IC1 O/P pin 2 is at a 0, 1C5 Q O/P pin 12 is at a 0 and S4 is in position A then IC6 AND gate pin 3 will b e at a 0 which puts a 0 on IC4 OR gate pin 2 which puts a O on IC5 clear pin 2 which inhibits IC5 from changing state.

When IC1 O/P pin 2 changes to a 1 then IC4 CR gate pin 1 will be at a 1 which puts a 1 on IC5 clear pin 2 which will allow IC5 to change state once it detects a drop from a 1 to a O on IC5 clock pin 1.

Once IC5 has changed state it is in a latched position.

The only way IC5 can be cleared is by IC5 clear pin 2 to go to a O. When IC1 O/P pin 2 drops to a O, IC4 pin 1 will be at a 0 but IC4 pin 2 will be at a 1 because ICS Q O/P pin 12 is at a 1 and S4 is at a 1 so IC4 pin 3 will remain at a 1 which does not give a reset condition for IC5 clear pin 2. This shows that the condition from the I/P stage does not reset the latch.

If 34 was put to position B then IC6 pin 3 would go to a 0 which would put a O on IC4 pin 2 and if IC1 pin 2 was at a 0 then this would give a reset condition of a O on IC5 clear pin 2. This shows that the condition from the I/P stage must be at a 0 and S4 must be in position B for the latch to be reset which in turn clears the alarm conditions from the indicator stage.

c) Timer Reset During the time period of timer IC3 O/P pin 9 raising to a 1 and then falling to a 0, which could be as long as two minutes set by VR7 and C1/C2, the I/P stage may have reverted back to a non alarm condition which would require the reseting of the timer IC3.

The timer is reset by IC1 O/P pin 2 dropping to a 0 which puts a O on 1C3 reset pin 10 which forces the 1 on IC3 O/P pin 9 to a 0. This charge cf s'aLe ;:u'~ trigger latch TC5 if it were not for IC5 clear pin 2 being connected via S2 or S2 and IC4 to IC1 O/P pin 2 which puts a 0 on the clear pin and inhibits IC5.

SUMMARY If pin A is held at OV then pin B will trigger IC1 when it becomes less than +5v i.e. +4v. If pin B is held at OV then pin A will trigger IC1 when it becomes less than -5v i.e. -4v. When IC1 is triggered it starts a timer off and when the time period has expired, triggers a latch which illuminates a red LED, alarms a buzzer and throws a relay contact. If the I/P voltage has reverted to normal before the time period has expired the timer and latch are reset.

The buzzer can be turned off by switch S5. If the alarm circuit is set for automatic reset then, when the I/P voltage reverts to normal after an alarm condition, the timer and latch are reset which turns off the red LED and stops the buzzer if S5 has the buzzer enabled or if S5 has the buzzer disabled, changes the colour of the LED from red to green which shows that the I/P voltage has returned to normal but the buzzer is still disabled.

If the alarm circuit is set for manual reset then the timer and latch can only be reset by pressing S4 while the I/P voltage is in the normal state but the bu#zer car. be c#abffle5 In the rorral zay by S5.

Multi-Channel Alarm Unit The multi-channel alarm unit is the collection of completely identical alarm channels which operate completely independent of each other but share the master reset switch S4, the buzzer LS1 and an additional master relay. The common connection point for the master reset switch is the I/P of AND gate IC6 and the centre contact of 524. This would reset all alarm channels if they were set for manual reset, the I/P condition was normal and the master reset switch was pressed.

The common connection point for the buzzer LS1 is the anode of D3. This would alarm the buzzer L51 if any channel entered into an alarm condition but could still be turned off on an individual channel basis by S5. As BL1 and LS1 are in effect parallel with each other then a 0 condition on LS1 would also activate all the relays on the other channels. D3 prevents current flowing via RL1 to a 0 on LS1 thus preventing this relay interaction.

The additional master relay is connected directly in parallel with LS1 so as long as the buzzer is going the master relay is active.

I/P Voltage Threshold Alteration As described above the voltage threshold for switching IC1 is +5v.

This threshold voltage may be altered to +Ov if R3 is taken off the +5v rail and connected to the Ov rail.

Then with I/P pin A at Ov, I/P pin B will be in a normal condition when it is greater than + 0.05v i.e.

any positive voltage. It will alarm when the I/P pin A gazes negative.

With I/P pin B at Ov, I/P pin A will be in a normal condition when it is greater than -0.05v i.e.

any negative voltage. It will alarm when the I/P pin B goes positive.

The following specification is given for the components of the circuit shown in Figure 2 but clearly is not limitative: IC1 LM339 R1,x1OK C1 4.7nF TR1 2N3904 IC2 724LS04 R2#10K C2 47 pF TR2 2N3904 IC3 556 CMOS R3-x10K C3 47 > iF IC4 74L532 R4--1OK IC5 74us73 R5 10K=-D1 OA90 LED1 TRI COLOUR IC6 74LS08 R6 4.7K#D2 OA90 IC7 ULN 2003 R7 1M - D3 OA202 R8 220---- The above described alarm unit will indicate a data communications problem immediately to the user.

It monitors the V24 signals from a modem and produces an alarm when either the communication line fails, the local equipment fails, the remote equipment fails, or an interface cable has become disconnected.

If a computer or a terminal is communicating with another computer or terminal via a telephone line then a modem will be used to connect them together. The modem is connected to the computer by a cable which lets the modem know what the computer is doing and the computer know what the modem is doing. This exchange of information has been designated by the CCITT authority under the title of V24.

When the modem is receiving information from the telephone line it passes the information onto the computer and lets the computer know the status of the telephone lin-e on the following V24 pins: Pin 3 - Receive Data - Data from the remote computer Pin 8 - Carrier Detect - The local modem is in communication with the remote modem Pin 21 - Signal Quality - The quality of the telephone line The Alarm Unit of the invention taps onto these V24 pins and continuously monitors them for a change of state which would indicate a problem. This would trigger a timing circuit inside the Alarm Unit, which is user adjustable from 0 seconds to 2 minutes. If the fault condition has not recovered within this period then an audible alarm will sound, a red LED illuminates and a relay contact closes.The audible alarm may be disabled by a switch which would leave the red LED to indicate the fault still existed. Once the fault is cleared the LED changes colour to green which would remind the user that the fault has been cleared but the audible alarm is disabled. When the audible alarm is enabled the LED will go out.

If the fault condition is intermittent and recovers before it can be located or an area is unoccupied for long periods of time but a record is needed if a fault occurred and recovered again, then the alarm unit can be set to latch. This would stop the alarm unit from reseting itself after the fault has been cleared and only be reset by pressing the Master Reset button while the input conditions are normal.

The alarm unit may be constructed as a 48 channel rack mountable unit and a 12 channel desk mounted unit.

Remote alarm monitors can be connected to the Master Unit for location where they are needed.

The advantages of using the present invention are:- 1) Instant recognition of a problem.

2) Remotely monitors any alarm condition on the equipment.

3) Groups together all equipment monitoring into one unit.

4) Can be connected easily to any V24 interface including Modems, Multiplexes, Line Drives and Port Sharers.

5) Will monitor any choice of V24 pins.

ill not alarm on short outages unless required.

7) Will automatically or manually reset after a fault.

8) Are rack or desk mountable with remote monitors.

The alarm unit can be used to monitor the CCITT V24 interface condition and give an audible and visual indication if these conditions change. It is capable of delaying its indication of an alarm condition so as to allow a time for the condition to revert back to normal. Once the alarm has been indicated by an audible noise, a visual indicator and a relay operating, the audible noise can be switched off on a per channel basis allowing other channels to indicate an alarm condition and also to avoid a nuisance. The alarm can be reset either by the input interface condition reverting to normal, or by the pressing of a reset switch whilst the input interface conditions are normal which would allow for an alarm indication to be captured before it was reset.

Claims (10)

CLAIMS.

1. An alarm device arranged to sense a change in state of an electrical interface signal between two items of equipment, comprising a timer means arranged to be started by such change in state and to delay the indication of an alarm, and a latch means arranged to reset the timer before the indication of an alarm upon reversal of such change of state.

2. An alarm device as claimed in Claim 1, including means to manually reset said timer by means of a switch.

3. An alarm device as claimed in Claim 1 or. 2, including a visual or audible alarm indicator operated by said timer.

4. An alarm device as claimed in any preceeding claim arranged to detect voltage changes in CCITT V24 interface signals.

5. An assembly alarm device latch as claimed in any preceeding claim, arranged to detect changes in state of respective signals and to operate a common alarm indication.

6. An assembly of alarm devices as claimed in Claim 5, including a common means to manually reset all said devices.

7. An alarm device as claimed in any preceeding claim in which said timer means includes an electrical comparator and variable resist or means for changing that comparator.

8. An alarm device as claimed in any preceeding Claim, in which said timer means is triggered by such change in state through the intermediary of a differential amplifier.

9. An alarm device as claimed in any preceeding Claim, in which said latch means comprises a J-K flipflop circuit.

10. An alarm device substantially as herein described with reference to the accompanying drawings.