GB2203578A

GB2203578A - Information monitoring control system

Info

Publication number: GB2203578A
Application number: GB08808312A
Authority: GB
Inventors: Hayami Yuasa
Original assignee: Nittan Co Ltd
Current assignee: Nittan Co Ltd
Priority date: 1987-04-10
Filing date: 1988-04-08
Publication date: 1988-10-19
Anticipated expiration: 2008-04-08
Also published as: JPH069070B2; JPS63254599A; GB8808312D0; GB2203578B

Abstract

An information monitoring control system includes a plurality of terminals (S1...Sn) connected to a common transmission line (1,2,3) and a central processing unit (Re). The central processing unit (Re) sequentially and circularly accesses the terminals (S1...Sn) by using a specific address signal (AD) assigned to each of the terminals and transmits and/or receives information to and/or from the terminals. Each terminal (S1...Sn) comprises an address butter (13) for setting the specific address, an address of which is set by the central processing unit (Re) through the transmission line (1,2,3). <IMAGE>

Description

Information Monitoring Control System The present invention relates to an information monitoring control system in which terminals for outputting information representing, for example, a temperature, a smoke density, or a burglar alarm are connected to a common transmission line and signals from the terminals are received and processed and, more particularly, to a means for setting an address of each terminal.

An example of a conventional address setting means for a terminal having a specific address uses a mechanical switch (e.g., a multiple switch or a rotary digital code switch having a predetermined number of bits respectively corresponding to ON/OFF contacts or a means using a semiconductor memory such as a rewritable EPROM as already disclosed in Japanese Unexamined Utility Model Publication (Rckai) No.

61-126393 or 60-82389.

In such a conventional address setting means for, e.g., a fire sensor, an address is set or written when the sensor is manufactured and a label having its address number is adhered to the sensor, or an address is set by operating a switch by a screwdriver when a terminal is installed.

In the above conventional terminals, addresses are independently set in the respective terrinals not association with a central processing unit. Therefore, the same address is sometimes set in a plurality of terminals, or when terminals of different types are installed in a single space, wrong types of address may be erroneously set. Especially in an apparatus for preventing disasters or crimes, erroneous address setting may be life-threatemng and lead to extreme danger.

According to one aspect of this invention, there is provided an intormation monitoring control system cor.#rising a plurality of terminals connected to a common transmission line, and a central processing unit for sequentially and circularly accessing the terminals by sing a specific address signal assigned to each of the terminals and transmitting or receiving information to or from the terminals, wherein each of the terminals comprises address buffer means for setting the specific ac#ress, an address of which is set by the central processing unit through the transmission line.

Embodiments of the present invention provide an information monitoring control system which an accurately set an address while transmitting or receiving a signal to or from a central processing unit.

Embodiments of the present invention provide an information monitoring control system in which an IC arrangement for setting an address can be employed.

By way of example only, an information monitoring control system according to an embodiment of the present invention will be described below with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing the main part of an information monitoring control system according to an embodiment of the present invention; and Figs. 2 and 3 are a tiig chart and a flow chart, respectively, for explaining the operation of the system in Fig. 1.

In Fig. 1, reference symbol Re represents a central processing unit comprising a microprocessor or an arithmetic and logic unit 4 including memories of various types, for supplying a clock signal to a clock line 1. This clock signal is supplied to a counter 7 for receiving an address signal from the ari t::#etic and logic unit 4, to a shift register 8 for converting an output from the counter 7 into a serial signal in response to the clock signal and supplying the address signal to an address line 2, and to a shift register 9 for receiving response data from a data line in response to the clock signal and supplying the data to the arithmetic and logic unit , respec--el .

A plurality of terminals S are connected to a transmission line consisting of the clock line 1, the address line 2, and the data line 3, all extending from the central processing unit Re. Each terminal S comprises a shift register 11, a shift register 13 for setting an address, an address comparator 12 for comparing the contents of the shift registers 11 and 13 and supplying a coincidence signal when the contents of the shift registers 11 and 13 coincide with each other, a sensor 20 for detecting a temperature, a smoke density, or the like, an information converter 15 for coding an output from the sensor 20, and a shift register 14 for, in response to the coincidence signal from the address comparator 12, reading a signal supplied from the information converter 15 and supplying the signal as a serial signal to the data line 3.

An address setting procedure of the present invention having the above arrangement will be described below in detail with reference to a timing chart of Fig. 2 and a flow chart of Fig. 3.

First, upon operation of a start switch (not shown) of the central processing unit Re, an address signal is supplied in accordance with a predetermined sequence. In this case, as shown in the flow chart of Fig. 3, the arithmetic and logic unit 4 is programmed such that the address signal is repeatedly supplied, i.e., the next address signal is not generated unless address setting of a given terminal S is completed and response data is supplied.

In the timing chart of Fig. 2, 8 bits are assigned for an address, and a 75th(HEX) (where HEX represents the hexadecimal notation) or (01110101)th terminal S is exemplified. First, a switch SW1 of the 75th terminal S is closed. At this time, the central processing unit Re repeatedly supplies address pulses representing 01110101 which are sandwiched by start and stop bits as indicated by AD of Fig. 2. Since the switch SWI is closed, the address pulses are sequentially read by the shift register 13. When reading is accurately completed, an output from a NAND gate 16 which received the start and stop bits goes to L (low level), and the clock signal from an AND gate 17 to the shift register 13 is stopped, thereby finishing address setting. When the same 75th(HEX) address signal is received from the address line 2, the address comparator 12 generates the address coincidence signal, and the information of the sensor 20 supplied through the information converter 15 and the start and stop bits are transferred to the shift register 14 and then supplied to the central processing unit Re through the data line 3 as a serial signal.

When this data transmission is completed, the central processing unit Re repeatedly supplies pulses representing the next address (e.g., 76th(HEx)), and address setting is performed in accordance with the above procedure, as shown in step f of Fig. 3.

The switch SWl may be opened when address setting is finished.

When the switch SW1 is closed to rewrite an address, an instantaneous reset signal (not shown) is supplied to the shift register 13. Therefore, an address number written in the shift register 13 is erased.

Note that in this embodiment, address setting is performed by operating the switch S1 of the terminal S. However, the present invention is not limited to this method but can be practiced by any other means to obtain the same effect.

When address setting of the respective terminals S is finished as described above, the flow advances to step q of the flow chart in Fig. 3, and the central processing unit Re sequentially and circularly processes data fetched by address polling and causes an alarm/display unit 10 to alarm or display in accordance with steps h to n. Of course if the response data is normal, an alarm signal is not generated in the alarm processing routine in step i.

As an address buffer memory, a nonvolatile memory with a power back-up and which can be rewritten, such as an E#ROM, is suitable so that data are not erased by a power failure.

In addition, the above address line, the data line, and the like constituting the transmission line can be replaced with a pair of lines by a time-division multiplex transmission method.

According to the information monitoring control system of the present invention, address setting is performed in each terminal installation while transmitting or receiving a signal to or from the central processing unit. Therefore, the same address is not set in different terminals, anda wrong address not corresponding to a terminal is not set therein. In addition, a contact failure as in a mechanical address switch does not occur, an arrangement of electrical components can be integrated, and an address can be accurately set.

Claims

1. An information monitoring control system comprising: a plurality of terminals connected to a common transmission line; and a central processing unit for sequentially and circularly accessing said terminals by using a specific address signal assigned to each of said terminals and for transmitting and/or receiving information to and/or from said terminals, wherein each of said terminals comprises address buffer means for setting the specific address, an address of which is set by said central processing unit through said transmission line.

2. A system according to claim 1, wherein said address buffer means comprises a shift register for storing an address signal.

3. A system according to claim 2, wherein said shift register comprises a programmable nonvolatile memory.

4. A system according to claim 2 or 3, wherein each terminal further comprises: address setting means, connected between said shift register and said central processing unit through an address bus, for supplying the address signal to said shift register, said address setting means being disabled in response to an address setting end signal; and address resetting means, connected between said address setting means and said central processing unit, for resetting the address signal stored in said shift register.

5. A system according to claim 4, wherein said address setting means includes integrated gate circuits.

6. A system substantially as hereinbefore described with reference to and as illustrated in any of the accompanying drawings.

7. Any and all novel features and combinations and subcombinations thereof substantially as disclosed herein.