GB2202974A

GB2202974A - Digital divider

Info

Publication number: GB2202974A
Application number: GB08707615A
Authority: GB
Inventors: Peter George Holland; Vincent Considine
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1987-03-31
Filing date: 1987-03-31
Publication date: 1988-10-05
Also published as: WO1988007717A1; GB8707615D0

Abstract

An array processor (fig. 2) is provided for implementing an iterative non-restoring division algorithm, in which each iteration of the algorithm is effected by a separate cell (10). The implementation utilises a simple regular structure using minimum width internal registers (14, 18). The dividend is shifted left and the divisor is added thereto in two's complemented or in non-complemented form in dependence upon the value of a previously formed quotient bit. The number of cells (10) equals the number of iterations and the width of the binary quotient.

Description

DIGITAL DIVIDER This invention relates to a straight-through digital divider for implementing a division algorithm in a simple manner.

The flow chart of the division algorithm is shown in Figure 1 of the accompanying drawings. The algorithm is known and is described, inter alia, in a paper entitled "Two's complement multiplication-division array based on the restoring division.1 This paper was published in the proceedings of the "1984 IEEE International Symposium on Circuits and Systems" (held in Montreal Canada 7-10th May 1984) Volume 3 pp 1078-1081. The algorithm is presently implemented, as described, in micro processor systems.

In the algorithm, a dividend binary word X less than or equal to a divider binary word Y is divided thereby to produce a quotient Q. The algorithm iterates and the number of iterations determined the number of bits N in the quotient.

To initiate the algorithm, a bit count is set to O and the MSB of the quotient Q(o) is set to 1. This initial setting of Q(o) is subsequently discarded from the quotient. The quotient is progresively formed (from the MSB to the LSB) as the shown loop is performed. The functions within the loop are effected in dependence upon the value of Q(n-l) i.e. on the previously formed quotient bit. The present quotient bit Q(n) is the complement of the carry of the function performed during the particular iteration.

In implementation of this algorithm, it is conventional to use repetitively the same registers.

Further, for N bit divisor Y or dividend X, the internal registers are normally 2N bits aside.

It is an object of the present invention to provide a digital divider for implementing the algorithm which is of simple regular construction and is able to operate at high speed.

According to the present invention, there is provided a digital straight-through divider, for implementing an iterative, non-restoring algorithm wherein a dividend is divided by a divisor to produce a quotient, comprising a first register whereinto a binary word representing a divisor may be loaded, a second register wherein progressively produced bits of a quotient may be successively stored starting from an MSB position, and a path whereon a binary word representing the dividend may be placed, the path including a plurality of similar cells, each cell comprising a third register for storing the dividend or a binary word resulting from an iteration of the algorithm, an adder, means for effecting a one-bit left shift of the binary word on the path in feeding the binary word to a first input of the adder, an output of the adder feeding the path to the third register of a next of the cells, means for complementing a carry output of the adder and for feeding the complemented carry output to the next bit position of the second register, there being means for feeding the divisor or the two's complement thereof in dependence upon the quotient bit produced in the previous cell to a second input of the adder.

The invention will be described further, by way of example, with reference to Figure 2 of the accompanying drawings which is a schematic diagram of one cell of a digital straight-through divider according to a preferred embodiment of the present invention.

As shown in Figure 2, each cell 10 is located upon a path 12 of the divider. A plurality of similar cells are located in series along the path 12. Each cell 10 comprises a first register 14 into which initially a binary word N bits wide and constituting the dividend is loaded. The dividend is fed to a first input of an adder 16. A binary word constituting the divisor is loaded into a second register 18. For each cell, a bank 24 of exclusive-or gates is interposed on the spur 22, there being one gate for each bit of the divisor and a second input 26 to each gate is received from a latch 28. The latch 28, for the first cell 10 is loaded with a "1" For each subsequent cell, the latch contains a quotient bit produced in a previous one of the cells. The latch 28 also provides a sign bit for a second input of the adder 16 and a carry-in input to the adder 16.Depending on the value of the bit contained in the latch 28 ("1^ or "0"), the divisor will change to its two's complement or will remain unchanged and will be input to a second input of the adder 16. The binary words input to the adder 16 at the first and second inputs are summed. The carry-out of the adder 16 is complemented and fed to a third register (not shown) wherein progressively formed quotient bits are stored starting from the MSB. The complemented carry-out is also fed to the next cell 10 to be stored in the latch 28 thereof.

The sum of the two input words to the adder is fed along the path 12 to a register 14 (not shown) to the next of the cells. The hardwire connection is arranged to effect a one bit left shift of the word on the path 12 between the cells.

It wil be appreciated that each cell performs an iteration of the above-described algorithm and that the width of the quotient is equal to the number of iterations and hence of cells 10.

The invention is not confined to the precise details of the foregoing example, and variations may be effected thereto. For example, in the above described embodiment, the dividend (or the binary word derived in each cell therefrom) is shiftd left one bit between adjacent pairs of cells. In the algorithm, however, the divisor is halved at each iteration. Thus, it is possible to replace the one bit left shifter between cells in the path 12 with a one bit right shift effected by an appropriate hardwire connection of the spurs 22.

The one bit left shift may alternatively be effected between the register 14 and the adder 16 of each cell.

The bank 24 of exclusive-or gates may be provided one per divider rather than one per cell as shown.

Further, it is not necessary to provide a latch 28 as the appropriate bit of the register (not shown) wherein the quotient bits are stored could be tested to determine whether the two's complement of the divisor or the divisor itself should be fed along the bus 20 and spur 22 to the appropriate cell 10.

If desired, the pipeline registers 14, 18 and 28 may be removed from the cell.

The simple and regular architecture of the cells 10 described enable VLSI chip fabrication of the divider.

The straight-through implementation of the algorithm permits a throughput rate of at least 10 MHz when operating on 16 bit binary words. With pipelining between cells, quotient are produced at the rate of one quotient bit for each clock pulse.

The internal registers (dividend and divisor) always contain the same number of bits, so that, regardless of the shifts left that occur, they only need to be as wide as the initially input words.

The divider of the invention may be used in any processor or processing application in which the division of binary numbers is involved.

Claims

1. A digital straight-through divider, for implementing an iterative, non-restoring algorithm wherein a dividend is divided by a divisor to produce a quotient, comprising a first register whereinto a binary word representing a divisor may be loaded, a second register wherein progressively produced bits of a quotient may be successively stored starting from an MSB position, and a path whereon a binary word representing the dividend may be placed, the path including a plurality of similar cells, each cell comprising a third register for storing the dividend or a binary word resulting from an iteration of the algorithm, an adder, means of effecting a one-bit left shift of the binary word on the path in feeding the binary word to a first input of the adder, an output of the adder feeding the path to the third register of a next of the cells, means for complementing a carry output of the adder and for feeding the complemented carry output to the next bit position of the second register, there being means for feeding the divisor or the two's complement thereof in dependence upon the quotient bit produced in the previous cell to a second input of the adder

2. A divider as claimed in claim 1 wherein the path connecting each cell to the next successive cell includes a hard wire connection constituting the means for effecting the one bit left shift.

3. A divider as claimed in claim 1 or 2 including, for each bit of the divisor, an exlusive-or gate, a second input to the bank of the gates being the last formed quotient bit.

4. A divider as claimed in claim 3 wherein each cell includes one of the banks of gates.

5. A divider as claimed in any preceding claim wherein each of the cells includes a latch for storing the quotient bit produced by the preceding cell.

6. A divider as claimed in any preceding claim wherein the first and third registers are N bits wide for N-bit binary words.

7. A divider as claimed in any preceding claim wherein the second register is of width equal to the number of cells.

8. A digital straight-through divider substantially as hereinbefore described with reference to and as illustrated in Figure 2 of the accompanying drawings.

9. A digital straight-through divider for implementing an iterative, non-restoring division algorithm comprising a first register whereinto a binary divisor may be loaded, a second register whereinto a binary dividend may be loaded and a third register in which a progressively produced quotient may be stored, including, for each iteration, a respective means for increasing the ratio of the dividend to the divisor by a factor of two, to produce a new dividend or new divisor, means responsive to a previously formed quotient bit for summing the new divisor with the dividend or the divisor with the new dividend, or for subtracting the new divisor from the dividend or the divisor from the new dividend, means for complementing the carry of such summation and for storing the complemented carry into the third register.