GB2198882A - A method of semiconductor device isolation by lateral separation - Google Patents

A method of semiconductor device isolation by lateral separation Download PDF

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Publication number
GB2198882A
GB2198882A GB08729422A GB8729422A GB2198882A GB 2198882 A GB2198882 A GB 2198882A GB 08729422 A GB08729422 A GB 08729422A GB 8729422 A GB8729422 A GB 8729422A GB 2198882 A GB2198882 A GB 2198882A
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United Kingdom
Prior art keywords
silicon
forming
etching
layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB08729422A
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GB8729422D0 (en
Inventor
Ju-Ho Song
Hyeon-Gi Ryku
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Samsung Semiconductor and Telecomunications Co Ltd
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Samsung Semiconductor and Telecomunications Co Ltd
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Application filed by Samsung Semiconductor and Telecomunications Co Ltd filed Critical Samsung Semiconductor and Telecomunications Co Ltd
Publication of GB8729422D0 publication Critical patent/GB8729422D0/en
Publication of GB2198882A publication Critical patent/GB2198882A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Description

9 c 2198882 A METHOD OF SEMICONDUCTOR DEVICE ISOLATION BY LATERAL
SEPARATION This invention relates to a method of semiconductor device isolation by lateral separation process, more particularly, to the inproved process technology of device isolation in densely integrated circuits.
Recently, the semiconductor memory IC is integrated more densely and according to this trend, many researches on device isolation technology are under study.
One such method which is mainly used for device isolation is known as the LOCOS method.
This method requires that a thin oxide layer 2 is f ormed on a silicon substrate 1 and silicon-nitride 3 is deposited on the oxide 2 as in Fig. l(A). Then, a photo-resist material 4 is deposited on the siliconnitride 3 and an opening 8 is made to form an isolation region by etching part of the silicon-nitride 3 by means of photo-lithograpby.
After ion implantion of a high dose impurity of the same type with the silicon substrate 1, ion implantation 5 is formed, and the photo resist 4 is removed. Then, a thick field oxide 6 is formed through oxidation in a high temperature tube as shown in Fig. I (B). The oxide grows fast in the region without silicon-nitride 3 used as an oxidation mask and lateral oxidation occurs at the edge of the silicon-nitride 3, so that a bird's beak 9 and the channel stcpper 7 due to activation and diffusion of the ion implanted impurity are formed.
Silicon-nitride 3 is then removed by etching and so is thin oxide layer 2 as shown in Fig. 1 (C).
Therefore, device or substrate region 10a where transistors or capacitors reside are separated from region 10b by field oxide 6 and channel stopper 7.
2198882 However, the isolation method by LOCOS used above results in the extension of the bird's beak to device region 10a, 10b and the reduction of the device region due to the lateral diffusion of the channel stopper region 7 in the process of field oxide 6 growth. Consequently, the active region in semiconductor IC is reduced badly.
Particularly, to manufacture a Megabit DRAM-level semiconductor memory IC, the technology to control 1 um is needed, but the method described above has a severe problem since the active region is reduced when field oxide thickness 6 is larger than 3500 A.
Also, the gate oxide near the field oxide region formed after removing the thin oxide as Fig. l(C) become a dangerously thin, which is called the gate thinning effect and the defect caused by stress in the silicon substrate during the forming of field oxide exists in the active region near the field oxide.
Therefore, it is desirable to provide a process of producing device isolation by lateral separation suppressing the extension of the isolation region to active region in processing densely integrated circuits.
According to the present invention there is provided a method of producing device isolation by lateral separation in the process of manufacturing a semiconductor device, the method comprising: forming an oxide layer on a silicon substrate; forming a silicon-nitride layer as an oxidation mask on said oxide layer; etching an opening by etching a part of said silicon-nitride layer; depositing a layer of polysilicon on the surface of said silicon-nitride and on said opening after forming the opening; forming a polysilicon spacer region in contact with the side wall of said opening through reactive ion etching without a mask; oxidising the polysilicon spacer through the formation of a field oxide; and forming the isolation region with the suitable field oxide thickness through etching the surface of the silicon-nitride layer and the oxide layer, after said oxidation process.
In one preferred method according to the present invention the process forming the channel stopper under field oxide reduces lateral diffusion of the channel stopper to active region.
Preferably, there may be provided a process for reducing the generation of crystal defect due to thermal stress in the isolation process.
llierefore the method of this invention includes the manufacturing technique to reduce the isolation region width and crystal defect due to lateral oxidation of the polysilicon 1) etching the silicon-nitride to form isolation region.
2) Forming the polysilicon spacer at the side w-dll of said silicon-nitride layer, and 3) subjecting the polysilicon and substrate to ion implantation.
An embodiment of the method according to the present invention will now be described by way of example with reference to the accompanying drawings, in which:
Fig. 1 (A) to (C) illustrate a known process of isolation, and Fig. 2 (A) to (E) illustrate a process of isolation according to the present invention.
The invention is explained in detail below with reference to Fig. 2 (A) to (E) which illustrate the manufacturing process of the isolation 30 method by lateral separation.
On the upper surface of a silicon substrate 20, an oxide layer 21 of about 100-300 A composed of silicon dioxide Si02 is formed by a normal process of thermal oxidation as shown in Fig. 2(A).
1 k A layer of silicon-nitride 22 S'3N4 of 1000 to 1500 A is then deposited on the surface of the oxide layer 21 by a normal low pressure CVD method, and a photo-resistant material 23 for photolithography is formed on the silicon-nitride layer 22.
The formation of the oxide layer 21 is used to make good the adhesion property with the silicon-nitride 22.
An isolation region is then formed by etching an opening 24 in the 10 silicon-nitride layer 22 using normal photolithography as shown in Fig. 2 (A).
After removing the photo-resistant material 23 as shown in Fig. 2 (A), a layer of 1000 to 2500 A polysilicon 25 is deposited on the whole 15 surface by a normal CVD method as shown in Fig. 2 (B).
The wafer is then plasma etched without a mask under a pressure of 900 milli-Torr, an RF of 200 Watts, a SF6 reacting gas of 175 SCCM, and a helium carrier gas of 50 SCCM.
If the polysilicon is etched back without mask as disclosed above, an amount as thick as the thickness of the polysilicon 25 on the siliconnitride 22 is etched so that a spacer of polysilicon 26 is formed on the side wall of the silicon-nitride 22, with a size of 1=0.1-0.25,pm in the horizontal direction as shown in Fig. 2 (C).
Therefore, the polysilicon spacer 26 as shown in Fig. 2 (C) is used as a side wall mask to suppress the isolation region extending to the active region caused by a "bird's beak" formation in the process of 30 field oxide formation as stated below.
Field ion implantation region 27 is formed by field ion implanting after etching the polysilicon as shown in Fig. 2 (C).
i -5 r As an example of an application of this invention, boron of 30 KeV energy and 3 x 1013ion/cm:2 is implanted into a p--type silicon substrate (20).
After ion implantation, field oxidation 28 of about 5500 A is formed as shown in Fig. 2(D). The process is performed in a high temperature diffusion tube according to a normal thermal oxidation process.
By this oxidation process, the polysilicon spacer region 26 is oxidized and becomes a silicon dioxide SiO2 oxidation as shown at 30 in Fig. 2 (D), which reduces the bird's beak shape oxidation into siliconnitride layer 22 adjacent to the polysilicon spacer layer 26.
Also, as stated above, the lateral diffusion of the field ion implantation region 27 has a margin having a width as large as the width (1) of the polysilicon spacer region 26, which prevents reduction of the active region due to lateral diffusion as conpared with the known LOCOS method.
The polysilicon spacer region 26 is oxidized at the same time as the field oxidation, preventing the field oxide from thinning which can occur in a small size pattern. The oxidation of the spacer region 26 also prevents thermal stress which can cause a crystal defect between the silicon dioxide Si02 and silicon near field oxide layer 28. A channel stopper region 29 is represented below the field oxide layer 28 in both Figs. 2(D) and 2(E).
Meanwhile, notch 31 due to the oxidation of the polysilicon spacer region 26, is made ad shown in Fig. 2 (D), but through the process of etching and removing the silicon-nitride 22 followed by removing the oxide layer for eliminating this notch 31, wherein the bird's beak shape is suppressed as shown in Fig. 2 (E), consequently, a thick field oxide layer 28 can be made. In the above process by removing the oxide layer, it is possible to form the field oxide layer 28 of the isolation region as shown in Fig. 2 (E) because of the active etching phenomina of the notch by etching on condition that the ratio of HF and DI water is 1 100 and etching time is about 6 min..
The defect in the formation of the isolation region by the known '-OMS method can be solved by adding a deposition of polysilicon and reactive ion etching this layer without pattern formation using an added mask by the method of lateral mask separation according to this invention.
That is, the ion is not implanted to a width as large as the width of the polysilicon spacer width by field ion implanting after forming the spacer to reduce lateral diffusion in the later process to form the field oxidation layer. The formation of the bird's beak shape is also suppressed because the oxidation into the active (device) region does not occur until the polysilicon spacer region is oxidized enough, fromthe beginning of oxidation and during the formation of the field oxide. The field thinning effect which means the oxide grows thin in process during the formation of the oxidation layer of small size patterns can be complemented because the polysilicon spacer compensates for the effective width of the oxidation region. It is also possible to prevent the formation of a nitride film caused by the reaction of ammonia gas due to the nitride layer and silicon substrate forming field oxide, and it is also profitable to be able to reduce the induction of a crystal defect into the silicon substrate because the polysilicon acts as a consumed layer for stress reduction.
Therefore, the method of this invention permits the process to have enough field oxide thickness in manufacturing a high dense IC with an isolation width of 1 m.
The invention is in no way limited to the example described hereinabove. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims (3)

CLAIMS: 1. A a method of producing semiconductor device isolation by lateral separation, the method comprising: forming an oxide layer on a silicon substrate; forming a silicon-nitride layer as an oxidation mask on said oxide layer; etching an opening by etching a part of said silicon-nitride layer; depositing a layer of polysilicon on the surface of said siliconnitride and on said opening after forming the opening; forming a polysilicon spacer region in contact with the side wall of said opening through reactive ion etching without a mask; oxidising the polysilicon spacer through the formation of a field oxide; and forming the isolation region with a suitable field oxide-thickness through etching the surface of the silicon-nitride layer 22 and the oxide layer, after said oxidation process.
1 ?
2. A method as claiemd in claim 1, including effecting field ion implantation after forming the polysilicon spacer region.
3. A method substantially as hereinbefore described with reference to Fig. 2 (A) to (E) of the accompanying drawings.
t A' Published 1988 at The Patent Office, State House, 66.71. High Holborn, London W01R 4TR Further copies may be obtained from The Patent Office, Sales Branch, St Mary Cray, Orpington, Xent BR5 3RD. Printed by Multiplex techniques ltd, st Mary Cray, Kent. Con. 1/87.
GB08729422A 1986-12-17 1987-12-17 A method of semiconductor device isolation by lateral separation Pending GB2198882A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR860010846A KR880008448A (en) 1986-12-17 1986-12-17 How to remove the side isolation device

Publications (2)

Publication Number Publication Date
GB8729422D0 GB8729422D0 (en) 1988-02-03
GB2198882A true GB2198882A (en) 1988-06-22

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JP (1) JPS63288043A (en)
KR (1) KR880008448A (en)
DE (1) DE3742912A1 (en)
GB (1) GB2198882A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions
GB2238658A (en) * 1989-11-23 1991-06-05 Stc Plc Integrated circuits
US5100830A (en) * 1989-02-22 1992-03-31 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
GB2252201A (en) * 1991-01-22 1992-07-29 Samsung Electronics Co Ltd Method of forming an insulating region in a semiconductor device
EP0520703A1 (en) * 1991-06-28 1992-12-30 STMicroelectronics, Inc. Method for forming field oxide regions
US5472905A (en) * 1990-11-17 1995-12-05 Samsung Electronics Co., Ltd. Method for forming a field oxide layer of a semiconductor integrated circuit device
US5563091A (en) * 1993-12-14 1996-10-08 Goldstar Electron Co., Ltd. Method for isolating semiconductor elements
US5599730A (en) * 1994-12-08 1997-02-04 Lucent Technologies Inc. Poly-buffered LOCOS
CN1059517C (en) * 1994-06-08 2000-12-13 三星电子株式会社 Device isolation method of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086352B (en) * 2020-08-06 2024-02-20 北京晶亦精微科技股份有限公司 Technology for growing oxidation isolation layer and preparing IGBT chip by using Locos
CN114429983A (en) * 2022-04-01 2022-05-03 北京芯可鉴科技有限公司 High-voltage transverse double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0067738A2 (en) * 1981-05-26 1982-12-22 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Method of reducing encroachment in a semiconductor device
US4435446A (en) * 1982-11-15 1984-03-06 Hewlett-Packard Company Edge seal with polysilicon in LOCOS process
EP0189795A2 (en) * 1985-01-31 1986-08-06 International Business Machines Corporation Oxygen-impervious pad structure on a semiconductor substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5735341A (en) * 1980-08-12 1982-02-25 Toshiba Corp Method of seperating elements of semiconductor device
JPS59139644A (en) * 1983-01-31 1984-08-10 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0067738A2 (en) * 1981-05-26 1982-12-22 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Method of reducing encroachment in a semiconductor device
US4435446A (en) * 1982-11-15 1984-03-06 Hewlett-Packard Company Edge seal with polysilicon in LOCOS process
EP0189795A2 (en) * 1985-01-31 1986-08-06 International Business Machines Corporation Oxygen-impervious pad structure on a semiconductor substrate

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5100830A (en) * 1989-02-22 1992-03-31 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions
GB2238658A (en) * 1989-11-23 1991-06-05 Stc Plc Integrated circuits
GB2238658B (en) * 1989-11-23 1993-02-17 Stc Plc Improvements in integrated circuits
US5472905A (en) * 1990-11-17 1995-12-05 Samsung Electronics Co., Ltd. Method for forming a field oxide layer of a semiconductor integrated circuit device
GB2252201A (en) * 1991-01-22 1992-07-29 Samsung Electronics Co Ltd Method of forming an insulating region in a semiconductor device
DE4129665A1 (en) * 1991-01-22 1992-07-30 Samsung Electronics Co Ltd METHOD FOR PRODUCING A COMPONENT INSULATION AREA IN A SEMICONDUCTOR COMPONENT
EP0520703A1 (en) * 1991-06-28 1992-12-30 STMicroelectronics, Inc. Method for forming field oxide regions
US5563091A (en) * 1993-12-14 1996-10-08 Goldstar Electron Co., Ltd. Method for isolating semiconductor elements
CN1059517C (en) * 1994-06-08 2000-12-13 三星电子株式会社 Device isolation method of semiconductor device
US5599730A (en) * 1994-12-08 1997-02-04 Lucent Technologies Inc. Poly-buffered LOCOS
EP0716442B1 (en) * 1994-12-08 2001-10-17 AT&T Corp. Integrated circuit fabrication utilizing LOCOS process

Also Published As

Publication number Publication date
GB8729422D0 (en) 1988-02-03
KR880008448A (en) 1988-08-31
JPS63288043A (en) 1988-11-25
DE3742912A1 (en) 1988-06-30

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