GB2196476A - A method for manufacturing a component and a component produced by the method - Google Patents
A method for manufacturing a component and a component produced by the method Download PDFInfo
- Publication number
- GB2196476A GB2196476A GB08723676A GB8723676A GB2196476A GB 2196476 A GB2196476 A GB 2196476A GB 08723676 A GB08723676 A GB 08723676A GB 8723676 A GB8723676 A GB 8723676A GB 2196476 A GB2196476 A GB 2196476A
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- Prior art keywords
- layer
- edge region
- component
- region
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Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000001465 metallisation Methods 0.000 claims abstract description 10
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005755 formation reaction Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A method for manufacturing a component includes etching a layer using three differently-shaped masks through successive intervals of depth, weighted in accordance with a binary sequence (1:2:4). The component produced by the method has 7 discrete steps (i.e. 2<n>-1 steps where n is the number of etch stages). The method can be used to produce a stepped edge region (bounding a contact hole) in the field oxide layer of a MOS field effect transistor. A metallisation layer is deposited on the stepped edge region with improved coverage. <IMAGE>
Description
SPECIFICATION
A method of manufacturing a component and a component produced by the method
This invention relates to a method for manufacturing a component and it relates particularly, though not exclusively, to a method for manufacturing a semiconductor component (e.g. an electrical device such as a MOS field effect transistor) using so-called planar fabrication techniques. The invention also relates to a component produced by the method.
Many electrical devices are manufactured using so-called planar fabrication techniques whereby individual elements of a device are formed in a single plane typically at a surface of a single crystal of silicon. Since, in general, several processing stages may be needed to fabricate the device the surface topology of the crystal is found, in practice, to be far from planar and may contain steep edges, some as deep as slum.
These edges can be troublesome if a thin, continuous film is to be deposited at the crystal surface, especially if the film thickness is less than, or similar to, the depth of an edge.
A problem may be encountered, for example, in forming an electrical contact with the drain, source or semiconductor bulk regions of a metal-oxide-semiconductor field effect transistor (MOSFET).
The problem is illustrated by reference to
Figure la of the accompanying drawings which represents one stage in the formation of an electrical contact. The figure shows a cross-sectional view through a substrate 1 of p-type silicon formed with a n±type diffusion region 2 constituting the drain (or source) region of the device. A field oxide layer 3 of silicon dioxide overlies the substrate and is provided with a contact hole 4 exposing the diffusion region.
The contact hole is formed by means of a photolithographic technique whereby a selected region of a layer 5 of a photoresist material is exposed to ultraviolet radiation through a suitably configured shadow mask thereby to permit etching of a desired region of the oxide layer. In this, and subsequently described, examples a positive photoresist, such as that known as Shipley AZ1350, is used, those regions which are exposed to radiation being susceptible to developing and etching. Figure 1 b represents a plan view of the shadow mask used in this example, the shaded part of the mask being non-transmissive of radiation and so preventing etching and the clear part being transmissive and per
mitting etching.Once etching is complete and
hole 4 has been formed, any residual photore
sist is removed and a metal film, shown at 6
in Figure Ic of the drawings, is deposited
(typically by thermal evaporation in a vacuum or by sputtering), thereby to establish an electrical contact with diffusion region 2. Typically the film is about 1,um thick though, as will be apparent from Figure 1c, the film has relatively thin regions, designated "A" in the drawing, where the metal covers an edge region, typically 0.5-1im deep, formed by the sides of hole 4. These sparsely covered regions are particularly prone to cracking due to thermal stress thus tending to cause an electrical discontinuity. Moreover, because the local resistivity of the film tends to be high in these regions the film is susceptible to burn-out and electromigration.These problems tend to degrade overall performance and reliability of the device and to limit its operational lifetime.
A similar problem may be encountered in forming an electrical contact with the gate region of a MOSFET. The gate oxide layer is typically 0.1 im thick whereas the field oxide layer, which borders the gate oxide layer, is typically 1 ,um thick. Consequently a metallisation film for establishing an electrical contact must cover a relatively steep edge, typically about 1 Hm deep.In some forms of
MOSFET, for example, where the device has been modified to be a gas-sensitive field-effect transistor (GASFET) a very thin gate electrode, typically 10 nm thick, of a catalytically active metal such as palladium or platinum is used and in these circumstances the electrode must cover two different edges, firstly due to the field oxide layer, and secondly due to a metal track which is typically 1 Cim thick and connects the electrode to a bonding pad.
Edge coverage problems may be encountered also in other contexts. For example, some devices such as microwave devices, power transistors and power rectifiers are fabricated so as to be intrinsically non-planar.
Also in some VLSI applications complex interconnections are required wherein two or more metallisation layers are arranged in stacked relationship with thin insulating films of SiO2 or polyimide separating adjacent layers. With this kind of construction a metallisation layer may cross one or more edges created by an underlying metallisation and or insulation layer.
It will be apparent from the aforementioned examples that edge coverage problems abound in the fabrication of many electrical devices. Attempts have been made to improve step coverage and in one known technique, described by Y.l. Cho et al in IEE Proc,
Vol 133, Pt I, No.1 February 1986, a hole formed in a layer of thermally grown silicon dioxide was tapered controllably by selective heat treatment of a thin layer of silicafilm applied to the oxide layer prior to etching. While it is possible to achieve improved coverage of the sides of the hole, the technique has not,
in general, proved to be sufficiently reproduci ble and reliable for many practical applications.
It is one object of the present invention to
provide an improved fabrication technique whereby the above-described problems may at least be alleviated.
According to a first aspect of the invention there is provided a method for manufacturing a component, the method including etching a layer of a material in accordance with each of a number of differently shaped patterns thereby to produce an edge region consisting of a series of discrete step formations arranged at successive levels in the layer.
The method may include etching said layer in accordance with n differently shaped patterns through successive intervals of depth weighted in accordance with a binary sequence, whereby said edge region consists of 2n~1 of said discrete steps and may further include depositing a further layer on said edge region.
According to another aspect of the invention there is provided a component produced by a method according to said first aspect of the invention. The component produced by said method may be in the form of a metaloxide-semiconductor field effect transistor wherein said layer of a material comprises a field oxide layer, said edge region bounds a contact region formed in the field oxide layer and said further layer comprises a metallisation for establishing an electrical contact with a surface exposed by said contact region. Said contact region may be a contact hole which exposes a drain, source or semiconductor bulk region of the device or a gate insulation region of the device.
According to a yet further aspect of the invention there is provided a component in the form of an electrical device including a layer of a first material having an edge region, and a layer of a second material overlying said edge region, wherein said edge region comprises a series of discrete, step formations arranged at successive levels in said layer of a first material.
The inventor has found that a stepped configuration of the kind defined is remarkably effective in promoting coverage of said edge region by said second material.
In order that the irlvention may be carried readily into effect an embodiment thereof is now described, by way of example only, by reference to Figures 2 to 4 of the accompanying drawings of which,
Figure la shows a cross-sectional view through part of a MOSFET to illustrate processing of a contact hole,
Figure lb shows a plan view of a shadow mask used to process the contact hole of Figure la,
Figure 1 c shows a cross-sectional view through the contact hole with a metallisation layer applied,
Figure 2 shows a cross-sectional view through a stepped edge region in accordance with the present invention,
Figures 3a, 3b and 3c shows respective plan views of different shadow masks used in a fabrication technique in accordance with the invention and
Figure 4 shows a cross-sectional view through an edge region to illustrate the fabrication technique.
Figure 2 of the drawings shows a detailed cross-sectional view through an edge region of an epitaxial layer 10 formed on a substrate 11. In one example of the invention layer 10 might comprise the field oxide layer of a
MOSFET with the edge region bounding a contact hole, and a layer 12 overlying the edge region could then comprise a metallisation film effective to establish an electrical contact with the drain, source or bulk semiconductor regions of the device at an exposed surface of the substrate. It will be appreciated, however, that in other applications of this invention either layer 10 or layer 12 could comprise a metal, a semi-conductor or an insulator such as an oxide or an organic material.
As shown in Figure 2, the edge region is formed as a series of discrete steps which are arranged at successive levels in the epitaxial layer, rather in the manner of a staircase, and the inventor finds that this configuration leads to improved coverage of the edge region. It will be apparent that in contrast to prior configurations, as illustrated in Figure lc for example, layer 12 is signficantly thinner than layer 10 on which it is deposited and yet is relatively free from the irregularities and relatively thin regions (A in Figure lc) which have proved to be so troublesome hitherto. Thus if layer 12 comprises a metallisation, a configuration in accordance with the present invention should be less susceptible to electrical discontinuity, burn-out and electromigration.
The inventor has discovered that a stepped edge region of the kind described may be fabricated in a relatively straight forward manner by means of a multi-stage etch process whereby a different, appropriately configured shadow mask is used at each successive stage in the process and successive etch depths, controlled by the duration of each etch, are weighted in accordance with a binary sequence (i.e. in the ratio 1:2:4: etc). By use of appropriately configured shadow masks the inventor finds that the total etch depth attained at any particular location in the edge region is equal to the sum of the individual etch depths to which that location has been subjected, thus producing a total of 2n different levels or 2n~1 different steps, where n equals the number of etch stages used. Thus, whereas a known, single stage etch process (n=1) yields 2 levels (i.e. 1 step -Figure la), a dual stage process (n=2) yields 4 levels (i.e.
3 steps) and a triple stage process (n=3) yields 8 levels (i.e. 7 steps) and so on.
The etch process will now be described in greater detail by reference to the triple stage process (n=3), and Figures 3a, 3b and 3c show plan views of the shadow masks used during the first, second and third stages respectively of the process thereby to produce a rectangular contact hole in the field oxide layer of a MOSFET.
For clarity of illustration, Figure 4 represents a cross-sectional view through one side only of the contact hole and different zones, defining the positions of different levels in the edge region, are designated in Figures 3 and 4 by numbers 0 to 7.
The uppermost level (zone 0), at the surface of the epitaxial layer, requires no etching and this is represented as an entry "0" (no etch) in a corresponding column of Table I, accompanying Figure 4, at each of the three stages I, III lil of the etch process, and as a dark region in each shadow mask.
In contrast, the lowermost level (zone 7) requires full etching, represented as an entry "1" (etch) in the table at each stage in the process, and as a clear area in each mask. In this example, the seven steps produced by the etch process are of equal depth t/7, where t is the thickness of the epitaxial layer, and the length x of each step may be as small as the process minimum feature size will allow, typically several microns. As described hereinbefore, successive etch depths are weighted in accordance with a binary sequence (i.e in the ratio 1:2:4). The step height t/7 defines the minimum etch depth required, and this is applied in the first stage (I) of the etch process, and the etch depths for the second (II) and third (III) stages in the process take the values 2/7t and 4/7t respectively.
The etch period corresponding to each etch depth is determined by timing complete removal of the epitaxial layer from a test wafer and calculating the appropriate proportion of the measured period.
It will be appreciated that the dark and clear areas of each shadow mask are so arranged as to mask zones 0 to 7 of the epitaxial layer in accordance with the scheme set out in Table 1 thereby to generate a stepped edge region as shown in Figures 2 and 4. Thus, for example, zone 6 of the epitaxial layer is subjected to etching during the second and third stages only of the process. The etch depths which apply in the second and third stages are 2/7t and 4/7t respectively and so the total etch depth attained is 6/7t, so that the level produced in zone 6 occurs at a depth 6/7ths of the way through the epitaxial layer.
It will be understood that although the above-described method is applicable to the fabrication of an electrical device such as a
MOS devices, for example a MOSFET-based chemical sensors, including GasFET devices, the present invention is considered to be applicable generally to the fabrication of discrete components including circuits. The invention is likely to find application in the field of silicon micromachining, for the production of components having specific topologies, for example tapered or wedge-shaped films and components having precisely defined features such as grooves, pits and depressions. Substantially pyramidal, domed or hemi cylindrical components produced by the method of this invention could find application in integrated optics, such as a micro lens or waveguide, for example. The invention is also applicable to
Langumuir-Blodgett device technology.
Claims (10)
1. A method for manufacturing a component, the method including etching a layer of a material in accordance with each of a number of differently shaped patterns thereby to produce an edge region consisting of a series of discrete step formations arranged at successive levels in the layer.
2. A method according to Claim 2 including etching said layer in accordance with n differently shaped patterns through successive intervals of depth weighted in accordance with a binary sequence, whereby said edge region consists of 2n~1 of said discrete steps.
3. A method according to Claim 1 or Claim 2 including depositing a further layer on said edge region.
4. A component produced by a method according to any one of Claims 1 to 3.
5. A component according to Claim 4 in the form of a metal-oxide-semiconductor field effect transistor wherein said layer of a material comprises a field oxide layer, said edge region bounds a contact region formed in the field oxide layer and said further layer comprises a metallisation for establishing an electrical contact with a surface exposed by said contact region.
6. A component according to Claim 5 wherein said contact region is a contact hole which exposes a drain, source or semiconductor bulk region of the device.
7. A component according to Claim 5 wherein said contact region exposes a gate insulation layer of the device.
8. A component in the form of an electrical device including a layer of a first material having an edge region, and a layer of a second material overlying said edge region, wherein said edge region comprises a series of discrete, step formations arranged at successive levels in said layer of a first material.
9. A method for manufacturing a component substantially as hereinbefore described by reference t6 Figures 2 to 4 of the accompanying drawings.
10. A component substantially as hereinbefore described by reference to Figures 2 to 4 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB868624637A GB8624637D0 (en) | 1986-10-14 | 1986-10-14 | Electrical device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8723676D0 GB8723676D0 (en) | 1987-11-11 |
| GB2196476A true GB2196476A (en) | 1988-04-27 |
| GB2196476B GB2196476B (en) | 1990-02-14 |
Family
ID=10605738
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB868624637A Pending GB8624637D0 (en) | 1986-10-14 | 1986-10-14 | Electrical device |
| GB8723676A Expired - Lifetime GB2196476B (en) | 1986-10-14 | 1987-10-08 | A method for manufacturing a component and a component produced by the method |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB868624637A Pending GB8624637D0 (en) | 1986-10-14 | 1986-10-14 | Electrical device |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB8624637D0 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0353693A2 (en) * | 1988-08-01 | 1990-02-07 | Fujitsu Limited | Compound semiconductor mesfet device |
| US5489678A (en) * | 1989-06-07 | 1996-02-06 | Affymax Technologies N.V. | Photolabile nucleoside and peptide protecting groups |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6379895B1 (en) | 1989-06-07 | 2002-04-30 | Affymetrix, Inc. | Photolithographic and other means for manufacturing arrays |
| US6309822B1 (en) | 1989-06-07 | 2001-10-30 | Affymetrix, Inc. | Method for comparing copy number of nucleic acid sequences |
| US5143854A (en) | 1989-06-07 | 1992-09-01 | Affymax Technologies N.V. | Large scale photolithographic solid phase synthesis of polypeptides and receptor binding screening thereof |
| US5800992A (en) | 1989-06-07 | 1998-09-01 | Fodor; Stephen P.A. | Method of detecting nucleic acids |
| US6551784B2 (en) | 1989-06-07 | 2003-04-22 | Affymetrix Inc | Method of comparing nucleic acid sequences |
| US6406844B1 (en) | 1989-06-07 | 2002-06-18 | Affymetrix, Inc. | Very large scale immobilized polymer synthesis |
| US6346413B1 (en) | 1989-06-07 | 2002-02-12 | Affymetrix, Inc. | Polymer arrays |
| US5424186A (en) | 1989-06-07 | 1995-06-13 | Affymax Technologies N.V. | Very large scale immobilized polymer synthesis |
| US6506558B1 (en) | 1990-03-07 | 2003-01-14 | Affymetrix Inc. | Very large scale immobilized polymer synthesis |
| EP1231282A3 (en) | 1990-12-06 | 2005-05-18 | Affymetrix, Inc. | Methods and compositions for identification of polymers |
| US6468740B1 (en) | 1992-11-05 | 2002-10-22 | Affymetrix, Inc. | Cyclic and substituted immobilized molecular synthesis |
| US6545264B1 (en) | 1998-10-30 | 2003-04-08 | Affymetrix, Inc. | Systems and methods for high performance scanning |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1048424A (en) * | 1963-08-28 | 1966-11-16 | Int Standard Electric Corp | Improvements in or relating to semiconductor devices |
| GB1146754A (en) * | 1965-10-01 | 1969-03-26 | Texas Instruments Inc | Electron beam evaporated quartz insulating material |
| GB1193868A (en) * | 1966-06-30 | 1970-06-03 | Texas Instruments Inc | Ohmic Contacts for Semiconductor Devices |
| GB1232286A (en) * | 1967-06-20 | 1971-05-19 | ||
| US3667005A (en) * | 1966-06-30 | 1972-05-30 | Texas Instruments Inc | Ohmic contacts for semiconductors devices |
| GB1488151A (en) * | 1973-08-29 | 1977-10-05 | American Micro Syst | Field effect devices |
| GB1552757A (en) * | 1977-02-16 | 1979-09-19 | Siemens Ag | Mis-field effect transistors |
| GB2042805A (en) * | 1979-02-22 | 1980-09-24 | Rca Corp | Multi-step mesa |
| EP0037115A1 (en) * | 1980-03-31 | 1981-10-07 | Siemens Aktiengesellschaft | Planar semiconductor with increased breakdown voltage |
| EP0069429A2 (en) * | 1981-07-06 | 1983-01-12 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
-
1986
- 1986-10-14 GB GB868624637A patent/GB8624637D0/en active Pending
-
1987
- 1987-10-08 GB GB8723676A patent/GB2196476B/en not_active Expired - Lifetime
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1048424A (en) * | 1963-08-28 | 1966-11-16 | Int Standard Electric Corp | Improvements in or relating to semiconductor devices |
| GB1146754A (en) * | 1965-10-01 | 1969-03-26 | Texas Instruments Inc | Electron beam evaporated quartz insulating material |
| GB1193868A (en) * | 1966-06-30 | 1970-06-03 | Texas Instruments Inc | Ohmic Contacts for Semiconductor Devices |
| US3667005A (en) * | 1966-06-30 | 1972-05-30 | Texas Instruments Inc | Ohmic contacts for semiconductors devices |
| GB1232286A (en) * | 1967-06-20 | 1971-05-19 | ||
| GB1488151A (en) * | 1973-08-29 | 1977-10-05 | American Micro Syst | Field effect devices |
| GB1552757A (en) * | 1977-02-16 | 1979-09-19 | Siemens Ag | Mis-field effect transistors |
| GB2042805A (en) * | 1979-02-22 | 1980-09-24 | Rca Corp | Multi-step mesa |
| EP0037115A1 (en) * | 1980-03-31 | 1981-10-07 | Siemens Aktiengesellschaft | Planar semiconductor with increased breakdown voltage |
| EP0069429A2 (en) * | 1981-07-06 | 1983-01-12 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0353693A2 (en) * | 1988-08-01 | 1990-02-07 | Fujitsu Limited | Compound semiconductor mesfet device |
| EP0353693A3 (en) * | 1988-08-01 | 1991-11-06 | Fujitsu Limited | Compound semiconductor mesfet device |
| US5489678A (en) * | 1989-06-07 | 1996-02-06 | Affymax Technologies N.V. | Photolabile nucleoside and peptide protecting groups |
| US5744101A (en) * | 1989-06-07 | 1998-04-28 | Affymax Technologies N.V. | Photolabile nucleoside protecting groups |
| US5744305A (en) * | 1989-06-07 | 1998-04-28 | Affymetrix, Inc. | Arrays of materials attached to a substrate |
| US5889165A (en) * | 1989-06-07 | 1999-03-30 | Affymetrix, Inc. | Photolabile nucleoside protecting groups |
| US6124102A (en) * | 1989-06-07 | 2000-09-26 | Affymetrix, Inc. | Methods for determining receptor-ligand binding using probe arrays |
| US6600031B1 (en) * | 1989-06-07 | 2003-07-29 | Affymetrix, Inc. | Methods of making nucleic acid or oligonucleotide arrays |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2196476B (en) | 1990-02-14 |
| GB8624637D0 (en) | 1986-11-19 |
| GB8723676D0 (en) | 1987-11-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19991008 |