GB2194085A

GB2194085A - Bus

Info

Publication number: GB2194085A
Application number: GB08716705A
Authority: GB
Inventors: Kevin Daryl Blackmore; Adrian William Walker
Original assignee: GEC Avionics Ltd
Current assignee: Allard Way Holdings Ltd
Priority date: 1986-07-24
Filing date: 1987-07-15
Publication date: 1988-02-24
Anticipated expiration: 2007-07-15
Also published as: GB2193019A; GB8618060D0; GB8716706D0; GB8716705D0; GB2194085B

Abstract

A bus arrangement which is particularly suitable for use with systems involving transputers is disclosed, which bus is a two wire bus connected to the one pair of the INMOS link connections on a transputer (RTM), 4. Spur lines are taken off the bus to other transputers in a system, which transputers may form part of physically separate circuits or modules. These spurs are fed through link selectors which examine a part of messages present on the line to decide whether that message is intended for that particular transputer. If so, the link selector allows messages to be passed to and from that particular transputer. <IMAGE>

Description

GB2194085A 1 SPECIFICATION any data present on the bus with a known

address of that transputer and, if the address Bus received is that of the transputer, to enable the buffer to allow the transputer to transmit This invention relates to a bus of the type 70 and receive data.

which provides a communication channel be- Preferably the decoding means comprises a tween electronic circuits, and in particular it link adapter arranged to convert data from se relates to a bus for providing a bi-directional rial form.on a two wire bus into parallel form, communication channel between a plurality of and a comparator adapted to compare the transputers or between a plurality of separate 75 parallel data from the link adapter with a modules or units at least some of which in- known address for that transputer.

clude a transputer (RTM). The term link adapter is one known in the A transputer is an integrated circuit manu- art and is a device such as that known as factured by INMOS Limited and is essentially a INMOS device COO1, C002 or C012 which micro computer with its own local memory 80 are normally adapted to provide an interface and with standard links for connecting one between an INMOS serial link and a micro transputer to another transputer in a network. processor system bus, via, for example, an 8 A transputer includes a number usually four, bit bi-directional interface.

of standard links, known as INMOS links, each In addition to the link in and link out con- comprising two wires and providing two unidinections a transputer also includes event re rectional communication channels. These links quest and event acknowledgement connec have been designed to implement the standard tions. These may be utilised in preferred em inter-transputer communication protocol be- bodiments of the invention, in which the first tween transputers mounted in a circuit, which transputer is arranged to generate messages may be connected in a grid like array fashion. 90 of which the first chosen number of bytes The normal inter-transputer protocol does not represent the address for which that message allow one transputer to communicate with is intended. The comparator at each transpu more than one other transputer over one link. ter can be fed an appropriate signal via the Hence, current architectures linking transputers event request and event acknowledgement in an array are limited to each transputer be- 95 connections at appropriate times when it is ing linked to up to four others. Furthermore, required to scan the message to compare the the standard links have only been envisaged address bytes, Alternatively, other methods as links between transputers mounted close to may be used to instruct the decoder when to each other on the same circuit. begin decoding part or the whole of a mes- For linking physically separate modules or 100 sage.

circuits some form of bus arrangement must The transputers may each be associated be used. In conventional micro computer ar- with a physically separate module and circuit chitectures, including conventional transputer and, in a preferred embodiment, up to 8 sepa micro computer architectures, these bus links rate modules may be connected by the two are complex and involve many wires, generally 105 wire bus as described. The size of the system in the form of ribbon cables, to communicate may however be extended if necessary.

between the separate circuit boards or mo- Embodiments of the invention will now be dules. The standard VME bus for instance described by way of example only with refer uses a 96 wire connector. Clearly, the greater ence to the accompanying drawings in which:

number of wires in a link the higher the 110 Figure 1 shows schematically a bus arrange- chances of an error occurring and also accu- ment according to the present invention.

rate timing signals must be provided. Figure 2 shows in more detail the connec- According to the present invention in a first tion of one transputer in the network to the aspect there is provided a method for bidirec- bus.

tional communication between physically sepa- 115 Referring to Figure 1, there is shown sche- rate electronic circuits, or modules, wherein matically the general bus arrangement accord the standard links provided by a transputer ing to the present invention which is essen are used as communication paths between the tially a two wire bus 1 and 2 connected to separate circuits such that there is essentially the link in and link out pins respectively of a a two wire connection between each circuit or 120 control transputer 3 such as INMOS device module. number IMS T414. The control transputer 3 In a second aspect of the present invention may be part of a control module or circuit for there is provided apparatus for providing bi- transmitting or receiving messages to or from directional communication between a plurality other physically separate modules. Outputs are of transputers, comprising a two wire bus; 125 taken from the bus line to respective transpu connections via respective buffers between ters 4 (T, to T.). Typically, each transputer each wire of the bus and the link in and link will form part of a separate module and in out connections of one pair of INMOS links of preferred embodiments thbre may be up to each transputer; and decoding means at each eight such modules, the input or output to transputer adapted to compare at least part of 130 each of which is controlled by the respective 2 GB2194085A 2 transputer. The links to the respective tran- comprise 32 words, made up of valid data sputers are fed through respective link selec- followed by dummy data if the length of real tors 5 (L, to I-j. These link selectors function, data is insufficient to fill the message. The in a manner which will become clear, to de- first byte of the message can define the ad cide, for each message which is present on 70 dress of the receiving transputer and the num the bus, whether that message is intended for ber of valid bytes in the message. For a sys receipt by that particular transputer. If so then tem having eight transputers linked to the the link selector serves to open a communi- control transputer, bits D.-D, may define the cation channel which allows that particular receiving transputer and bits D,-D7 can define transputer to receive or transmit data. Nor- 75 the number of valid data bytes in the mes mally the link selectors present a high impesage.

dance path which functions to close down any In these circumstances, the link selecters are communication channels so that the appropri- programmed to examine the Ist 33rd, ate respective transputer can not transmit or 65th n x 32 + 1 byte being transmitted receive data. In this manner the INMOS links 80 along the bus, and then to decide by compar associated with each transputer can be used ing these bytes against known programmed accordi 9 to the normal INMOS link protocol addresses within the selector whether to re in which one transputer may only communi- main high impedance or whether to open the cate with one other transputer over one link communication path for the next 31 bytes be but with the important difference that com- 85 fore returning to a high impedance-bus moni munication may be freely switched between toring state.

transputers and hence between modules or In this particular embodiment, since the link units as appropriate. selectors must only be programmed to exam- Figure 2 shows more clearly how the link ine particular bytes within the message, an selector works for a particular transputer moadditional timing line would be required along dule. Connections from the two wire bus are with the bus in order to provide synchronisa fed via buffers 6 and 7 to the link in and link tion signals to the decoder 9 and to tell it out inputs of transputer 4. A parallel path is precisely when to examine a particular byte.

also taken from the bus through a link adapter Outputs can be taken from the timing line into 8 and a decoder 9 which may comprise 95 the event request pin of a transputer and an merely a comparator circuit. The link adapter output taken from the event acknowledgement can be one of the devices manufactured by pin to the decoder. The last mentioned pins INMOS limited and may be for example one of are specifically designed for timing applications INMOS device numbers IMS C001 C002 or such as this.

C012. Essentially these devices are used in 100 However, some embodiments of the present embodiments of the present invention to con- invention will not need the additional timing vert from serial data along the two wire stan- sync line since messages could for example dard INMOS link into eight bit parallel data be transmitted in pulses with messages could which would, in more conventional architec- for example be transmitted in pulses with tures be applied to a parallel bus line or as an 105 gaps between the pulses which serve to set input to a micro processor or other such perthe decoders or alternatively any other suitable ipheral. The parallel data is in fact, in this arrangement may be used. Messages could in embodiment, input to the decoder 9. clude for example flag data recognisable by The decoder is programmed or otherwise the link selectors and instructing them to be- supplied with details of an address which is 110 gin decoding.

unique to that particular module. The decoder

Claims

provides a comparison function upon certain CLAIMS chosen portions of any

message present on 1. A method for bi-directional communi- the bus at any time. If a message is intended cation between physically separate electronic for that particular module then the decoder 115 circuits or modules, wherein the standard link will read the correct address, decide that the INMOS links provided by a transputer are used module has been selected and serve to enable as communication paths. between the separate buffers 6 and 7 such that communication can circuits such that there is essentially a two occur over lines 10 and 11. Normally the wire connection between each circuit or mo buffers 6 and 7 are disabled such that no 120 dule.

data can flow along lines 10 and 11 and all
2. Apparatus for providing bidirectional data is routed to adapter 8 and decoder 9 communication between a plurality of transpu which present a high impedence path to the ters, comprising; a two wire bus; connections bus and hence block the flow of data to or via respective buffers between each wire of from transputer 4. 125 the bus and respective ones of respective IN- A suitable communication protocol for com- MOS link connections of one pair of INMOS munication between the control transputer 3 links of each transputer; and decoding means and any one of the other transputers within at each transputer adapted to compare at the network is to transmit messages from the least part of any data present on the bus with control transputer which messages typically 130 a known address of that transputer and, if the 3 GB2194085A 3 address received is that of the transputer, to enable the buffers to allow the transputer to transmit and receive data.
3. Apparatus as claimed in claim 2 wherein each transputer forms part of a physically se- parate electronic circuit or module.
4. Apparatus as claimed in claim 2 or claim 3 wherein the decoding means comprises a link adapter arranged to convert data from se- rial form into parallel form and a comparator arranged to compare the parallel data from the link adapter with a known system address for that transputer.
5. Apparatus as claimed in any of claims 2 to 4 and further including a timing line upon which signals instructing the decoding means to begin decoding part of a message may be applied.
6. A micro processor bus arrangement sub- stantially as hereinbefore described with refer- ence to and as illustrated by, the accompany ing drawings.

Published 1988 at The Patent office, State House, 66/71 High Holborn, London WC 1 R 4TP. Further copies may be obtained from The Patent Office, Sales Branch, St Mary Cray, Orpington, Kent BR5 3RD, Printed by Burgess & Son (Abingdon) Ltd. Con. 1/87.