GB2192506A

GB2192506A - Demodulation circuit

Info

Publication number: GB2192506A
Application number: GB08617027A
Authority: GB
Inventors: Peter Alan Ramsdale; Philip Stuart Gaskell
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1986-07-12
Filing date: 1986-07-12
Publication date: 1988-01-13
Anticipated expiration: 2006-07-12
Also published as: GB2192506B; GB8617027D0

Abstract

A zero IF receiver for data received as FSK demodulates in a series of steps: (i) I and Q signals which are in phase quadrature are derived 2-5; (ii) the I and Q signals are digitised 6,7; (iii) the I and Q signals as digitised are used to produce R (amplitude) and theta (phase) signals, which together define the modulation. In the present arrangement, the I and Q signals are derived to more than one-bit accuracy, and the plural bit digitised I and Q signals are used to access look-up tables 10 which give the theta signal, and possibly also the R signal. Then the theta and R signals together define the modulation. This is usable to detect data transmitted in radio pagers, cellular telephones, and cordless telephones. <IMAGE>

Description

SPECIFICATION Demodulation circuit The present invention relates to a demodulation circuit for use in a zero-lF radio receiver. A demodulation circuit for such a receiver is described in our British Patent Specification No. 2149244A (I.A.W. Vance 17).

The demodulation circuit of the above Patent Specification is used in a radio receiver for frequency shift keyed (FSK) signals, used, for instance, in a radio pager. A simplified block diagram of such a receiver is shown in Figure 1 of the accompanying drawings.

The Rf carrier, modulated by FSK signals, from the aerial 1 are mixed in two high-gain mixers 2 and 3 with signals from a local oscillator 4 whose frequency is at the nominal centre frequency of the RF signal. The output of the oscillator is applied directly to the mixer 2, and via a quadrature phase shifter 5 to the mixer 3.

The outputs of the mixers are low pass filtered to produce signals I and Q which are in phase quadrature, with the 0 signal lagging or leading the I signal, dependent on whether the signal frequency is above or below the nominal centre frequency.

The signals I and Othus produced are applied via respective baseband filters to analogue-digital converters 6 and 7 respectively, and the digital versions of these signals are applied to a digital signal processor 8, which derives the 6 and R signals from which the original modulation is obtained. Note that the û and R signals represent the phase and amplitude respectively of the modulation signal.

The derivation of the 0 and R signals from the I and Q signals involves the performance of the following operation by the processor 8: 6 = tan -1

In data modulation arrangements, the two logic states are represented by two distinct conditions of the modulated radio signal. This has been used particularlyforwide-deviation FSK, where the relative positions of pulse edges in amplitude-limited I and Q data streams, or 1-bit ADC streams, are different for the two logic states.

Although such demodulators are useful, they do have certain disadvantages. Thus they do not exploit all the desirable features of the modulation technique, and they are only appropriate to a limited set of data modulations. For example, rejection of co-channel signals is poor because an FM advantage mechanism is not exploited. Further, the modulation characteristics must be such as to generate adequate zero crossings for proper modulation.

An object of the present invention is to provide an improved demodulation arrangement in which the above disadvantages are minimised.

According to the invention there is provided a demodulator circuit for receiving a signal modulated by binary frequency or phase modulation, in which the signal to be demodulated is mixed with the output of a local oscillator to produce quadrature channels, there being a first channel in which the difference frequency (I) between the local oscillator frequency and the received signal frequency appears and a second channel in which the difference frequency (Q) is in phase quadrature with respect to the difference frequency (i) in the first channel, in which the frequency (0) in the second channel lags or leads on the frequency (!) in the first channel, dependent on the signal frequency being above or below the local oscillator frequency, in which the difference frequencies thus produced are digitised and the respective digital representations of the I and Q signals are processed to produce the modulation signal, in which the digitisation is effected in such a way as to give results with greater than 1 -bit accuracy, and in which the processing of the digitised representations of the I and Q signals to obtain the modulation signal involves the use of a look-up table in memory, which look-up table is accessed under the control of said digitised representations.

Such a demodulation method is applicable to several forms of data modulation, i.e. binary frequency or phase modulation. However, it is described herein as applied to dealing with the reception of FSK signals.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which Figures 2, 3 and 5 show in block diagram form various demodulation circuits embodying the invention, and Figure 4 is an explanatory drawing.

The concept on which the operations of the arrangements to be described below is based is to digitise the I and Q channel signals in the analogue-to-digital converters to greater than 1-bit accuracy, and to use a look-up table such as a ROM to provide the value of û to an appropriate resolution. This is facilitated by the availability of simple and inexpensive analogue to digital converters, and the recognition that the look-up ,table requires a comparatively small number of input and output bits for effective demodulation of the data.

The use of a single look-up table avoids a series of calculations or individual function look-ups which have previously been used to calculate tan-' (O)/I to the accuracy needed. Access to a single value look-up table can be rapid, and also consumes little power.

In Figure 2, the I and Q signals are applied to a look-up table 10, e.g. a ROM, so that û is looked up for each unique combination of I, Q values. û is then differentiated by subtracting from it the previous value thereof to give û0û. This is represented by 6. This result 6 is applied to the demodulator's output via a decision circuit 12, whose output is the demodulated FSK signal. This output changes state when û moves quickly through 180 .

The decision circuit 12 regenerates the original modulation signal. It may vary in complexity from a simple threshold ci rcuit to more sophisticated circuits using, for example, signal interpolation and data clock regeneration.

In the arrangement of Figure 3, the I and Q channel signals are applied to a quadrant logic circuit 20 in which the "width" of the input words is reduced by restricting the range of û to 0"-90". This range may be further restricted to 0-45" by deriving I' and Q', where l'=l, and Q'=Q, when 12Q, and l'=Q and Q'=l when l < Q. This uses a so-called octant logic circuit indicated at 20a.

Hence a 45 look-up table 21 is used to respond to the newly-derived I' and Q' signals from the circuit 20. The output for the look-up table 21 is applied to an adder 22, controlled from the circuit 20, and also from an octant logic circuit 20a (if provided) to reinsert the octant offset angle. There follows the subtractor 23 and in turn the threshold circuit 24. These latter are similar to the equivalent devices of Figure 2 This range reduction enables a smaller look-up table to be used than in the case for Figure 2.

The relation between I' and Q', and the maximum and minimum value of I' can be seen from Figure 4, and this will be referred to below.

The look-up table size can be further reduced by using prior knowledge of the dynamic range of the signal after the front-end AGC. Having ensured that the I and 0 signals are converted, as described above, to I' and Q' such that tan~l Q 4 450 the value I' need only be coded to represent a range of values from 1,mien to 1,may' as indicated in Figure 4. This leads to a reduction in the memory size needed to represent the values of 0 needed. NAND-ing the unused data lines from I' also provides a simple "below range" flag.

In the highly schematic Figure S,the number of inputs is doubled by taking pairs of successive values of I and Qto enable FSK to be output from a single look-up table without the intermediate calculation of û.

In the arrangements described above, û is determined to the resolution of the input signals or thereabouts, and determination of one of two states made afterwards. This contrasts with the known 1 bit analogue-digital conversion (limiting amplifier) arrangements, where the reduction to this resolution occurs prior to the calculation of û.

Many receivers need some monitoring of signal amplitude for an S meter indicating field strength or for AGC control. By using à wider word stored in the look-up table, a single access can output both amplitude and phase.

The arrangements described above are usable, in addition to radio pagers, in cellular radio systems, cordless telephones, and data systems.

As already indicated, although the invention has been described in its application to the reception of FSK signals, it is applicable also to the reception of other forms of modulation, such as binary modulated frequency or phase modulation.

Claims

1. A demodulator circuit for receiving a signal modulated by binary, frequency or phase modulation, in which the signal to be demodulated is mixed with the output of a local oscillator to produce quadrature channels, there being a first channel in which the difference frequency (I) between the local oscillator frequency and the received signal frequency appears and a second channel in which the difference frequency (Q) is in phase quadrature with respect to the difference frequency (I) in the first channel, in which the frequency (Q) in the second channel lags or leads on the frequency (I) in the first channel, dependent on the signal frequency being above or below the local oscillator frequency, in which the difference frequencies thus produced are digitised and the respective digital representations of the I and 0 signals are processed to produce the modulation signal, in which the digitisation is effected in such a way as to give results with greater than 1-bit accuracy, and in which the processing of the digitised representations of the land Q signals to obtain the modulation signal involves the use of a look-up table in memory, which look-up table is accessed under the control of said digitised representations.

2. A demodulator circuit for an FSK signal, in which the signal to be demodulated is mixed with the output of a local oscillatorto produce quadrature channels, there being a first channel in which the difference frequency (I) between the local oscillator frequency and the received signal frequency appears and a second channel in which the difference frequency (Q) is in phase quadrature with respect to the difference frequency (I) in the first channel, in which the frequency (0) in the second channel lags or leads on the frequency (I) in the first channel, dependent on the signal frequency being above or below the local oscillator frequency, in which the difference frequencies thus produced are digitized and the respective digital representations of the I and 0 signals are processed to produce the modulation signal, in which the processing involves the production of an R signal representing the amplitude of the modulation signal and a 6 signal representing the phase angle of the modulation signal, which R and 6 signals are used to derive the modulation signal, in which the digitisation of the I and 0 signals is effected in such a way as to give results with greater than 1-bit accuracy, and in which the value of the 6 signal is obtained by the use of a look-up table stored in a memory, which memory is accessed using the digitised values of the I and Q signals as look-up table addresses to obtain a read-out representative of the value of the 6 signal.

3. A demodulator as claimed in claim 2, and in which the look-up table is also used to provide the R signal.

4. A demodulator as claimed in claim 2 or 3, in which when the value of the 6 signal has been determined a subtraction is effected between the current value of 6 and the preceding value of 6, the difference 6 thus derived being used in said processing.

5. A demodulator as claimed in claim 4, and in which the value 6 is applied to a decision circuit included in the processing means, which decision circuit is of the threshold detection type.

6. A demodulator as claimed in claim 2,3,4 or 5, in which the processing is simplified by restricting the range of values of 6 to be dealt with by the use of quadrant and/or octant logic circuits.

7. A demodulator as claimed in claim 6, in which the dynamic range of the signal Q or a signal Q' derived therefrom is used to further reduce the address space of the look-up table.

8. A demodulator circuit as claimed in claim 1, in which a single look-up table is used to determine the modulation signal on the basis of successive pairs of values of I and Q.

9. A demodulator circuit as claimed in claim 2 or in any claim appendent thereto, in which the value R is also used to control automatic gain control when the demodulator circuit is used in a radio receiver.

10. A demodulator circuit for a radio receiver, substantially as described with reference to Figures 2,3 or 5 of the accompanying drawings.

11. A radio receiver which includes a demodulator circuit as claimed in any one of the preceding claims.

Amendments to the claims have been filed, and have the following effect: An additional claim has been filed as follows:

12. A demodulator circuit for an FSK signal, in which the signal to be demodulated is mixed with the output of a local oscillator to produce quadrature channels, there being a first channel in which the difference frequency (I) between the local oscillator frequency and the received signal frequency appears and a second channel in which the difference frequency (0) is in phase quadrature with respect to the difference frequency (I) in the first channel, in which the frequency (Q) in the second channel lags or leads on the frequency (I) in the first channel, dependent on the signal frequency being above or below the local oscillator frequency, in which the difference frequencies thus produced are digitized and the respective digital representations of the I and Q signals are processed to produce the modulation signal, the digitisation of the I and 0 signals being effected in such a way as to give results with greater than 1-bit accuracy, in which the signal processing involves the production of an R signal representing the amplitude of the modulation signal and a 6 signal representing the phase angle of the modulation signal, which R and 6 signals are used to derive the modulation signal, in which the value of the 6 signal is obtained by the use of a look-up table stored in a memory, which memory is accessed using the digitised values of the I and Q signals as look-up table addresses to obtain a read-out representative of the value of the 6 signal, in which the look-up table is also used to provide the R signal, and in which the signal processing is simplified by restricting the range of values of 6 to be dealt with by the use of quadrant and/or octant logic circuits.