GB2188519A - Graphics display apparatus - Google Patents

Abstract

A digitally operable graphics display apparatus provides a bit-map display on a CRT display device in accordance with digital information stored in a display memory e.g. 3D coordinates of primitives, this digital information is updated rapidly (e.g. within one frame period of the CRT raster scan) by using a plurality of processors P1 to P10 each of which provides computing for m/n pixel rows, where m is the total number of pixel rows and n is the number of processors, with the pixel rows allotted to each processor being separated from each other by n-1 other pixel rows. The apparatus may be used to provide real time movement (or animation) of an object in the overall graphics image. <IMAGE>

Description

SPECIFICATION Graphics display apparatus This invention relates to digitally operable graphics display apparatus for displaying on the screen of a raster scan display device a graphics image which is represented by digital information stored in a display memory, the graphics image being displayed as a matrix of discrete pixels, each of which pixels has its colour and/or luminance defined by digital information stored in the display memory at a location corresponding to the position of the pixel in the display, the apparatus including processor means for controlling digitally the storage, selection and generation of data for producing the graphics image display.

The display produced by apparatus of the above type is termed a bit-map display, and is, for example, a 360 x 280 resolution pixel (dot) matrix colour display. The digital information stored in the display memory is accessed repeatedly by the processor means to update the display in a recurrent cycle of scanning lines which may be produced with or without interlaced field scanning.

A problem that is encountered with such bit-map displays on a raster scan display device is to be able to produce real time move- ment (or animation) of an object in the overall graphics image display, because in order to achieve each movement it becomes necessary for the processing means to alter the contents of the display memory in respect of the object within one frame period of the raster scan.

One approach to this problem has been to use multiple co-operating processors as the processing means. For this approach, the display screen of the display device is divided notionally into a plurality of horizontal display areas each composed of a given number of pixel rows, and one processor is allotted to each area and is operable to provide the computing which is necessary to process the digi tal information in the display memory for the data in the appertaining display area. However, unless the computing load is shared by a large number of processors, this load may be distributed unevenly between the processors when it is concentrated only in one or two adjacent horizontal areas.Therefore, a large number of co-operating processors has hitherto been used in order to ensure that no single processor is so over-loaded as to be unable to carry out the logic operations required of it in the time available. This requirement tends to make this known approach to the problem cumbersome and impractical.

It is an object of the present invention to provide a practical solution to the above problem.

According to the present invention, digitally operable graphics display apparatus of the type set forth above, in which the processing means comprises a plurality of co-operating display processors, is characterised in that said processors are so organised that each provides computing for m/n pixel rows, where m is the total number of pixel rows and n is the number of processors, with pixel rows allotted to each processor being separated from each other by n-l other pixel rows.

In carrying out the invention, the apparatus may include a central processor which is operable to distribute to the display processors the data to be processed for their allotted pixel rows.

This organisation of the processors in accordance with the invention provides an interleaved allocation of the pixel rows to the processors and thus an interleaved distribution of the computing load. This gives the advantage that the computing load required for dealing with a small detailed object in the overall graphics image display will be handled by several of the processors, even when the processing means comprises only a relatively small number of processors.

In further considering the nature of the invention, reference will now be made by way of example to the accompanying drawings, of which: Figure 1 shows diagrammatically a graphics display apparatus in which the present invention can be embodied; Figure 2 shows diagrammatically the distribution of computing load for a plurality of processors by the interleaved allocation of pixel rows thereto in accordance with the invention; and Figure 3 shows diagrammatically an implementation of the invention in respect of a simple primitive triangle which represents a triangular face displayed in three dimensions.

Referring to the drawings, the graphics display apparatus shown in Fig. 1 comprises a raster scan display device 1, a display memory 2, a plurality of display processors 3, a central processor 4, a background memory 5 an arithmetic unit 6, three digital-to-analogue converters 7, 8 and 9 and user interface devices 10 and 11 which may be, respectively, a keyboard and a writing tablet.

The raster scan display device 1 is suitably a colour television monitor which is connected to receive R, G, B video signals from the three digital-to-analogue converters, 7, 8 and 9 respectively. These converters are driven by digital signals read out from the display memory 2 in synchronism with the raster scanning cycle of the display device 1.

The background memory 5 contains descriptions of a large number of different objects which can be selected under the control of the central processor 4 to produce a graphics image display in accordance with instructions received from the user interface devices 10 and 11. These object descriptions are in the form of sets of vertices which define primi tives that are used in combinations to makeup objects for display. In this respect, it is now well-established in the art that any three dimensional object for display can be approximated by a suitably shaped polyhedron. Such a polyhedron can be modelled by defining each of its faces as a planar polygon and each of the faces, in turn, can be modelled by a plurality of planar triangular faces which, finally, can be represented by an ordered list of vertices.

The object descriptions for an object selected for display are read from the background memory 5 and applied to the arithmetic unit 6 where these object descriptions are subjected to translation algorithms to undergo rotation, scaling, lighting, perspective, and clipping changes appropriate for displaying the object in the desired three-dimensional orientation. The book "Principles of Interactive Computer Graphics", by W.M. Newman and R.F. Sproull, published by McGraw Hill, 1979, gives a general state of the art on graphics image displays.

The plurality of processors 3 are involved jointly in the processing performed in the arithmetic unit 6. In accordance with the invention this involvement is such that so-called scan-conversation of the modified object descriptions into the digital (pixel) information which is stored in the display memory 2 is effected by arranging that each processor of said plurality provides computing for m/n pixel rows, where m is the total number of pixel rows and n is the number of processors, with the pixel rows allotted to each processor being separated from each other by n-l other pixel rows. This distribution of computing load is illustrated in Fig. 2.

It is assumed for the purposes of the present invention that the display device 1 provides a 360 x 280 resolution pixel matrix display and that there are ten separate but mutually co-operating display processors. In Fig. 2, this pixel matrix display is represented at PMD by the horizontal pixel rows 0 to 9, 120 to 129 and 350 to 359. Fig. 2 also shows ten separate processors P1 to P10, together with a central processor CP which corresponds to the central processor 4 in Fig. 1.The allocation of the pixel rows of the display to the ten processors P1 to P10 is interleaved, that is, as illustrated, the display information for pixel rows 0 to 9 is dealt with by the processors P1 to P10, respectively; as is the display information for the pixel rows 60 to 99, respectively, and 350 to 359, respectively. The allocation is the same for the other pixel rows, not shown, as that each display processor deals with the display information for only every tenth pixel row.The result of this allocation is that the overall computing load involved in producing the display is distributed evenly amongst the ten display processors P1 to P10 Fig. 3 illustrates the distribution of the computing load for a single primitive triangle T which is displayed in a three dimensional orientation.

This triangle T has three modified vertices A, B and C, each of which comprises three components xayaza, xaybza and xayczc by which the triangle is given a size, perspective and three-dimensional orientation as it is to be displayed. Within the limits of the resolution of the display, this triangle T is displayed as a solid graphics figure comprised of discrete pixels, as shown at TD. In order to achieve this display, the modified vertices components are translated into sets of data for horizontal pixel portions hl to h12 each of which is one pixel high and of a lerigth which is specified by end points (pixels). Because these horizontal pixel portions have to be located in the display, the set of data for each includes the number of the pixel row in which it is to be displayed together with data for setting the horizontal pixel portion at the appropriate position in the row. The set of data for each horizontal pixel portion also includes data giving the effective gradient of the portion as viewed from above in dependence on the three-dimensional orientation of the triangle. These sets of data for the horizontal pixel portions are dealt with by respective ones of the display processors P1 to P10 in accordance with the interleaved allocation of the computing load for these processors as shown in Fig. 2. The digital (pixel) codes which are produced for the display are then written by the display processor into the display memory 2.

Claims (3)

1. Digitally operable graphics display apparatus for displaying on the screen of a raster scan display device a graphics image which is represented by digital information stored in a display memory, the graphics image being displayed as a matrix of discrete pixels, each of which pixels has its colour and/or luminance defined by digital information stored in the display memory at a location corresponding to the position of the pixel in the display, the apparatus including a plurality of display processors for controlling digitally the storage, selection and generation of data for producing the graphics image display, characterised in that said plurality of processors are so organised that each provides computing for m/n pixel rows, where m is the total number of pixel rows and n is the number of processors, with the pixel rows allotted to each processor being separated from each other by n-l other pixel rows.

2. Digitally operable graphics display apparatus as claimed in Claim 1, including a further, central, processor which is operable to distribute to the display processors the data to be processed for their allotted pixel rows.

3. Digitally operable graphics display appa ratus, substantially as hereinbefore described with reference to the accompanying drawings.