GB2186768A - Video display unit with improved security - Google Patents

Abstract

In a video display unit the timing of the scanning and synchronising signals is modified so as to render more difficult the interception of the intelligence carried by the radiation that may be emitted by the associated video signal generating or processing circuits. Three ways of modifying the timing are disclosed as (i) changing the phase of the video dock between character positions; (ii) introducing a random or pseudo random delay at the end of each line; (iii) inserting a delay at the end of each field. A known directly synchronised scan generator can tolerate scanline changes of 5%. <IMAGE>

Description

SPECIFICATION Video display unit with improved security This invention relates two circuit means to prevent the iterception ofthe intelligence carried by the radiation that is emitted by the video signal generating or processing circuits of a video display unit. Within the specification of this invention video display unit and visual display unitare synonymous and are hereafter abbreviated to VDU. The invention also relates to VDUs incorporating or modified to incorporate means whereby such security may be achieved, and to a method whereby such security may be achieved.

VDUs are widely used as components of systems which store and manipulate confidential information.

The incidental radio frequency emissionsfrom the circuits of VDUs can be received at some distance from the VDU itself, and these emissions can be decoded or deciphered in order to reveal the information which is displayed upon the VDU screen. In view ofthecommercial and legal importance of maintaining the security of such information, attempts have been made either to reduce the radio frequency emissions, orto change them so that decoding or deciphering ofthe signals is made more difficult or impossible. Known methods for reducing radiofrequency emission include the use of shielding or screening oftheVDU, careful choice of circuit layout, and the filtering of external connections. However, none ofthese known methods is wholly satisfactory.

It is an object of the present invention to provide circuit means whereby it is made more difficult or impossibletodecodeordecipherthe Remission from a VDU at a location remote from the screen.

According to the present invention there is provided circuit means to prevent the interception of the intelligence carried by the radiation that is emitted by the video signal generating or processing circuits of a VDU, said circuit means being adapted to modify the timing ofthe video signal and/orthe associated line or field scanning signals.

The invention also provides a method to prevent the iterception ofthe intelligence carried by the radiation that is emitted by the video signal generating or processing circuits of a video display unit, said method comprising modification ofthetiming of the video signal and/orthe associated line orfield scanning signals.

A circuit means and method in accordance with the present invention will now be described, byway of example, with reference to the accompanying drawing, in which: Figure lisa schematic diagram of a part of a conventional VDU and ofthe circuitry associated therewith; and Figure 2 is a detailed schematic diagram of one of the components shown inthepreviousfigure.

Referring to figure 1,the VDU includes a cathode ray tube 10, associated with which is a scan generator 12 and scanning circuits which deflect the light spot to form a raster pattern on the CRT screen. The VDU also includes digital interface circuits, including a data register 14 and a divider 16 for the character clock, which, for each position on the screen in turn, take from memory overthe character data bus lines 18 the information as to the identity of the character required (the "character code"), translate this information using information stored in the font memory 20, and using a serialiser 22 re-order into a serial sequence the pixel information that constitutes the required video signal on line24.Thevideosignal input on line 24 is required to provide sequentially the brightness information for each element or pixel of each line in turn. The pixel sequence is timed by a pixel clock generator 26, that is usually a high-stability crystal oscillator dedicated to the timing ofthe VDU display circuits. The output from the pixel clock generator 26, as well as being taken to the divider 16 and serialiser 22, is also fed to a display controller 28, among the outputs of which are synchronising signals on line 30 which goes to the scan generator 12 and which define thetimesatwhich new lines and new pictures and "fields" are to commence.

The video signal on line 24 is a precisely timed electrical signal which contains all the information displayed on the screen, and which is repeated every time the display is rescanned, typically 50 times per second. Furthermore, the video information is based on character shape, and so contains more detail than the minimum information required to identify the character. The precise frequency control, regular repetition and inherent redundancies ofthevideo signal make it easy to extract the information content from the RF emission even when the signal-to-noise ratio is poor. It is also well-known that mostVl)Us radiate detectable signals at the frequency ofthe pixel clock generator 26, and at the frequencies of its harmonics, and thatthese signals are all modulated with the video signal.

The present invention is based upon the fact that any interception apparatuswill requiretimingin- formation from the synchronising circuits ofthe VDU in order to reconstruct the display. It is relatively difficultforthe interceptor to decodethis synchronising information, and technique which make use of the known precise crystal-controlled timing of the VDU are employed. Therefore, in accordance with the present invention, this timing is modified to as great an extent as is possible without preventing proper operation ofthe VDU scanning circuits. It has been observed that known directly-synchronised scan generator circuits will operate correctly despite scan time changes of 5%.The so-called "flywheel sync" circuits sometimes used for line-scan synchronisation may only operate correctly with instantaneous scan time changes of 0.05% or less. This modification ofthe timing can be achieved in a number of ways. The following three ways are given by way of example: (a) The phase of the video clock is changed between each character position on the VDU. This will have no effect on the VDU but will make it more difficult for an interceptor to employ a phase-locked loop to recover the video clock signal from the VDU emission from which the interceptor might hope to obtain the synchronising signals by frequency divi sion.

(b) By altering the timing along a line, for example by employing a pseudo-random variation ofthe timing along a line. A random or pseudo-random delay can be introduced attheend of each line, before generating a line sync pulse and commencing the next line. This will destroy the readability of an intercep tor's picture if he tries to usefrequency-division from a local referencefrequencyorfrom a phase-locked loop that recovers the video clocksignal from the VDU emission.

(c) As an alternative, a delay can be inserted atthe beginning or end of each fieíd. This will have a comparable effectto (b) but will exploit another dimension oftolerance oftheVDU synchronisation circuits.

These three ways of achieving this countermeasure are indicated in figure 1 ofthe accompanying draw ingsbytheelementsshown in broken lines. Block34 has one inputtaken from the output ofthe clock 26 and another inputtaken alternatively from the character clock divider 16 orfrom the outputs ofthe display controller 28.

Block 34 comprises logic means which may include programmable counters shift registers and combinational logic arranged to modify eitherthe frequency or the phase ofthe pixel clock signal applied to serialiser 22 and optionally also modify the signal applied to display controller 28. The modification will be varied according to a random or pseudo-random signal either generated within block 34, or supplied to block 34 by some non-correlated signal from another part of the associated digital system. Figure 2 shows a detailed embodiment of block 34 in which the incoming clock signal is routed to the output by the 'and' gate 34a only when the 'carry' signal from the counter34b is logically high.Following receipt of a 'load' signal the modifying number supplied by the random number generator34d is loaded into the counter asynchronously. The 'carry' signal then goes low, and the clock signal is routed by gate 34c so as to increment the counter 34b until its terminal count is reached and the 'carry' signal is once again high.

Duringthecounting period no pixel clock output is supplied for serialiser 22 and controller 28 so as to achievetheobjectofthe invention.

In the first ofthe above-mentioned examples the load signal that initiates the timing modification is controlled according to an output ofthe character generator 16. In the second and third examples the modifications are controlled according to the line and field synchronising signals respectively. These alternative connections are shown dotted in Figure 1.

The circuit means described in the above-men tioned examples may be used singlyorin any combination as appropriate.

Claims (9)

1. Circuit means to prevent the interception of the intelligence carried by the radiation that is emitted by the video signal generating or processing circuits of a video display unit, said circuit means being adapted to modifythetiming of the video signal and/orthe associated line orfield scanning signals.

2. Circuit means according to claim 1 wherein the frequency or phase ofthe pixel clockfrequencythat is applied to the video data serialiser is modified by a variable amount, such modification being timed synchronouslywith the displayed character pattern.

3. Circuit means according to claim 1 wherein the frequency or phase of the pixel clock frequency that is applied to both the video data serialiser and the displaysynchronising controllerismodifiedbya variable amount, such modification being timed synch ronously with the line scan signal.

4. Circuit means according to claim 1 wherein the frequency or phase ofthe pixel clockfrequency that is applied to both the video data serialiser and the display synchronising controller is modified by avariable amount, such modification being timed synchronouslywith the field scan signal.

5. Circuit means according to any of claims 2 to 4, wherein the modification ofthe pixel clockfrequency is achieved by digital logic means.

6. Circuit means according to any of claims 2 to 4, wherein the modification of the pixel clock frequency is achieved byvariable-frequencyoscillator means.

7. Circuit means substantially as described herein with reference to the accompanying drawings.

8. A video display unit incorporating the circuit means of any one of claims 1 to 7.

9. A method to prevent the interception of the intelligence carried by the radiation that is emitted by the video signal generating or processing circuits of a video display unit, said method comprising modifica tion ofthetiming of the video signal and/orthe associated line or field scanning signals.