GB2173671A - TDM switching - Google Patents

Abstract

A switching device for the time-division digital interconnection of information sources 2, consists of a control circuit block and a connection circuit block, wherein said control circuit block /1/ consists of a control unit provided with a memory block /3/, a transient storage unit provided with speed-matching device /4/, a control-matching circuit /5/, a transient storage unit /6/, a distributed patch panel instruction storage unit /7/, a generator of patch panel addresses /8/, a change in state sensing circuit /9/, a storage unit containing states and/or changes in state /10/,a generator of scanning addresses /11/, an intervention control circuit /12/, an instruction converter /13/, an address decoder /14/, a decoder of state addresses /15/, and an address decoder of intervention point /16/ respectively. <IMAGE>

Description

SPECIFICATION Apparatus for time-division digital inter-connection of information sources, particularly for telephone exchanges The invention relates to an apparatus for timedivision digital interconnection of information sources, particularly for telephone exchanges, which through the favourable arrangement of the switching functions and with their digital time-division realization are used for building up flexible switching apparatuses of varying function and capacity.

The apparatuses based on time-division digital (PCM) connection use the combination of timedivision (T) and space-division (S) stages. A characteristic example of these solutions is the DBX-1200 type digital private exchange. In this private exchange - similarly to the first generation of digital switching apparatuses of other forms - the connection takes place with pulse code-modulated (PCM) signals within the exchange. For the A/D - D/A convertion multichannel (32) common coding-decoding circuit is used adopted from the primary PCM multiplex apparatuses used already much earlier in communication. Eight commoin coding-decoding circuits are found in the apparatuses, each forming a PCM bus. A bus and its time slots are fixed to the analogue channel.The analogue channels are connected by the syitable co-ordination of the time slots, so that the eight line PCM signal is transmitted with the insertion of a series/parallel converter to a separate switching stage for transfer of the time slots. The signal tones are transmitted with the switch stage to the calling and called subscribers, since the tones are connected to a separate 32channel A/D - D/A converter block.

The DBX-1200 type private exchange has several adverse properties. On account of the 32-channel common AID-DIA converters, the capacity of the system can be expanded or reduced only by steps of 32. The fixed time slot allows the connection of as many information sources as the number of time slots. This increases unnecessarily the number of time slots and that of the A/D-D/A converters. The fixed time slot has an additional drawback in that switching stage is required for the interconnection of information sources even in case of minimal build up. Since listening into the speech connection is solved with a separate 32-channel port, furthermore the tones necessary for building up the call are connected to a so-called service port, seven the minimal build up requires three ports and one patch panel.

The objective of the invention was to eliminate the earlier described shortcomings and to realize an economical, flexible switching apparatus expandable in smaller steps as to have the cost of the exchange increasing in proportion to expansion of the information sources and thus the cost of each line should be as low as possible.

The objective was attained with the use of AI DIA converters for each channel instead of the 32-channel A/D-D/A converters, and distributed patch panel was ued for each channel. This enabled the coupling of information sourses more than the number of time slots to the primary PCM bus, but naturally only as many information sources were activated as the number of time slots. Transition from the transmission bus to the reception bus does not require separate time switching stage, hence the use of 32-channel D/A'-AID module is necessary for producing the selective tones and for realizing the operator's functions within which the operator's monitoring if of special significance.

The invention is described in detail by way of example with the aid of drawings in which Figure 1: Connection layout of the apparatus according to the invention with connecting circuit block and adapted to four different information sources and with one PCM bus; Figure 2: Version built up for three PCM buses; Figure 3: Version adapted to analogue telephone set of the circuit of the connecting circuit block shown in Figure 1 matching several information sources; Figure 4: Version adapted to the main exchange of circuit of the connecting circuit block shown in Figure 1 matching several information sources; Figure 5: Version adapted to the operator's set of the circuit of connecting circuit block shown in Figure 1 matching several information sources; Figure 6:Version adapted to digital subscriber's station of the circuit of connecting circuit block shown in Figure 1 matching several information sources; Figure 7: detailed diagram of the change in state sensing circuit of the control circuit shown in Figure 1; Figure 8: Detailed diagram of the signle bus switch of the control circuit shown in Figure 1.

Construction of the switching apparatus according to the invention is shown in Figure 1 and 2 and certain parts of the connection layout are shown in Figures 3 to 8. The diagrams represent the switching apparatus according to the invention given by way of example as private exchange, but the invention is not restricted only to these. By the suitable formation of the modules any other digital (PCM) switching apparatus (rural dependent exchange, transit exchange of office network, data switching exchange of office network, etc.) can be built up.

The switching apparatus according to the invention shown in Figure 1 is built up of two blocks, the control circuit block 1 and connecting circuit blocks 2. The most important part of the control circuit block is the central control unit 3 in which the microprocessor 3a is connected to RAM 3b and PROM 3e with bi-directional data bus and one directional address and control bus, and it is connected with the same buses to the circuits transmitting information and instruction to the other parts of the control circuit block 1.

The connecting circuit blocks 2 match the information source to the switching apparatus. On account of the different information sources the connecting circuits blocks 2 are also different but each is provided with distributed patch panel 18, intervention receiver circuit 19, scanned signal transmitting circuit 20 and information source matching circuit 23.

Since the connecting circuit block as subject of the invention may be different according to the type of information source, thus the four most frequently used forms of the information matching circuit 23 are described in detail in the following.

Matching of analogue telephone sets S: Build up of the connecting circuit block 2 in this case is the same as that of the one shown in Figure 1.

Build up of the information source matching circuit 23 is shown in Figure 3. The two-wire analogue telephone set is connected through the signal transmitter 23a to the level matching unit 23b. The signal transmitter 23a is a relay contact in the simplest case, on the neutral contact of which the speech information between the switching apparatus and the telephone set, while on its operative contact the call signal (ringing) to the telephone set are transmitted. The intervention device 23c in this case may be the coil of the relay actuated through the intervention summator 22 by the intervention receiver circuit 19. In the case of necessity the intervention device 23c may insert damping or amplification into the four-wire speech path, similarly upon the initiative of the intervention receiver circuit 19.

Purpose of the level matching unit 23b is emission of the microphone supply current to the telephone set four-wire matching to the AID-D/A converter 21 of the bi-directional information transmission of the two-wire telephone set connected to the information source matching unit 23, sensing the loop closing or loop chopping of the telephone set and actuation of the earth knob, as well as matching these signals through the signal level matching unit 23d to the electronic circuits of the switching apparatus, furthermore transmission of these signals to the scanned signal transmitting circuit 20.

Matching of the analogue main exchange T: Build up of the connecting circuit block 2 is the same as that of the one shown in Figure 1. Build up of the information source matching unit 23 is shown in Figure 4. In this case the level matching unit 23b performs only the 2/4wire convertion. The signal transmitter 23a receives the call signals, state monitoring and rate metering signals, etc. arriving from the main exchange, which are transmitted through the signal level matching unit 23d to the scanned signal transmitting circuit 20. The loop closing and perhaps the poiarity changing circuit which receives the actuating information through the intervention device 23c from the intervention receiver circuit 19 are found similarly in the signal transmitter 23a.

Matching of the analogue operator 0: Build up of the connecting circuit block 2 is the same as that of the one shown in Figure 1. Build up of the information source matching unit 23 is shown in Figure 5. The two-wire or four-wire line of the operator's set is connected to the level matching unit 23b. In case of two-wire line the level matching unit 23b performs 2/4 wire conversion too, and in case of four-wire line it performs level matching only in the path of the speech signal. Its four-wire output is connected to the input of the signal summator 23e.

The four-wire output of the signal summator 23e is connected to two A/D-D/A converters 21 in the connecting circuit block 2, this way enabling the operator to bring about speech connection with another information source, or to cut into a speech connection as a third party between two information sources. The signals from the keyboard of the operator's set are transmitted through the signal level matching unit 23d to the scanned signal transmitting circuit 20, while the intervention device 23c controls the signalling devices of the operator's set through the signals coming from the intervention receiver circuit 19.

Matching of the digital information source D: Build up of the connecting circuit block 2 is the same as that of the one shown in Figure 1. Build up of the information soruce matching unit 23 is shown in Figure 6. The information transmission between the digital information source D and the switching apparatus takes place with digitally coded line signals according to a certain procedure by two or four wires and with the speed depending on the informations to be transmitted and on the transmission procedure. The digital signal flow between the digital information source D and level matching unit 23b may carry signal informations and data transmission informations too in addition to the speech information.These signal and data informations pass through the intervention device 23c and level matching unit 23b to the digital signal flow of the line at the rate fixed by the intervention receiver circuit 19. The signals and data sent from the digital information source D are recovered from the line signal flow through the level matching unit 23b and signal transmitter 23d received by the scanned signal transmitting circuit 20. The digital speech informations recovered from the line digital signal flow on the level matching unit 23b are matched by the speech matching unit 23f to the distributed patch panel 18 of the switching apparatus at the bit-rate required by the system.

Connection between the control circuit block 1 and the connecting circuit block 2 can be realized in the course ofthreefunctions: the scanning, intervention and control of the distributed patch panel. The three functions are described separately as follows: The control circuit block 1 obtains knowledge of the states (two lines in case oftelephone set: lifting, earth knob; in case of main exchange frequently four lines: monitoring of seizing, monitoring of call, monitoring rate metering signal, and monitoring of loop state) of the information sources connected to the connecting circuit block 2, i.e. analogue telephone set, main exchange T, digital subscriber D, etc. In case of scanning the generator of the scanning addresses 11 - which may be an n-bit counter in a simple case- produces the addresses of the points to be scanned which are decoded by the decoder of state addresses 15 and individual permit signals are sent to the scanned signal transmitting circuit 20 which become active and transmit the state of the scanning point connected to their input towards the control circuit block 1. The scanned signal transmitting circuit 20 - in case of transmitting single bit information - is realizable with an AND gate and in case of multi-bit with a parallel/series converter. The series information transmitted into the control circuit block is preprocessed.The information of each scanning cycle is written into the state storage unit 10, suitably a RAM - and it will be compared to the state received from the same point in the previous scanning cycle, that is stored in the state storage unit 10. Similarly the state storage unit 10 containsthe information whether the state i nformations received in the two scanning cycles preceeding the instantaneous cycle were the same or different. Thus the change in state sensing circuit 19- to be described later-takes into consideration the state of the instantaneous and previous scanning cycles, as well as the relative value of the states received in the two scanning cycles preceding the instantaneous cycle.

If relative change in state occurred in the two previous cycles, then this is not regarded to be evaluated by the circuit in respect of operation of the apparatus, but as a disturbing pulse not suitable for further processing. If the states were the same in the two preceding cycles, but the instantaneous state shows change in state compared to the previous one, then it is still not change in state in respect of operation of the apparatus. In this case the change in state sensing circuit 9 only assumes the change in state and stores it in the state storage unit 10. The assumed change in state is not transmitted to the central control unit 3. This will be decided according to the evaluation of the state received in the next scanning cycle.Actual change in state exists only when the states received in the two scanning cycles preceding the instantaneous scanning cycle show change in relation to each other, but the states of the instantaneous and previous cycles are identical. In this case the change in state sensing circuit 9 sends signal through the control matching circuit 5 - that is a parallel periphery - to the central control unit 3.

Thereupon the central control unit 3 reads in the address pertaining to the change in state, i.e. the state of the generator of scanning addresses 11, which at the same time gives the address of the connecting circuit block in question as well as which state characteristic line of the connecting circuit block 2 is spoken about. The central control unit sends out the instructions according to the stored program which become necessary as a result of the change in state. (There may be intervention information, instructions interconnecting information sources, etc.).

One of the types of the change in state sensing circuit 9 is shown in Figure 7 in connection with the state storage unit 10. Upon switching on the supply voltage the null circuit 9g resets the memory area containing the state of the scanned points of the state storage unit 10 through one of the gates 9b OR and the memory area of the assumed changes in state through the other gate 9b OR to homing position. The series scanned informations are sent to the signal generator 9a, where the actual value of the information will be determined by sampling. The regenerated signal - except the zero setting time passes invariably through gate 9b OR to the singlebit comparator 9d and state storage unit 10.The single-bit comparator 9d compares the regenerated signal with the state information read out of the state storage unit 10, i.e. received from the same scanning point in the previous scanning cycle, which is stored in the single-bit transient storage unit 9c for the time of evaluation. Output of the single-bit comparator 9d and assumed change in state information stored in the other single-bit transient storage unit 9c are transmitted to the positive AND gate 9e and negative AND gate 9f. The positive AND gate 9e establishes the assumed change in state and it is written back through gate 9b OR into the state storage unit 10.

The negative AND gate 9f senses the actual change in state and from its output sends signal to the control matching circuit 5.

Intervention is spoken about when the instruction of the central control unit 3 changes the state of intervention device in the connecting circuit block 2 (e.g. ringing relay, damping circuit closer, circuit breaker). The intervention takes place as follows: the central control unit 3 transmits the date related to the new state of intervention device and the address of the intervention point which is the same as that of the intervention receiver circuit 19 to the transient storage unit 6. Upon transmission of the date and address the transient storage unit S sends signal to the intervention control circuit 12 which produces permit signal for a short time.The address decoder of intervention point 16 performs the decoding on the basis of the received addresses and sends permit signal for the time fixed by the intervention control circuit 12 to the addressed intervention receiver circuit 19, into which the information related to the new state of the intervention device is written in. The intervention receiver circuit 19 can be realized by a bit by bit addressed storage unit.

For interconnection of information sources the transmission and reception time slots of the distributed patch panel 18 have to be coordinated. The control takes place by the central control unit 3 issuing the instrictions related to the operation mode of the distributed patch panel 18 together with the address of the distributed patch panel 18 in question.

The instruction word and address are received by the transient storage units provided with speed matching device 4. This is necessary to prevent the transient storage unit from receiving further instruction from the central control unit 3 until the earlier instruction is written into the distributed patch panel instruction storage unit 7 (RAM).

The distributed patch panel instruction storage unit 7 is used for the storage of instructions related to all distributed patch panels 18 of the apparatus in order to read out the instructions at fixed intervals and to forward them to all distributed patch panels 18 for renewal. In accord with the task the capacity of the distributed patch panel storage unit 7 must be co-ordinated with the number of distributed patch panels 18 existing in the apparatus. Control and renewal of the distributed patch panels 18 take place by producing the addresses of the distributed patch panels 18 with the generator of patch panel addresses 8which might also be a binary counterthereby the patch panel instruction storage unit 7 is addressed and the word or words pertaining to the distributed patch panel 18 in question are read out.

The instruction word read out from the distributed patch panel instruction storage unit7 is transmitted to the instruction converter 13 for parallel/series conversion, the output of which simultaneously with the permit signal of the address decoder 14 connected to the generator of patch panel addresses 8 transmits the instruction word to the input of the distributed patch panel 18 in the form of series signal.

Upon the series control word the distributed patch panel 18 functions as follows: it stores the time slot information related separately to transmission and reception. In accord with the received transmission or reception timing signal it actuates two internal counters the states of which are compared with the stored time slot data related to the transmission and reception.

If the comparison shows identity the circuit permits transmission or reception of the distributed patch panel, perhaps both at the same time, depending on which stored time slot shows identity with the internal counters. The permission is valid only for a single time slot in each allocated time in both operation modes until the next instruction coming from the central control unit 3 changes the contents of the internal instruction storage unit in the distributed patch panel 18.

Such integrated circuits available on the market are also known which fulfil the functions of the distributed patch panel 18 (e.g. Intel 2911, MOTOR OLA MC 14416).

Operation of the apparatus according to the invention shown in Figure 1 by way of example, in case of call is the following: the operation is described in case of signal connection between two information sources, when both information sources are telephone sets.

The demand for building up the connection is indicated by lifting the handset of the call signal apparatus. This results in change in state related to the information source. This new state passes during the cyclic scanning from the scanning signal transmitting circuits 20 to the change in state sensing circuit 9 with the aid of the generator of scanning addresses 11 and decoder of state addresses 15. The change in state sensing circuit 9 establishes the fact of change in state with the aid of the state storage unit 10, and sends signal through the control matching circuit 5 to the central control unit 3. The central control unit 3 interrupts the currrently running program upon the signal, and through the control matching circuit 5 it reads in the address of the change in state, i.e. the instantaneous state of the generator of scanning addresses 11.The central control unit 3 establishes the address of the apparatus initiating the lifting, and the address of the pertaining distributed patch panel 18 from the read-in address. Assuming that there is free time slot for interconnection of the information sources, the central control unit 3 sends selective tone to the call-initiating apparatus by switching the reception input of the distributed patch panel 18 to such time slot in which the PCM words pertaining to the digital samples of the selective tone can be found. These words are transmitted to the reception bus by the cyclic read-out of the digital audio-frequency generator, suitably a PROM.This control process takes place in such a way that the central control unit 3 sends the address of the distributed patch panel, furthermore the code corresponding to the reception operation mode and reception time slot to the transient storage unit provided with speed matching device 4. The codes corresponding to the operation mode and time slot- i.e. the instruction word are written from the transient storage unit provided with speed matching device 4 into that line of the distributed patch panel instruction storage unit 7, which pertains to the distributed patch panel 19.The generator of patch panel addresses 8 forwards the instruction word from the distributed patch panel instruction storage unit 7 so that the output of the generator of patch panel addresses 8 addresses the distributed patch panel 18 with the aid of address decoder 14 which is capable to receive the instruction word read out from the instruction converter 13.

Then the input of the distributed patch panel 18 will be open ins the time slot corresponding to the selective tone and it forwards the information in that particular time slot to the AID - D/A converter 21.

Now in the receiver of the call signal apparatus the selective tone becomes audible. This is the starting condition ofthe selection process (e.g. dialling).

Each pulse of the pulse sequence sent for the call number of the called information source will be transmitted as change in state to the central control unit 3. On the basis of the received changes in state the central control unit 3 establishes the address of the called information source. If the called information source is free, the central control unit 3 sends the address of the intervention device (ringing relay) pertaining to the called information source, and the state information required for operating the relay to the transient storage unit 6. The intervention receiver circuit 19 is addressed with the aid of the address decoder of intervention point 16, and stores the information corresponding to the new state of the intervention device in the information source matching circuit 23.Output of the intervention receiver circuit 19 actuates through the intervention summing circuit 22 the ringing relay, since in this case the intervention summing circuit 22 does not change this state. The ringing is interrupted by releasing or repeated operating of the ringing relay so that the intervention receiver circuit 19 receives different informations from the central control unit 3. If the apparatus of the called information source is lifted during the time of ringing, then the intervention summing circuit 22 changes the state of the intervention point, i.e. releases the ringing relay indepen dentlyfrom the central control unit 3 based on the signal received from the information source matching circuit 23.Lifting of the called information source appears as change in state in the central control unit 3, upon which the central control unit 3 orders a free pair of time slots to the two information sources. The distributed patch panels 18 are controlled so that the transmission side of the caller in one of the free time slots is active and the reception input of the caller is open, while it is reversed in the otherfree time slot.

The transmission outputs of the distributed patch panels are connected to a single line, to the transmission bus X. The PCM signals pass through the transmission bus X to the single-bus switch 24, that brings about connection, in this case short-circuit between a transmission bus X and a reception bus R.

The circuit of the connecting circuit block 2 pertaining to the operator 0 has the possibility of cutting into an already built up connection as a third party without the need of changing the time slots of the calling and called information sources participating in the original connection, or without the need of further time slots. This takes place in such a way that one of the distributed patch panels 18 of the operator O is inserted into one of the information signal paths (e.g. to the caller- called direction) and the other distributed patch panel of the operator 0 into the other information signal path (e.g. called - caller direction). As a consequence of this insertion the informations sent by the information sources are taken over by the two distributed patch panels 18 of the operator 0, forwarding to the connecting AID- D/A converter 21.The information source matching circuit 23 adds the analogue signal from operator 0 to the obtained analogue signal, then it sends back to the A/D - D/A converter 21. The totalized analogue informations in the form of PCM words pass with the aid of the two distributed patch panels 18 and with the single bus switch 24 into the same time slots from where they were taken out. This takes place so that the transmission output of the two distributed patch panels 18 pertaining to operator 0 is not connected to the transmission bus X, but to the permit circuit 24b of the single-bus switch shown in Figure 8. The transmission bus X is connected to the inhibit circuit 24a.The time slot of the operator transmission Tx linked with the two distributed patch panels 18 pertaining to operator 0 is attached to the inhibit circuit 24a and permit circuit 24b, and it is active in those time slots when the transmission output of the two distributed patch panels is active.

Signal of the time slots of the operator's transmission Tx with the aid of the inhibit circuit 24a delates the informations given by the calling and called subscribers and with the aid of circuit 24b it permits the PCM signals pertaining to operator 0 in the same time slots. The inhibit circuit 24a and permit circuit 24b are realized with three-state gates thus interconnecting their outputs, the reception bus R is brought about. This way the called subscriber is able to receive the informations sent by the calling subscriber and operator 0, while the calling subscriber receives the information sent by the called subscriber and operator 0 in the reception time slot.

The signal-bus switch 24 is also suitable for bringing about connection in a single time slot between any information source and the operator 0.

In this case only one of the distributed patch panels 18 pertaining to operator 0 is active, hence the deletion takes place in a single time slot in the single-bus switch 24, i.e. in the transmission time slot of the information source being in connection with the operator 0 and the information of the operator 0 is transmitted in the same time slot.

Another typf of the switching apparatus representing subject of the invention is shown in Figure 2 built up with groups of connecting circuit blocks 2 and each group is connected to a driving circuit 17.

Sub-blocks of said connecting circuit blocks 2, i.e.

distributed patch panels 18 and intervention receiver circuits 18 are controlled and scanned signal transmitting circuits 20 are challenged similarly as in case of the preferred embodyment shown in Figure 1. The difference is that the outputs PCM of the distributed patch panels 18 are not connected to a common transmission bus but each group to a transmission bus. The transmission bus is connected to a driving circuit 17, which gates the transmission bus with transmission time slot signal Tx produced in the active transmission time slots by the distributed patch panels 18 in the group, i.e. the signal is transmitted to the multi-bus switch 25 only in the active state of the transmission time slot Tx. This gating allows to connect the connecting circuit blocks 2 forming two groups and geometrically far removed from each other to a transmission bus X.

The switching i.e. transfer of the time slots between transmission buses X and reception buses R is carried out by the multi-bus switch 25. ready-made circuits are available on the market for building up the multi-bus switch 25 (e.g. MO88, manufactured by SGS).

Claims (5)

1. Apparatus for time-division, digital interconnection of information sources consisting of control circuit block and connecting circuit blocks, characterized in that the control circuit block (1) consists of control unit (3), transient storage unit provided with speed-matching device (4), control matching circuit (5), transient storage unit (6), distributed patch panel instruction storage unit (7), generator of patch panel addresses (8), change in state sensing circuit (9), state storage unit (10), generator of scanning addresses (11), intervention control circuit (12), instruction converter (13), address decoder (14), decoder of state addresses (15) and address decoder of intervention point (16); the connecting circuit block (2) consists of distributed patch panel (18), intervention receiver circuit (19), scanning signal transmitting circuit (20) and information source matching circuit (23), where the control unit (3) is connected to transient storage unit provided with speed-matching device (4), control matching circuit (5) and to transient storage unit (6); the distributed patch panel instruction storage unit (7) is connected to transient storage unit provided with speed-matching device (4), generator of patch panel addresses (8) and to the instruction converter (13); the generator of patch panel addresses (8) is connected to the address decoder (14); the control matching circuit (5) to the change in state sensing circuit (9), state storage unit (10) and to the generator of scanning addresses (11); the change in state sensing circuit (9) is connected to the state storage unit (10); the generator of scanning addresses (11) to the decoder of state addresses (15); the transient storage unit (6) to the address decoder of intervention point (16), intervention control circuit (12) and to the intervention receiver circuits (19); the intervention control circuit (12) to the address decoder of intervention point (16); the instruction converter (13) to the distributed patch panels (18); the address decoder (14) to the distributed patch panels (18); the change in state sensing circuit (9) through another line to the state storage unit (10) and to the scanned signal transmitting circuits (20); decoder of the state addresses (15) to the scanned signal transmitting circuits (20); the address decoder of intervention point (16) to the intervention receiver circuits (19); the information source matching circuit (23) to the scanned signal transmitting circuit (20); the distributed patch panel (18) through two lines is connected to the other distributed patch panel (18).

2. Apparatus as claimed in claim 1, characterized in that said connecting circuit block (2) comprises an AID - D/A converter (21) and an intervention summing circuit (22), wherein said AID - D/A converter is connected to said distributed patch panel (18) and to said information source matching circuit (23), further said intervention summing circuit (22) is connected to said intervention receiver circuit (19) and via two further lines to said information source matching circuit (23).

3. Apparatus as claimed in claim 1, characterized in that a single-bus switch (24) is provided with which comprises an inhibit circuit (24a) connected to a transmission bus (X) and a permit circuit (24b) connected to an operator's transmission bus (X,), further both said circuits (24a, 24b) are connected to an operator's transmission time slot line (TXo) wherein outputs of both circuits (24a, 24b) are connected to a reception bus (R).

4. Apparatus as claimed in claim 1, characterized in that a multi-bus switch (25) and driving circuits (17) are provided wherein of said connecting circuit blocks (2) are connected via two information lines and via a transmission time slot line (TX) to said driving circuits (17) which are connected via transmission buses (X) and reception buses (R) to said multi-bus switch (25).

5. Apparatus as claimed in claim 1, characterized in that said change-of-state sensing circuit (9) comprises a signal regenerator (9a), OR-gates (9b), single-bit transient storage units (9c), a single-bit comparator (9d), a positive AND-gate (9e), a negative AND-gate (9f) and a null circuit (9g) wherein a first OR-gate (9b) is connected to said signal regenerator (9a), to said negative AND-gate (9f), to said single-bit comparator (9d) and to said state storage unit (10), respectively, said state storage unit (10) is connected to said single-bit transient storage units (9c), one ofwhich is connected to said single-bit comparator (9d), further said null circuit (9g) is connected to a common terminal of said single-bit comparator (9d) and said positive AND-gate (9e) on one hand, and on the other hand to a common terminal of said positive AND-gate (9e) and of a further single-bit transient storage unit (9c).