GB2172721A - Protective software - Google Patents
Protective software Download PDFInfo
- Publication number
- GB2172721A GB2172721A GB08601808A GB8601808A GB2172721A GB 2172721 A GB2172721 A GB 2172721A GB 08601808 A GB08601808 A GB 08601808A GB 8601808 A GB8601808 A GB 8601808A GB 2172721 A GB2172721 A GB 2172721A
- Authority
- GB
- United Kingdom
- Prior art keywords
- address
- address word
- input
- memory
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Data processor address bus (12) provides an input to an address memory (22) which retrieves an output address word for presentation via a translated address bus (18) as the address to a system memory. Control (20) determines the state of a flipflop (26) whose output is coupled to the most significant bit-line (24) of the input to the address memory (22). The address memory (22) is partitioned into an upper half where each input word received on the processor address bus (12) retrieves an unmodified version of itself and a lower half wherein each input word retrieves a unique modified version of itself where the order of the binary digits as shuffled according to a predetermined scheme. The flipflop (26) may be switched via interrupt or other control lines from a data processing unit or via a monitor monitoring the processor address bus (12) for one or more predetermined address words. The data processing unit thus controls whether a modified or unmodified address will be provided to the system memory. Alternatively, the unmodified address may be provided via a multiplexer instead of from the address memory (22) (Fig. 3). Address translation units may be cascaded (Fig. 4). <IMAGE>
Description
SPECIFICATION
Method and apparatus for protecting soft
ware
The present invention relates to a method and
apparatus for use in data processing equip
ment wherein a processor unit is operative to
store data in a memory and to retrieve data
and programme step instructions from the
memory via data and address buses. The pre
sent invention particularly relates to a method
and apparatus for rendering difficult copying of
material held within the data processing equip
ment and use of copied material.
Computer software is a valuable part of any
data processing system and is subject to a
risk of unauthorised copying and use.
Generally speaking, material used in one
data processing system can be copied onto
disc and used in another. Methods have been
used employing specialised hardware to pre
vent program copying. Such hardware can in
terfere with "normal" operation of the data
processing system within which it is resident
and can require use of additional control sig
nals not normally present in a conventional
Von Neuman data processor as is currently
understood in the art.
It is desirable therefore to provide a method
and apparatus whereby the contents of a data
processing system can be rendered unintelligi
ble to attempts at conventional copying whilst
allowing unimpeded and unslowed operation
of the data processing system. It is further
desirable that such a system employs signals
already present in a data processor of the Von Neuman type, as currently understood in
the art, for its control.
According to a first aspect, the present in
vention consists in an apparatus for translating
memory addresses in a data processing sys
tem, said apparatus comprising a translation
unit including: an address memory, operative
to store a plurality of modified address words,
coupled to receive an input address word, op
erative in response to receipt thereof to select
and recall one of said plurality of modified
address words and operative to present said
recalled, modified address word as an output
address word; and a translation controller op
erative, in response to receipt of a control
signal, to select as said output address word
either said recalled modified address word or
said input address word unmodified.
According to a second aspect the present
invention consists in a method for translating
memory addresses in a data processing systerm, said method including the steps of: em
ploying an address memory to store a plurality
of modified address words; receiving an input
address word as an address input to said ad
dress memory, said address memory being
operative in response thereto to select and
recall one of said plurality of stored, modified address words; and, in response to receipt of a control signal,selecting as an output address word either said selected, modified address word or said input address word.
In a first preferred embodiment a translation unit is provided for use between the address bus of a data processor unit and the main system memory. The translation unit comprises a memory wherein alternative addresses are stored. The data processor address bus is coupled as the input address of the address memory and retrieved addresses from the address memory are coupled onto the address bus for the main system memory.
The contents of the address memory are divided into an upper and a lower half. A master address line controls whether the data processor address bus addresses the upper or the lower halfbof the address memory. The upper half contains output addresses identical with the input addresses from the data processor address bus. The lower half of the address memory contains modified addresses wherein the bit-order of the input address word is moved around so that each input address word addresses its own unique stored address word. When retrieved the stored address word is passed on to the system memory.
The master address line is derived from a control line passing through a flipflop which is operative to receive and hold a command from the data processor for either the unmodified addresses in the memory upper half or the modified addresses in the memory lower half now provided as the system memory address.
In a second preferred embodiment the address memory contains only modified addresses and the retrieved modified addresses from the address memory are provided as a first input to a multiplexer. The input address word which also addresses the address memory is provided as a second input to the multiplexer and the multiplexer is controlled by a control line once again passed through a flipflop to select either the modified addresses from the address memory or the input address word from the data processing unit.
In both the first and second embodiment the flipflop can be of a variety which is set and thereafter re-set depending upon the receipt of first and second instructions. As an alternative, the flipflop may be of a variety set to toggle between alternate states on successive instances of receipt of a control signal.
The control signals to the flipflop can be derived from the input address word via a monitor scanning the input address word for a predetermined word or words.
Both the first and second preferred embodiment may be concatenated to form a multielement translation unit where the output address word of one translation unit provides the input address word of the following tran slation unit in the chain.
The invention is further described, by way of an example, by the following description in conjunction with the appended drawings in which: FIG. 1 shows a block schematic diagram of a translation unit according to the present invention in place in a data processing system.
FIG.2 shows a schematic block diagram of a first preferred embodiment of the present invention.
FIG.3 shows a schematic block diagram of a
second preferred embodiment of the invention,
and FIG.4 is a schematic block diagram show
ing how translation units can be cascaded.
FIG. 1 shows the context of use of the in
vention.
A data processing unit 10 provides a pro
cessor address bus 12 intended to provide address -input to a system memory 14
wherein programme steps and data are
stored. In addition to fast memory the system
memory 14 can include disc drives and other
peripheral devices.
An address translation unit 16 is interposed
between the processor address bus 12 and
the system memory 14 and provides, on a
translated address bus 18 under control of
signal 20 from the data processing unit 10
either the input address word received on the
processor address bus 12 unmodified or a
translated modified address for use by the
system memory 14.
FIG.2 shows a schematic block diagram of a
first preferred embodiment of the address
translation unit 16 shown in FIG. 1.
The processor address bus 12 is provided
as an addressing input to an address memory
22. The most significant bit-line 24 addressing
the address memory 22 is controlled by the -output of a flipflop 26 whose state is deter
mined by the control signal 20 from the data
processing unit 10.
When the most significant bit-line 24 is logi
cally false the lower half of the address mem
ory 22 is addressed by the input address
words received on the processor address bus
12 and when the most significant bit-line 24
is logically true the upper half of the address
memory 22 is addressed by the processor ad
dress bus 12. Whichever storage location in
the address memory 22 is addressed, its re
trieved contents are presented as output on
the translated address bus 18.
The upper half of the address memory 22
contains unmodified addresses. That is to say,
each input address word received on the pro
cessor address bus 12 retrieves from the ad
dress memory 22 an output address word 18
which is identical with itself so that the tran
slation unit 16 is effectively invisible save for
a small delay caused by the presence of the
address memory 22 which is chosen to be a
high speed memory.
The lower half of the address memory 22 contains modified addresses where each input address word received from the processor address bus 12 addresses and causes the retrieval of an output address word on the translated address bus 18 where the order of the binary digits has been swapped around according to a predetermined scheme. Thus each input address word received from the processor address bus 12 when the most significant bit-line 24 is logically false addresses and causes the retrieval of an address word which is unique to itself. No input word will produce an output word which can be retrieved by any other input word.
FIG.3 shows a block schematic diagram of the second preferred embodiment of the present invention.
The processor address bus 12 from the data processing unit 10 is provided as input to a translation address memory 28 storing only modified addresses such as would be stored in the lower half of the address memory 22 of FIG.2.
The processor address bus 12 is also coupled as input to a monitor 30 operative to scan the processor address bus 12 for one or more predetermined input addresses thereon.
In response to receipt of a pre-determined input address the monitor 30 provides a first output 32 coupled to the flipflop 26 and in response to the receipt of a second predetermined input address word from the processor address bus 12 the monitor 30 may optionally provide a second output 34 again used to control the flipflop 26.
The translation address memory 28 provides a retrieved modified address on a memory output bus 36 coupled as a first input to a multiplexer 38. The processor address bus 12 is coupled as a second input to the multiplexer 38. The flipflop 26 signals its state on a flipflop control line 40 which is coupled as a controlling input to the multiplexer 38. The multiplexer 38 responds to state of the flipflop 26 either by selecting the contents of the memory output bus 36 to be provided on the translated address bus 18 as the output address word or by selecting the input address word provided on the processor address bus
12 on the translated address bus 18 as the output address word.
The flipflop 26 may be set by the first output 32 of the monitor 30 and reset by the second output 34 of the monitor 30. Alternatively the flipflop 26 may be wired to toggle and only one output 32 provided by the monitor 30 causing the flipflop 26 to toggle between first and second selection states.
In both the first and second embodiments the control signal or signals to the flipflop 26 can be provided using a monitor 30 as shown in FIG.3, using interrupt lines and other control lines normally found in the data processing unit 10, or can exploit a combination of both.
At commencement of operation the flipflop
26 is set to an initial state. During, for
example, a power-on reset the flipflop 26 in
both the first and second preferred embodi
ments will be switched to cause the output
address word on the translated address bus
18 to be identical with the input address word
received on the processor address bus 12.
Thereafter software control operates to select
either the translated modified address or the
unmodified address dependently upon the con
tents of the programme.
FIG.4 shows a schematic block diagram indi
cating how translation units 16 can be cas
caded with the translated address bus 18 of
one translation unit earlier in the chain provid
ing the input address word to that translation
unit 16 next later in the chain. The data pro
cessing unit 10 may provide the control signal
or signals 20 to the translation units 16 in the
chain either via interrupt or other data pro
cessing register lines or by monitoring of the
input address word as shown in FIG.3.
The present invention includes all combina
tions of the features shown in FIGS.2 and 3
of this application used singly or together and
includes the address translation units 16 of FIG.4 comprising translation units embodying different modified versions as above described incorporating singly or together those features
of FIGS. 2 and 3.
With reference to FIG.4 the translation units
16 can be operated all in the straight through
mode where unmodified addresses are pro
vided as output or any one or more of them
can be caused to provide translation. Each
translation unit 16 can contain a different tran
slation table and by selecting different transla
tion units 16 in the chain at different times to
provide its translation table a range of differ
ent translation tables can selectively be ac
cessed by the data processing unit 10 to
gether with selectable combinations of those
tables by causing more than one translation
unit 16 in the chain to provide translated ad
dresses at any one time.
The address memory 22 or the translation
address memory 28 can be either a pre-pro
grammed Read-Only-Memory whose contents
are predetermined and fixed or a programma
ble memory such as a Random-Access-Mem
ory which can be loaded with a translation table of choice. In this latter instance the
memory 22, 28 would require, in addition to those features shown in FiGS.2 and 3 to be in
receipt of a data bus from the data processing
unit 10 whereby the data processing unit 10
could be operative by strobing different input addresses and presenting different data on the
data bus to load the memory 22, 28 prior to
its use.
Claims (20)
1. An apparatus for translating memory ad
dresses in a data processing system, said
apparatus comprising a translation unit including: an address memory, operative to store a plurality of modified address words, coupled to receive an input address word, operative in response to receipt thereof to select and recall one of said plurality of modified address words and operative to present said recalled, modified address word as an output address word; and a translation controller operative, in response to receipt of a control signal, to select as said output address word either said recalled modified address word or said input address word unmodified.
2. An apparatus according to Claim 1 wherein said address memory is operative to store a plurality of unmodified address words, and wherein said translation controller is operative to command said memory to select, as a recalled address word, only from among said plurality of unmodified address words for presentation as said output address word.
3. An apparatus according to Claim 1 wherein said translation controller comprises a multiplexer, coupled to receive said recalled, modified address word as a first data input, coupled to receive said input address word as a second data input, and operative to select as output either said first data input or said second data input.
4. An apparatus according to any of the preceding claims wherein said translation con troller-comprises a control register operative to enter and retain a selectable one of a first or second selection state in response to receipt of said control signal.
5. An apparatus according to claim 4 wherein said control register is operative to alternate between said first and second selection states in response to successive instances of receipt of said control signal.
6. An apparatus according to any of the preceding claims wherein said translation controller is coupled to monitor said input address word and is operative to recognise receipt of said control signal whenever said input address word is a predetermined input address word.
7. An apparatus according to any of claims 1 to 5 wherein said translation controller is coupled to receive as said control word a signal from a control line.
8. An apparatus according to claim 7 wherein said control line is an interrupt line from a data processor.
9. An apparatus according to any of the preceding claims including a plurality of concatinated translation units, all but a first translation unit in the chain being coupled to receive, as said input address word, an output address word from a translation unit earlier in said chain and all but a last translation unit in the chain being coupled to provide said output address word as said input address word to a translation unit later in the chain.
10. An apparatus substantially as described with reference to the appended drawings.
11. A method for translating memory addresses in a data processing system, said method including the steps of: employing an address memory to store a plurality of modified address words; receiving an input address word as an address input for said address memory, said address memory being operative in response thereto to select and recall one of said plurality of stored, modified address words; and, in response to receipt of a control signal, selecting as an output address word either said selected, modified address word or said input address word.
12. A method according to Claim 11 including the steps of employing said address memory to store a plurality of unmodified address words and, when it is desired to select, as said output address word, said input address word, causing said address memory to respond to said input address word by selecting and recalling only from among said plurality of unmodified address words.
13. A method according to Claim 11 including the step of employing a multiplexer to select and provide as said output address word either said recalled, modified address word from said address memory or said input address word.
14. A method according to any of claims
11 to 13 including the step of employing a control register operative to enter and remain in a selectable one of first and second selection states in response to receipt of said control signal.
15. A method according to Claim 14 including the step of causing said control register to alternate between said first and second selection states in response to successive instances of receipt of said control signal.
16. A method according to any of claims
11 to 15 including the steps of monitoring said input address word for a predetermined address word and deeming said control signal to have been received when said predetermined address word is detected.
17. A method according to any of claims
11 to 15 including receipt of said control signal from a control line.
18. A method according to claim 17 wherein said control line is an interrupt line from a data processor.
19. A method according to any of claims
11 to 18 including the steps of providing said output address word as the input address word for a further address memory.
20. A method substantially as described with reference to the appended drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB858507427A GB8507427D0 (en) | 1985-03-21 | 1985-03-21 | Prevention of soft & hardware copying |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8601808D0 GB8601808D0 (en) | 1986-02-26 |
| GB2172721A true GB2172721A (en) | 1986-09-24 |
Family
ID=10576419
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB858507427A Pending GB8507427D0 (en) | 1985-03-21 | 1985-03-21 | Prevention of soft & hardware copying |
| GB08601808A Withdrawn GB2172721A (en) | 1985-03-21 | 1986-01-24 | Protective software |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB858507427A Pending GB8507427D0 (en) | 1985-03-21 | 1985-03-21 | Prevention of soft & hardware copying |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB8507427D0 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2222899A (en) * | 1988-08-31 | 1990-03-21 | Anthony Morris Rose | Computer mass storage data protection |
| GB2248702A (en) * | 1990-10-11 | 1992-04-15 | Viserge Limited | Protection of software in ROM |
| WO2002093387A2 (en) | 2001-05-17 | 2002-11-21 | Koninklijke Philips Electronics N.V. | Method and device for protecting data transmission between a central processor and a memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2140592A (en) * | 1983-04-29 | 1984-11-28 | Philips Nv | Memory unit comprising a memory and a protection unit |
| EP0132129A2 (en) * | 1983-07-14 | 1985-01-23 | BURROUGHS CORPORATION (a Michigan corporation) | Address translation buffer |
-
1985
- 1985-03-21 GB GB858507427A patent/GB8507427D0/en active Pending
-
1986
- 1986-01-24 GB GB08601808A patent/GB2172721A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2140592A (en) * | 1983-04-29 | 1984-11-28 | Philips Nv | Memory unit comprising a memory and a protection unit |
| EP0132129A2 (en) * | 1983-07-14 | 1985-01-23 | BURROUGHS CORPORATION (a Michigan corporation) | Address translation buffer |
Non-Patent Citations (1)
| Title |
|---|
| WO A1 81/02480 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2222899A (en) * | 1988-08-31 | 1990-03-21 | Anthony Morris Rose | Computer mass storage data protection |
| US5144660A (en) * | 1988-08-31 | 1992-09-01 | Rose Anthony M | Securing a computer against undesired write operations to or read operations from a mass storage device |
| GB2222899B (en) * | 1988-08-31 | 1993-04-14 | Anthony Morris Rose | Securing a computer against undesired write operations or from a mass storage device |
| GB2248702A (en) * | 1990-10-11 | 1992-04-15 | Viserge Limited | Protection of software in ROM |
| GB2248702B (en) * | 1990-10-11 | 1994-11-02 | Viserge Limited | Data-processing apparatus |
| WO2002093387A2 (en) | 2001-05-17 | 2002-11-21 | Koninklijke Philips Electronics N.V. | Method and device for protecting data transmission between a central processor and a memory |
| WO2002093387A3 (en) * | 2001-05-17 | 2003-01-30 | Koninkl Philips Electronics Nv | Method and device for protecting data transmission between a central processor and a memory |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8507427D0 (en) | 1985-05-01 |
| GB8601808D0 (en) | 1986-02-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |