GB2169170A - Video data transfer between a real-time video controller and a digital processor - Google Patents

Abstract

A video processing system includes a video controller 12, a digital signal processor 14, and a buffer memory 52 for communicating information between the two. The buffer memory 52 is alternatively dedicated to one of the video controller 12 and the digital processor 14 by passing a token between the controller and the processor. The buffer memory is dedicated to the video controller during the vertical blanking interval of analog video signals processed by the controller, and is dedicated to the digital processor during other times. Commands and data may be communicated between the digital processor and the video controller via the buffer memory. An indication that a command has been communicated and an indication that a command has been processed may be produced. <IMAGE>

Description

SPECIFICATION Video Data Transfer Between a Real-time Video Controller and a Digital Processor Field of the Invention The present invention is related to video processing systems. More particularly, the present invention is related to arrangements and methods for bi-directional communication of information between a real-time video controller and a digital processor.

Background of the Invention Video processing systems commonly include a digital video controller and a digital signal processor. The digital video controller is a real-time processor which acquires video information, digitizes the acquired information and stores the resulting digital information in a frame store. After information is acquired and digitized by the video controller, it may be transferred to a digital signal processor. The digital signal processor performs various operations on the digitized video information (such as data compression, image enhancement, analysis, etc.). The digital signal processor returns processed digitized video information to the video controller for reconversion of the information to analog video signals and display of the image represented by the analog signals on a display.

Often, it is desirable for the video controller to acquire video information and control the display of processed information at the same time the digital signal processor processes recently-acquired information. Accordingly, information transfer between the video controller and the digital signal processor should be performed as quickly as possible and in such a way that the transfer does not cause interruption of the operations being performed in real time by the video controller. It is also desirable to minimize the overhead tasks which must be executed for each transfer to free most of the resources of the digital signal processor for processing digitized video information. In the past, it has been difficult to meet both of these countervailing design goals in the same video processing system.

United States Patent No. 4,148,070 to Taylor (1979) discloses a video processing system including a real-time video controller and a computer which performs operations on digitized video information. The computer accesses the information stored in the frame store of the video controller during the video line blanking period. A first-in, first-out buffer is provided to interface the high access rate of the frame store with the relatively low computer processing rate.

Unfortunately, the Taylor arrangement requires that extensive hardware and processor task overhead be provided to interface the computer directly to the controller frame store.

Bi-directional communication between a main video information processor and a peripheral video information processor during the video vertical blanking interval is, in general, known. See, for example, United States Patent No. 3,997,718 to Ricketts et al (1976), United States Patent No.

4,013,836 to Williams (1977) and United States Patent No. 4,390,900 to Van Kampen et al (1983).

Other patents disclosing bi-directional transmission of data over a single transmission channel include United States Patent No. 3,943,284 to Nelson (1976) and United States Patent No.3,975,712 to Hepworth eta (1976).

The use of a buffer memory to transfer information between two processors is also known in the prior art. See, for example, the following: United States Patent No. 4,032,899 to Jenny et al (1977); United States Patent No. 3,611,300 to Aldridge (1971); United States Patent No. 3,943,493 to Shelton (1976); and United States Patent No. 3,638,195 to Brenderetal (1972).

The following references disclose multiplexing of a memory device between different processors: United States Patent No. 4,056,843 to Bishop et ai (1977); United States Patent No. 3,848,234 to MacDonald (1974); United States Patent No. 4,075,692 to Sorenson et al (1978); United States Patent No. 4,080,651 to Cronshaw et al (1978); and United States Patent No. 4,079,454 to Sorenson et al (1978).

United States Patent No. 4,400,775 to Nozaka et al (1983) discloses a computer arrangement for facilitating the sharing of information among computers at a memory level wherein one processor is permitted to directly access memory dedicated to another processor. A scheme for multiplexing peripheral devices between different processors is disclosed in United States Patent No.

3,214,739 to Gountanis et al (1965).

United States Patent No. 4,396,938 to Dischert (1983) discloses a digital signal processing system including two random access memories for each processing channel. One of the random access memories stores information used to process video signals. The contents of the other random access memory may be changed during the active video portion of the scanning rasterwithoutcausing disturbances in the viewed scene. During the next vertical interval, the functions of the two random access memories are switched.

United States Patent No. 4,353,129 to Nishiwaki (1982) discloses a system for transmitting a coded digital video signal via a buffer memory.

The following prior-ussued United States patents teach performing operations (such as transmission of auxiliary information) in a video system during the vertical and/or horizontal blanking intervals: United States Patent No.4,191,969 to Briand et al (1980); United States Patent No.3,491,199 to Weinstein et al (1970); United States Patent No. 3,961,137 to Hutt et al (1976); United States Patent No. 3,900,887 to Soga et al (1975); United States Patent No. 3,947,870 to Yumde et al (1976); and United States Patent No. 3,982,065 to Barnaby et al (1976).

United States Patent No. 3,337,853 to Harrand (1967) discloses an intermediate storage device for temporarily storing information during information transfer between two processors. A binary pilot bit of information is stored in a control flip-flop having two stable states. The binary pilot information indicates the direction in which the information should be transferred.

Summary of the Invention The present invention is a method and apparatus for transferring information between first and second video information processors. In the present invention, analog video signals are produced and converted by a video controller to digital signals. A buffer memory is provided for storing digital signals. The buffer memory includes at least first and second respective storage segments. A digital signal processor processes digital signals. Signals are selectively communicated between the video controller and the buffer memory and between the buffer memory and the digital processor. The buffer memory is alternately dedicated to the video controller and the digital processor.

Atoken may be passed between the video controller and the digital processor for dedicating the buffer memory to one of the controller and the processor. The video controller may be permitted to communicate with the buffer memory during the vertical blanking interval of the analog video signals, while the digital processor may be permitted to communicate with the buffer memory at times other than during the vertical blanking interval. The buffer memory may be alternately synchronized with the video controller and the digital processor.

The buffer memory may store in the second storage segment those signals communicated to it by one of the video controller and the digital processor when signals stored in the first segment have not yet been communicated to the other one of the video controller and the digital processor. An address storing device may be provided for storing an address of one of the segments of the buffer memory. Addressed signals may be communicated from the video controller to the address storing device and from the digital processor to the address storing device. The address stored in the address storing device may be incremented.

The processor may also generate at least one command specifying a predetermined task. The generated command may be communicated between the processor and the buffer memory and between the buffer memory and the video controller for processing by the video controller. An indication that a command has been communicated by the digital processor to the buffer memory may be produced, and an indication may be produced when the command has been processed by the video controller.

Brief Description of the Drawings These and other features of the present invention will be more completely appreciated by reading the following detailed description taken in conjunction with the accompanying drawings, of which: Figure 1 is a block diagram of one possible arrangement for transferring information between a digital video controller and a digital signal processor; Figure 2 is a block diagram of the presently preferred exemplary embodiment of the present invention; Figure 3 is a more detailed schematic diagram of the CONTROL LOGIC and BUFFER MEMORY blocks shown in Figure 2; Figure 4 is a schematic diagram of a suitable circuit for providing handshaking between the video controller and the digital signal processor shown in Figure 2; Figure 5(A) is a flow chart of the handshaking routine performed by the video controller shown in Figure 2;; Figure 5(B) is a flow chart of the handshaking routine performed by the digital signal processor shown in Figure 2; Figure 6(A) is a timing diagram of the transfer of blocks of information from the video controller to the digital signal processor shown in Figure 2 when the signal processor is capable of processing one block of information between vertical blanking intervals; Figure 6(B) is a timing diagram of the transfer of blocks of information between the video converter and the digital signal processor shown in Figure 2 via a single buffer memory area when the digital signal processor requires a time in excess of the interval between vertical blanking intervals to process one block of information; and Figure 6(C) is a timing diagram of the transfer of blocks of information between the video controller and the digital signal processor shown in Figure 2 in accordance with the present invention when the digital signal processor requires a time in excess of the interval between two vertical blanking intervals to process one block of information.

Detailed Description of the Preferred Embodiment Figure 1 is a block diagram of one possible configuration of a video processing system 10.

Video processing system 10 includes a digital video controller (controller) 12, a digital signal processor (processor) 14 and a bi-directional communications channel 16. Controller 12 is a real-time processor which acquires analog video information from a source of video (such as a camera 18), digitizes the acquired information in a conventional manner, and stores the digitized video information in an internal frame store (not shown). Controller 12 also (simultaneously if desired) accesses digital information stored in its internal frame store, converts the accessed digital information to analog video signals, and controls a conventional video display 20 to display the image represented by the video signals.

Processor 14 is a conventional digital signal processor (such as a microprocessor based digital computer including a random access memory, a read-only memory, a microprocessor, I/O controllers, a clock generator, etc.). Processor 14 performs predetermined processes on digitized video information, such as image enhancement, image analysis, bit shifting, overlay generation, scrolling, video inversion, data compression, etc.

The processes performed by processor 14may vary from one application to another, and may be user-definable in a conventional manner. Processor may communicate to other processors, peripheral devices, etc., via a communications link 15.

Communications channel 16 transfer information from the internal frame store of controller 12 to processor 14, orfrom the processor to the controller frame store. For instance, controller 12 may acquire and digitize a frame of video information and transmit the digitized information to processor 14 for further processing. After processor 14 has processed the information, the processor may transmit the processed (or different) information back to the frame store of controller 12 for display on display 20.

Because the internal frame store of controller 12 is desirably controlled by a sophisticated memory control mechanism (the frame store is typically a dynamic refresh random access memory requiring periodic refreshing) and because controller 12 and processor 14 function at different rates, large amounts of specialized dedicated hardware and a great deal of coordination between processor 14 and controller 12 would be necessary to enable processor 14 to directly access the frame store of the controller. Accordingly, communications channel 16 provides at least one storage buffer accessible by both controller 12 and processor 14 for interfacing processor 14 with the frame store of controller 12.

More particularly, communications channel 16 includes a bi-directional controller data bus 22, a bi-directional processor data bus 24, and latches 26 and 28. Information present on controller data bus 22 can be temporarily stored in latch 26 by controller 12 and applied to processor 14via processor data bus 24. Likewise, information present on processor data bus 24 can be temporarily stored in latch 28 by processor 14 and applied to controller 12 via controller data bus 22. Thus, two uni-directional storage buffers respectively buffer information transmitted by controller 12 to processor 14 and buffer information transmitted from the processor to the controller to accomplish data transfers in either direction.

In the arrangement shown in Figure 1, it is typically impractical to transfer large blocks of information at once unless the I/O ports of controller 12 and processor 14 are very wide (i.e. have a large number of bits) and buses 22 and 24 and latches 26 and 28 are made to have a corresponding width. It is undesirable to multiplex data between controller and controller bus 22 or between processor 14 and processor bus 24 because of the resulting decrease in information transfer rate. Therefore, information may be transmitted via communications channel 16 only in a byte-by-byte format. During information transfer, both controller 12 and processor 14 must be simultaneously engaged in handling the information transferred. Processor 14 must remove the byte of information last stored in latch 26 before controller 12 may transmit a new byte of information.Likewise, controller 12 must remove the information last stored in latch 28 by processor 14 before the processor may store a new byte of information in the latch. Because controller 12 and processor 14 operate at different clock rates, the overhead involved in handshaking the controller with the processor to complete the transfer of a 16x16 pixel (64 byte) block of digitized video information is enormous. Accordingly, the arrangement shown in Figure 1 is disadvantageous in terms of both efficiency and transfer rate.

Figure 2 is a block diagram of the presently preferred exemplary embodiment of a video processing system 50 in accordance with the present invention. Communications channel 16 shown in Figure 1 is replaced by a buffer memory 52, a controller bi-directional tri-state bus driver 54, a processor bi-directional tri-state bus driver 56, a bi-directional data bus 58 and control logic 60.

Controller 12 is connected to controller bus driver 54 via a parallel signal path 62. Processor 14 is connected to processor bus driver 56 via a parallel signal path 64. Controller bus driver 54 and processor bus driver 56 are connected to bidirectional data bus 58 via signal paths 66 and 68, respectively. Buffer memory 52 is connected to data bus 58 via a parallel signal path 70. In the preferred embodiment, data bus 58 is dedicated to bus drivers 54 and 56 and memory 52. Controller 12 and processor 14 each apply control signals to control logic 60 (via control signal paths 72 and 74, respectively), which, in response to the applied control signals, applies control signals to buffer memory 52 via signal path 76.

Controller 12 acquires and displays video information in real time, and is therefore constantly preoccupied with processing information. If controller 12 were required to handle transfers of information at arbitrary times, video acquisition and display might be interrupted, resulting in degradation of the acquired information and/or the displayed image. To prevent information transfer from degrading the performance of controller 12, the information transfer in the present invention takes place only when controller 12 is not busy digitizing or displaying video data. Accordingly, information is transferred to/from controller 12 only during the vertical blanking interval of the composite video signal being processed by controller 12.

Camera 18 and display 20 are both conventional raster scan-type devices in the preferred embodiment. Camera 20 scans its target line-by-line from top to bottom. A complete video frame consists of a 525-line raster. However, in accordance with standard television broadcasting practice, the raster is decomposed into two interlaced 262.5-line rasters. Horizontal and vertical sync pulses mark the beginnings of the horizontal and vertical deflection waveforms of the video signal, respectively. After each 262.5-line raster is completed, the scanning beam is retraced to the upper left-hand corner of the image during a retrace ("fly back") period. During the retrace period, vertical blanking signals are produced to avoid spurious and meaningless video outputs. Accordingly, controller 12 is not occupied with processing video information during the vertical blanking interval.Although the duration of the vertical blanking interval is relatively brief (0.57 milliseconds), it occurs once every 16.67 milliseconds (1/60 of a second). In accordance with the present invention, information is transferred between controller 12 and buffer memory 52 only during the vertical blanking interval to avoid interruption of the real-time processing performed by the controller. Digital signal processor 14 may access buffer memory 52 during the remainder of the time.

Information is transferred from controller 12 to processor 14 in two discrete steps: (1) the information is transferred from controller 12 to buffer memory 52; and (2) the information is subsequently transferred from buffer 52 to processor 14. To transfer information to processor 14, controller 12 applies the information to be transferred to signal path 62 and controls bus driver 54 to take the signal present on signal path 62 and apply itto data bus 58 via signal path 66 (bus driver 54 in the preferred embodiment is a conventional TTL bi-directional tri-state bus transceiver such as a 74LS245 or the like). Controller 12 simultaneously applies appropriate control signals to control signal path 72.In response to the control signals present on control signal path 72, control logic 60 applies appropriate control signals to buffer memory 52 via control signal path 76 to cause the buffer memory to store the information present on data bus 58 (and applied to the buffer memory via signal path 70) in a predetermined memory segment of the buffer memory. Controller 12 in the preferred embodiment transfers an entire block of data to buffer memory 52 during a single vertical blanking interval by rapidly repeating these steps for each word of the block.

At the end of the vertical blanking interval, the block of information now stored in buffer memory 52 is available for access by processor 14. Processor 14 applies appropriate control signals to control logic 60 via control signal path 74to cause buffer memory 52 to place the information stored in the predetermined segment of the buffer memory onto data bus 58 via signal path 70. In the preferred embodiment, processor 14 simultaneously controls processor bus driver 56 to transmit information present on data bus 58 (applied to the bus driver via signal path 68) to the processor via signal path 64.

Processor 14 may store the information so transmitted in an internal random access memory, internal registers, etc., as desired, or may directly process the information to avoid an extra storage step and to conserve memory usage. Processor 14 may transfer information to controller 12 via buffer memory 52 over the same signal paths in a similar fashion.

Figure 3 is a detailed schematic diagram of buffer memory block 52 and control logic block 60 shown in Figure 2. In the preferred embodiment, buffer memory 52 includes a first 1 Kx4 bit random access memory chip 52a and a second 1 Kx4 bit random access memory chip 52b (of course, any number of size random access memory chips could be used).

Random access memory chips 52a and 52b are static RAMs in the preferred embodiment to simplify memory control. Each of random access memory chips 52a and 52b have a 4-bit ADDRESS input, a write enable (WE) control input, a chip select (CS) control input, and a 4-bit DATA input/output. The WE, CS, and ADDRESS inputs of each of RAM chips 52a and 52b are connected in parallel. The DATA input/output of RAM chips 52a is connected via signal path 70a to the lower 4 bits of data bus 58, while the DATA input/output of RAM chip 52b is connected via signal path 70b to the higher 4 bits of the data bus (data bus 58 in the preferred embodiment is 8 bits wide). Hence, buffer memory 52 in the preferred embodiment comprises a 1 Kx8 bit static random access memory (i.e., the memory has 1024 addressable storage locations each of which store one 8-bit word of data).

The ADDRESS inputs of RAM chips 52a and 52b are connected in parallel to the output of a 10-bit programmable counter 78. The DATA input of counter 78 is connected to data bus 58 via an 8-bit wide signal path 70c. When an appropriate signal level is applied to the load (LD) input of counter 78, the contents of the counter are preset at the value applied to the DATA input of the counter. Thus, the counter may be preset to any value in the range of 000 to 3FC in the preferred embodiment by placing the value onto data bus 58 and applying an active signal level to the LD input of the counter. Counter 78 applies sequentially-increasing values beginning at the value to which it has been preset to the ADDRESS inputs of RAM chips 52a and 52b as the counter counts up in response to a clock signal applied to the clock (CLK) input of the counter.The contents of counter 78 may be cleared (i.e., the counter may be reset to 000) by applying an active signal to the clear (CLR) input of the counter.

Controller 12 and processor 14 in the preferred embodiment are capable of independently causing information to be read from or written into specifiable segments of buffer memory 52. In the preferred embodiment, controller 12 selectively applies four control signals to control logic 60 via control signal path 72: CNTR CLK, I/O RD, CNTR EN, CLR (while all of these signals are active-low signals in the preferred embodiment, the "bars" over their designations have been omitted for the sake of convenience). Processor 14 selectively applies the following control signals to control logic 60 via control signal path 74: BUFF MEM R/W, BUFF MEM ADR CNTR ENABLE, BUFF MEM ENABLE, and PROC CLK.While controller 12 and processor 14 could use identical control signals, they need not, and in the preferred embodiment do not (since, in the preferred embodiment, controller 12 is an off-the shelf digital video controller having a predetermined control signal format).

When controller 12 wishes to access (read to or write from) buffer memory 52, it produces an active signal level control signal CNTR EN and also produces CNTR CLK clock (i.e., synchronization) control signals. If controller 12 wishes to write into buffer memory 52, it also produces an active signal level control signal I/O RD. Controller 12 may selectively preset the contents of counter 78 to 000 by producing an active signal level control signal CLR.

Processor 14 can enable buffer memory 52 independently from the actions of controller 12 by producing an active signal level control signal BUFF MEM ENABLE. Processor 14 may also independently cause counter 78 to begin counting by applying an active signal level control signal BUFF MEM ADR CNTR ENABLE to control logic 60.

The clock signal PROC CLK of processor 14 is always present and corresponds to the access time of the processor (compare the CNTR CLK control signal, which is produced by controller 12 only when the controller actually wishes to access buffer memory 52). Processor 14 may cause information to be written into buffer memory 52 by producing an active control signal level control signal BUFF MEM R/W.

The processor clock synchronization signals are gated via a NAND gate 80 by the inverse of a signal TURN (i.e., TURN). The signal TURN is a signal used for handshaking controller 12 with processor 14, and will be described in greater detail inconnection with Figures 4, 5(A) and 5(B). The signal TURN dedicates buffer memory 52 to one of controller 12 and processor 14 depending upon whether it is at a logic 0 level or at a logic 1 level. During the vertical blanking interval, the signal TURN preferably is set to a logic level 0 value, indicating controller 12 has exclusive access of buffer memory 52. During all other times, the signal TURN takes on a logic level 1 value, indicating that processor 14 has exclusive access to buffer memory 52. The processor clock signal appears at the output of gate 80 during times when processor 14 has access to buffer memory 52.

The CNTR CLR signal and the output of gate 80 are applied to respective inputs of a NOR gate 82. Gate 82 produces an output when either of the two signals applied to its input is active. Controller 12 produces CNTR CLK clock signals only when it is entitled to access buffer memory 52. Likewise, gate 80 passes the processor clock signal to the input of gate 82 only when ~processor 14 is entitled to access buffer memory 52. Accordingly, the output of gate 82 (BUFF MEM CLK) is a periodic pulse train which alternates at the synchronization rate of whichever one of controller 12 and processor 14 presently has access to buffer memory 52. The output of gate 82 is used to synchronize the counting rate of counter 78 and the access rate of buffer memory 52.

The BUFF MEM ENABLE and BUFF MEM ADR CNTR ENABLE control signals produced by processor 14 and the CNTR CLK control signal produced by of controller 12 are applied to respective inputs of a 3-input NOR gate 84. Gate 84 produces an active output level whenever information is either to be read from or written into buffer memory 52 by either of processor 14 or controller 12. The output of gate 84 is used to gate the MEM BUFF CLK signal output of gate 82 via-a NAND gate 86. NAND gate 86 passes the synchronization signal output of gate 82 along to the CLK input of counter 78 whenever information is to be read from or written into buffer memory 52, thereby synchronizing the counter (and the access of storage locations of RAM chips 52a and 52b) with the appropriate one of processor 14 and controller 12.

The BUFF MEM R/W control signal produced by processor 14 and the I/O RD control signal produced by controller 12 are applied to respective inputs of an AND gate 88. Gate 88 produces an active signal level output WRITE whenever either processor 14 or controller 12 begins a memory write cycle. The CNTR CLK control signal of controller 12 and the BUFF MEM ENABLE control signal of processor 14 are connected to respective inputs to another NOR gate 90, which produces an active signal level output whenever either controller 12 or processor 14 have enabled buffer memory 52. The output of gates 82, 88 and 90 are connected to respective inputs of a three-input NAND gate 92.NAND gate 92 produces an active signal level- alternating at the clock rate of the one of controller 12 and processor 14 entitled to exclusive access of buffer memory 52 whenever information is to be written into buffer memory 52. The output of gate 92 is applied to the WE inputs of RAM chips 52a and 52b to cause information present on data bus 58 to be written into the location of the memory specified by the output of counter 78.

The BUFF MEM ADDR CNTR ENABLE control signal of processor 14 and the CNTR EN control signal of controller 12 are applied to respective inputs of a two-input NAND gate 94. The output of NAND gate 94 is connected to both the LD input of counter 78 and the CS inputs of RAM chips 52a and 52b. When the signal output by NAND gate 94 is inactive, RAM chips 52a and 52b are disabled and counter 78 is preset to the binary value present on data bus 58. When gate 94 outputs an active signal level, RAM chips 52a and 52b and counter 78 all become enabled.

By applying the described control signals to control logic 60 via paths 72 and 74, controller 12 and processor 14, respectively, can independently cause buffer memory 52 to perform a number of different functions. Controller 12 or processor 14 can place the address of a predetermined location of buffer memory 52 onto data bus 58, and cause the predetermined memory address to be loaded into counter 78. Controller 12 can also cause counter 78 to be cleared (i.e., preset to 000) to address the lowest location of buffer memory 52 (of course, processor 14 can also preset counter 78 to 000 by simply applying a value of 000 to data bus 58).

Controller 12 and processor 14 can control counter 78 to increment its count a predetermined number of times in synchronization with their respective clock signals, thereby causing a block (of predetermined size) of sequential memory locations beginning at the memory address to which counter 78 was preset to be adressed. Controller 12 or processor 14 can either place information onto data bus 58 to be written into this block of addressed memory locations of buffer memory 52, or can read the contents of each of the locations of the block as they appear on data bus 58.

In the preferred embodiment, buffer memory 52 is, in general, dedicated exclusively to controller 12 during the vertical blanking interval, and is dedicated exclusively to processor 14 during all other times. Figure 4 is a schematic diagram of a suitable circuit 96 for handshaking controller 12 and processor 14 so that the controller and processor do not try to simultaneously access buffer memory 52.

In addition, handshaking circuit 96 permits the one of controller 12 and processor 14 which last stored information into buffer memory 52 to characterize the information as either data or command information. The bulk of information transferred between controller 12 and processor 14 is data.

However, the present invention also permits control information to be transferred between controller 12 and processor 14 via buffer memory 52, thereby eliminating the need for a control bus and thus reducing the complexity and cost of system 50.

The handshaking circuit 96 includes a TURN flip-flop 98, a tri-state buffer 100, a COMMAND flip-flop 102, and anothertri-state buffer 104.

Handshaking circuit 96 communicates with processor 14 via an internal processor data bus 106 (which is a different data bus from data bus 58 and is used by processor 14to access the handshaking circuit and other peripheral devices not shonw).

Handshaking circuit 96 communicates with controller 12 via four control lines: CM DACK TURN R, TURN and CMD. The TURN and CMD signals indicate the states of TURN flip-flop 98 and COMMAND flip-flop 102, respectively. Controller 12 can affect the states of TURN flip-flop 98 and COMMAND flip-flop 102 by producing TURNR and CMDACK, respectively. ~~~~~ In the preferred embodiment, the TURN signal takes on a logic level 0 value when controller 12 is entitled to exclusive access of buffer memory 52 (e.g., during the vertical blanking interval), and takes on a logic level 1 value when processor 14 is entitled to exclusive access of the buffer memory (i.e., during all other times). The TURN flip-flop 98 may be viewed as a token passing device which passes a token back and forth between controller 12 and processor 14.The one of controller 12 and processor 14 "possessing" the token is entitled to access buffer memory 52, while the other must wait until the one possessing the token relinquishes it before the other is permitted to access the buffer memory.

After controller 12 has finished accessing buffer memory 52, controller 12 produces an active signal level TURN R, thereby resetting the TURN flip-flop 98 and causing the level of the signal TURN to assume the logic level 1 value (indicating that processor 14 is entitled to exclusive access to the buffer memory 52). Processor 14 ascertains the state of TURN flip-flop 98 by enabling the output of the flip-flop 98 onto processor data bus 106 via tri-state buffer 100 and reading the associated line of the data bus. Processor 14 may access buffer memory 52 if permitted to do so.After accessing buffer memory 52, processor 14 causes TURN flip-flop 98 to set by disabling tri-state buffer 100 and placing a logic "1" signal level onto the line of data bus 106 to which the D input of TURN flip-flop 98 is connected (flip-flops 98 and 102 are clocked by the processor clock signal during times when the processur accesses processor data bus 106). When TURN flip-flop 98 sets, the level of the signal TURN is set to logic level 0, indicating that controller 12 has exclusive access to buffer memory 52 once again.

COMMAND flip-flop 102 is controlled in a manner identical to that of TURN flip-flop 98. When COMMAND flip-flop 102 is set by processor 14, a signal CMD (the Q output of the flip-flop) is at logic level 0, indicating that processor 14 has stored a command in buffer memory 52 to be read and processed by controller 12 (such commands could specify data block size, scan direction, data format, coordinates, etc.). After controller 12 processes the command stored in buffer memory 52, it resets COMMAND flip-flop 102 (by producing an active signal level control signal CMDACK) to acknowledge the command. When the COMMAND flip-flop 102 is reset, the signal CMD rises to logic level 1, indicating that a command has been acknowledged.Processor 14 can determine whether its command was acknowledged by controller 12 by enabling the output of COMMAND flip-flop 102 onto processor data bus 106 via tri-state buffer 104 and testing the level of the appropriate line of the data bus.

Figures 5(A) and 5(B) show the handshaking routines performed by controller 12 and processor 14, respectively. When controller 12 wishes to access buffer memory 52, it first determines whetherthe TURN signal is at logic level 0 (decision block 108). If the TURN signal is not at logic level 0, processor 14 has exclusive access to buffer memory 52, and controller 12 is therefore denied access to the buffer memory. However, if the TURN signal is at logic level 0, controller 12 may access buffer memory 52. Controller 12 then determines whether processor 14 has stored a command in buffer memory 52 (decision block 110). If there is a command stored in buffer memory 52 (i.e., the CMD signal is at logic level 0), controller 12 removes the information stored in buffer memory 52 in a manner described previously, and interprets and executes the command (block 112). Once the command is successfully completed (decision block 116), controller 12 resets COMMAND flip-flop 102 to acknowledge the command (block 118). If the command is not yet successfully completed, the command is not acknowledged. In either case, controller 12 resets TURN flip-flop 98 to permit processor 14to access buffer memory 52 (block 120).

If decision block 110 determined that processor 14 did not store a command into buffer memory 52, controller 12 stores one block of information into the buffer memory to be subsequently transferred to processor 14 for processing (block 114). Alternatively, controller 12 may read data from buffer memory 52 at this time, as appropriate.

Figure 5(B) is a flow chart of the handshaking routine performed by processor 14. When processor 14 wishes to transmit a command or data to controller 12 or receive data transmitted by the controller, it first determines whether the TURN signal is at logic level 1 (decision block 122). If the TURN signal is at logic level 0 (indicating controller 12 has exclusive access to buffer memory 52), processor 14 loops back to the input of decision block 122 to wait for the controller to give the processor access to the buffer memory. If the TURN signal is at logic level 1 (indicating controller 12 has already relinquished access of buffer memory 52), processor 14 writes command and/or data into the buffer memory (or alternatively, reads information from the buffer memory as appropriate) (block 124).

Processor 14 then sets TURN flip-flop 98to give control of buffer memory 52 to controller 12 (and also sets CO M MAN D flip-flop 102 if a command was stored into buffer memory 52 by block 124) (block 126). Processor 14 then waits until controller 12 resets the TURN flip-flop 98 to relinquish control of buffer memory 52 (decision block 128). When processor 14 is once again permitted to access buffer memory 52, the processor determines if controller.12 acknowledged the previously transmitted command (i.e., it determines if CMD is at logic level 1) (block 130). If the command was not acknowledged, processor 14 retransmits the command (blocks 124-128) to permit controller 12 to try to perform the command again. If the command was acknowledged (decision block 130), processor 14 may go on to perform other tasks.Of course, if processor 14 did not transmit a command to be acknowledged, it would not have set COMMAND flip-flop 102, so that decision block 130 would never transfer control back to block 124 (and, in fact, decision blocks 128 and 130 could be bypassed altogether).

In the preferred embodiment, each frame of video information is divided into blocks of 16x16 pixels (each pixel being represented by an 8-bit word).

Controller 12 in the preferred embodiment preferably is fast enough to transfer one 256 byte block of data to or from buffer memory 52 within a single vertical blanking interval. The processing speed of processor 14, however, may vary depending upon, for instance, the complexity and priority of other tasks it is performing. The interval of time between sequential vertical blanking intervals is fixed (equal to 16.67 ms-0.57 ms=16.10 ms) in the preferred embodiment. Hence, processor 14 has only 16.10 milliseconds to process each block of information stored by controller 12 in buffer memory 52 during the previous vertical blanking interval.As shown in Figure 6(A), if processor 14 is capable of processing a block of data in the time between vertical blanking intervals, the effective rate of transfer of data between controller 12 and processor 14 is one block per vertical blanking interval (i.e., controller 12 stores one block of information into buffer memory 52 during each vertical blanking interval, and processor 14 processes the block of data out of the buffer memory before the next vertical blanking interval occurs).However, as shown in Figure 6(B), if the time needed by processor 14 to process a block of information is even slightly greater than the interval of time between vertical blanking intervals, the effective data transfer rate is reduced to only one block of data for every two vertical blanking intervals (processor 14 will not set TURN flip-flop 98 until it is finished with its access of buffer memory 52). The efficiency of system 50 may be decreased substantially, even though processor 14 may be capable of processing a block of information in only slightly greater than the time between vertical blanking intervals, as the processor must wait until the second vertical blanking interval after the one during which data was stored in buffer memory 52 before it receives another block of information from controller 12.

To increase efficiency, the present invention uses a buffer memory 52 which is capable of holding a plurality of blocks of data to be transferred. As will be recalled, counter 78 may be preset to any desired value by either controller 12 or processor 14.

Therefore, controller 12 and processor 14 may access any arbitrary block of buffer memory 52 (in the preferred embodiment, blocks are stored only on predetermined 256 byte boundaries of the memory buffer to simplify memory addressing; however, other arrangements are possible as will be understood by those skilled in the art).

By increasing the size of buffer memory 52 so that the buffer memory may store a plurality of blocks of data simultaneously, controller 12 can store information at a rate at which, at least in the short run, is independent of the rate at which processor 14 processes information. As shown in Figure 6(C), controller 12 stores a block of information in buffer memory 52 upon the occurrence of every vertical blanking interval. During intervals between vertical blanking intervals, processor 14 processes blocks of information stored in buffer memory 52.If controller 12 is permitted to seize control of buffer memory 52 (such as by asynchronously changing the state of TURN flip-flop 98) or if processor 14 is forced to otherwise relinquish control of buffer memory 52 at the beginning of each vertical blanking interval (such as by causing the processor to trap to an interrupt vector at the beginning of each vertical blanking interval), controller 12 may store an additional block of data in buffer memory 52 beginning at the next sequential 256 byte block boundary of available space in the buffer memory even though processor 14 has not yet finished processing the first-transmitted block of information.

Controller 12 may keep track of those blocks of buffer memory 52 which are still available for storage (or other well-known memory allocation algorithms may be used to keep track of which blocks of the memory are available for storing information, e.g., a "free space" list may be maintained in buffer memory 52 itself). Depending upon the size of buffer memory 52 and the longterm equality between the block processing rates of controller 12 and processor 14,there may always be at least one free block of space in buffer memory 52 into which controller 12 may store information.Of course, if no additional free space exists in buffer memory 52 after several blocks of information have been stored in the memory by controller 12, the controller may be forced to wait for processor 14 to complete its processing of a block of data before it can store the next block of data in the buffer memory. However, so long as the average processing rate of processor 14 is greater than 1 block per the interval between vertical blanking intervals, controller 12 will not be forced to wait during short-term decreases in the processing rate of processor 14.

In any event, because processor 14 is permitted uninterrupted access to buffer memory 52 except during vertical blanking intervals and may begin operating on another block of data stored in buffer memory 52 as soon as it is finished processing a first block, the processor 14 is kept busy all the time.

Therefore, the performance of system 50 is improved by increasing the size of buffer memory 52 to store a plurality of blocks of data at once even if the long-term processing rate of processor 14 is less than one block per interval between vertical blanking intervals. Moreover, processor 14 need not be idling during vertical blanking intervals when it is denied access to buffer memory system 52, but may be performing other processes using its own work space (so long as it does not access the buffer memory during this time).

Although the blocks of data have been described as being fixed in length, variable length blocks of data could be used instead. Well-known techniques for indicating the length of the block (such as including header information at the beginning of each block which indicates the block length) can be used. Control information in the preferred embodiment is preferably transmitted using such a variable-block-length format. Processor 14 accesses the plurality of blocks stored in buffer memory 52 in a first-in first-out (FIFO) order in the preferred embodiment, although other sequences of accessing information could be used instead.The beginning location in buffer memory 52 of the next blockto be accessed can be predetermined as the next highest 256 byte boundary of buffer memory 52, or can be obtained in other ways (such as from the last block of information processed).

Although only one exemplary embodiment has been described in detail above, those skilled in the art will appreciate that many variations and modifications may be made without departing from the novel and advantageous features of the invention. For instance, data may be transferred during the horizontal sync or vertical sync pulses of the video signal if desired (so long as enough time is present to make data transfer during these short intervals useful). While buffer memory 52 includes two RAM chips 52a and 52b, any convenient number of RAM chips could be used instead.

Indeed, any sort of information storage device (e.g., dynamic RAM, CCD, bubble memory, etc.) could be substituted for static RAM chips 52a and 52b. Of course, the block size need not be limited to 1 6x 16, and the number of blocks transferred during each vertical blanking interval can be greater than one.

Although in this exemplary embodiment, the digital processor access the buffer memory only after vertical blanking interval, it actually can access the buffer memory as soon as controller release the token even still within vertical blanking interval. The various control signals used by processor 14 and controller 12 to control control logic 60 can comprise any convenient command protocol.

Although logic 60 comprises two levels of discrete digital logic gates for the sake of speed, it will be understood that any convenient signal processing circuit could be used instead (such as a microprocessor or bit slice processor, analog circuitry, etc.). Likewise, other circuit arrangements (such as direct connections between controller 12 and processor 14, etc.) could be substituted for the handshaking circuit arrangement depicted in Figure 4. Although commands are only sent from processor 14 to controller 12 in the preferred embodiment, itwill be understood that with minor modification, bi-directional transfer of control information between the processor and controller could be easily accomplished. Accordingly, all such variations and modifications are intended to be included within the scope of the appended claims.

Claims (27)

1. Avideo processing system comprising: means for producing analog video signals; video controlling means for converting said analog video signals to digital signals; buffer memory means for storing digital signals, said buffer memory means including at least first and second respective storage segments; digital signal processing means for processing digital signals; communicating means for selectively communicating digital signals between said video controlling means and said buffer memory means and for selectively communicating digital signals between said processing means and said buffer memory means; and means for dedicating said buffer memory means alternately to said video controlling means and said processing means.

2. A system as in claim 1 wherein said dedicating means includes means for passing a token between said video controlling means and said processing means.

3. A system as in claim 1 wherein said dedicating means includes: means for permitting said video controlling means to communicate with said buffer memory means during the vertical blanking interval of said analog video signals; and means for permitting said processing means to communicate with said buffer memory means at times other than during said vertical blanking interval.

4. A system as in claim 1 wherein said buffer memory means includes means for storing those signals communicated to it by one of said video controlling means and said processing means in said second storage segment when signals stored in said first segment have not yet been communicated to the other one of said video controlling means and said processing means.

5. A system as in claim 4 wherein: said system further includes address storing means for storing an address of one of said segments of said buffer memory means; and said communicating means also communicates address signals from said video controlling means to said address storing means and communicates address signals from said processing means to said address storing means.

6. A system as in claim 5 further including means for incrementing the address stored in said address storing means.

7. A system as in claim 1 wherein: said processing means includes means for selectively generating at least one command specifying a predetermined task; said video controlling means includes means for processing said command; and said communicating means also communicates said command between said processing means and said buffer memory means and communicates said command between said buffer memory means and said video c.ontrnlling means.

8. A system as in claim 7 further including: means for indicating when a command has been communicated by said processing means to said buffer memory means; and means for indicating when said command has been processed by said video controlling means.

9. A system as in claim 1 wherein said communicating means comprises a bi-directional data bus.

10. A system as in claim 1 further including means for synchronizing said buffer memory means alternately with said video controlling means and said processing means.

11. A method of processing video information comprising the steps of: (1) producing analog video signals; (2) converting said analog video signals to digital signals at a video controller; (3) communicating said digital signals to a buffer memory including at least first and second storage segments; (4) storing said digital signals in one of said first and second storage segments of said buffer memory; (5) communicating signals stored in said buffer memory to a digital signal processor; (6) processing said digital signals at said digital signal processor; and (7) dedicating said buffer memory alternately to said video controller and said digital processor.

12. A method as in claim 11 wherein said dedicating step (7) includes passing a token between said video controller and said digital processor.

13. A method as in claim 11 wherein said dedicating step (7) includes: permitting said video controller to communicate with said buffer memory during the vertical blanking interval of said analog video signals and permitting said digital processor to communicate with said buffer memory at times other than during said vertical blanking interval.

14. A method as in claim 11 wherein said storing step (4) includes the step of storing signals communicated to said buffer memory by said video controller in said second storage segment when signals stored by said video controller in said first segment have not yet been communicated to said digital processor.

15. A method as in claim 11 wherein: said storing step (4) includes the steps of: communicating an address from said video controller to an address specifying means, and writing said digital signals to locations of said buffer memory beginning at the location specified by said address specifying means; and said communicating step (5) includes the steps of: communicating an address of a location in said buffer memory means from said digital processor to said address specifying means, and reading information stored beginning at the location of said buffer memory specified by said address specifying means.

16. A method as in claim 15 wherein said writing step and said reading step each include the step of incrementing the address specified by said address specifying means.

17. A method as in claim 11 further including: selectively generating, at said digital processor, at least one command specifying a predetermined task; communicating said command from said digital processor to said buffer memory; storing said command in said buffer memory; communicating said stored command to said video controller; and processing said command at said video controller.

18. A method as in claim 17 further including: indicating when a command has been communicated by said digital processor to said buffer memory; and indicating when a command has been processed by said video controller.

19. A method as in claim 11 wherein said communicating step (3) and said communicating step (5) each include the step of applying information to a bi-directional data bus.

20. A method as in claim 11 further including synchronizing the buffer memory alternately with said video controller and said digital processor.

21. A method of transferring information between first and second video signal information processors, including the steps of: (1) transferring a first block of data from said first processor to a bi-directional data bus; (2) subsequently to said transferring step (1), storing information present on said data bus in a first storage segment of a storage device including at least first and second storage segments; (3) subsequently to said storing step (2), transferring information stored in said first segment onto said data bus; (4) subsequently to said transferring step (3), transferring information present on said data bus to said second processor; (5) subsequently to said storing step (2), transferring a second block of data from said first processor to said data bus; and (6) subsequently to said transferring step (5), storing information present on said data bus in said second storage segment.

22. A method as in claim 21 wherein: said transferring step (1) and said storing step (2) are performed during a first occurrence of a periodicaily-occurring event; said transferring step (5) and said storing step (6) are performing during a second occurrence of said periodically-occurring event; and said transferring step (3) and said transferring step (4) are performed during the time between said first and second occurrences of said event.

23. A method as in claim 22 wherein said event is the vertically blanking interval of a video signal processed by said first processor.

24. A method as in claim 21 further including: subsequent to said storing step (2) and preceding said transferring step (3), passing a token from said first processor to said second processor; and subsequent to said transferring step (4) and preceding said transferring step (5), passing said token from said second processor to said first processor.

25. A video processing system substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

26. A method of processing video information substantially as hereinbefore described.

27. A method of transferring information between first and second video signal information processors substantially as hereinbefore described.