GB2157926A - Analog display circuit including wideband amplifier for a high resolution raster display - Google Patents

Abstract

In a high resolution raster display (e.g. for air traffic control) a central processor (22) provides image data, a digital image processing circuit (24) converts the image data to display signals, and an analog display circuit (28) converts the display signals to drive signals to form a (preferable color) raster display on a CRT (30). A display memory stores the image data and a programmable attribute look-up table stores attribute data. Under the control of the central processor, the image data in the display memory is read out and addresses the attribute look-up table which provides attribute signals as output. A pixel rate converter reads in the attribute signals at a first rate and outputs analog display signals at a much higher second rate, with a video bandwidth of up to 210 MHz. The central processor can also provide intensity control signals to the analog display circuit so that the intensity level of each of the attributes identified by the attribute signals can be varied. The display signals are amplified by a current switching amplifier with a separate channel for each category of pixel, the output being converted to a voltage signal to drive the gun or guns of the CRT. <IMAGE>

Description

SPECIFICATION Analog display circuit including a wideband amplifier circuitfora high resolution raster display system This application is related to our application entitled "Circuitfor Processing Digital Image Data in a High Resolution Raster Display System" filed on the same day as the subject application and claiming priority from U.S. application Serial No. 600,980.

This invention relates to high resolution raster display systems and particularly to an analog display circuit including a wideband amplifier circuit for use in such a system.

There exists, in the prior art, a variety ofsystemsfor displaying data, including systems for direct viewing of a cathode ray tube (CRT), systems for projection viewing of a CRT, and flat screen systems (e.g., LED displays, plasma display panels, flat CRT panels, etc.).

In addition, different systems existfor generating the display for use in a particular display system. These display generation systems include raster scan display systems and stroke writer systems.

Recently, there has been an increased concern with air safety and, in particular, with the quality of air traffic control. This has lead to a study of the air traffic control equipment presently being used, and particularlythe displays used in such equipment. It has been found thatthis equipment should be improved and made uniform. In an effortto update the airtraffic control system in the United States, the FAA is seeking to provide air traffic control work stations which are standardized to have a 20" x 20" display of at least 2000 by 2000 pixels (where a pixel is defined as the smallest addressable dot which can be displayed on a screen).The FAA has also required th at these displays be capable of providing shaded background areas and a color display.

Displays used in air traffic control have traditionally used stroke writertechnology which is capable of providing clear,flicker-free presentations of lines and characters at acceptable brightness levels. However, with this type of display system, it is difficult to provide shaded background areas and to provide a color display. In particular, in order to provide shaded areas on the display, a high power deflection system would be required to move the beam fast enough to create a shaded area. In addition, it would be necessary to provide new equipment in order to generate a color display.

In contrast to stroke writer systems, raster display systems (e.g., standard television) consume relatively less power, have no background shading problem, and currently are capable of providing a color display.

However, currently available raster displays are not capable of providing the large viewing area and high resolution required for certain applications, including the large screen, high resolution requirements ofthe FAA.

At present, commercial television provides 525 horizontal lines which are interlaced 2 to 1, with a 30 hertz refresh cycle. In addition,there are approximately 300 pixels per horizontal line on the display. Thus, the requirement of a display of 2000 lines by 2000 pixels imposes substantially greater data handling requirements on the display system than does commercial television.

Today, a high quality raster display is capable of providing 1280 by 1024 pixels and requires 100 to 120 MHz video bandwidth (as opposed to the commercial broadcast video bandwidth which is approximately 3 MHz). In contrast, the provision of a display of 2048 by 2048 pixels (rounding the 2000 x 2000 pixel requirement to a power of 2), interlaced 2 to 1, with a refresh cycle of 40 hertz, requires a video bandwidth of approximately 210 MHz.

In addition to the FAA requirements, it is desirable that an airtraffic control display have high resolution as well asthe capability of displaying various characteristics (e.g., weather, data, flight path, emergency situations, map area, etc.) in a flexible manner which can be altered by an operatorwho isviewing the display, thereby providing the operator an opportunityto more clearly interpretthe data being displayed by adjusting the relative intensity of selected portions ofthedisplay.Thistypeofflexihledisplaywould also allow an airtrafficcontrollerto clarify what he or she sees on the display and to obtain a better view of particular portions ofthe display (e.g., by brightening or damming certain displayfeatures) in an effort two clarify the image as seen by the operator.

In addition to the need for the above-discussed type of display for use in airtraffic control work stations, there is a general need in the display art for large, high resolution displays for use in a variety of industries.

For example, such high resolution displays would be advantageous for use as monitors in the fields of computer graphics, CAD/CAM, medicine, defense and other fields.

Therefore, there is a need in the display art, for circuitry capable of processing digital image data art a high data rate in order to provide the processed image data as display signals for use in a high resolution raster scan display system. There is also a need for such processing circuitry which allows certain attributes ofthe display to be programmable, so that the display can be programmed to display different types offeatures as required fordifferenttypes of displays.

Further, there is a need for analog display circuitry which is capable of receiving the high speed display signals and driving high resolution raster displays.

There is also a need for analog circuitry which is capable of changing the relative display intensities of certain features ofthe display.

SUMMARY OF THE INVENTION It is an object ofthe present invention to provide an analog displaycircuitfora high resolution raster display system which overcomes the deficiencies inherent in prior art display systems.

In particular, it is an objectofthe present invention to provide an analog display circuit which includes a wideband amplifier circuit for receiving displaysignals at a high rate and for converting the display signals to drive signals for driving the color guns of a CRT,sothatthe rasterdisplaysystem is capable of providing a high resolution raster display.

Afurtherobjectofthe present invention is to provide a wideband amplifiercircuitwhich employs high speed current switching to generate the drive signals on the basis ofthe display signals input to the analog display circuit.

A still furtherobject ofthe present invention is to provide a wideband amplifier circuit which includes a plurality of digital to analog converters connected to receive operator controlled intensity control signals and which provide a voltage output signal to current switching circuits so thatthe current output by the current switching circuits (and thus the level ofthe drive signals) can be varied under operator control. In this manner, the operatorwho is viewing the high resolution raster display is capable of altering the intensity of selected portions ofthe display so as to make iteasierforthe operatorto discern the different features present on the display.

The analog display circuit ofthe present invention has a number of novel features as set forth below. The analog display circuit includes a wideband amplifier circuitfor providing drive signals to the color guns of a CRTand display drive circuitfor providing a sweep the CRT. The wideband amplifier circuit includes one amplifier circuit for each ofthe color guns ofthe CRT, and each amplifier circuit includes ten channels, a main currentsource connected to the ten channels and a currentto voltage converter connected to the outputs of the ten channels. Each of the channels includes a digital to analog converter circuitfor receiving an operator controlled intensity control signal from a central processor and for outputting a voltage output signal having a level which is dependent upon the intensity control signal.Each channel also includes a current switching circuitwhich is connected to one often differential lines which provide a display signal from a pixel rate converter in a digital image processing circuit. Each current switching circuit is also connected to the output ofthe digital to analog convertercircuitso that it receives the voltage output signal from that circuit. When the display signal is provided on the differential line from the pixel rate converter to the current switching circuit, a switching signal is generated, and the current switching circuit provides a current output signal to the currentto voltage converter.The current to voltage converter convertsthe current output signal to a drive signal which comprises voltagesfordriving the grid and cathode ofthe CRT. The display drive circuit comprises a combination of a linear amplifier and a resonant amplifier, so that the sweep signal provided to the CRT has the advantages of a controlled sweep and a fastflyback operation.

The analog display circuit ofthe present invention is capable of receiving the high speed display signals provided bythe digital image processing circuit and outputting the drive signals at a high rate, so that the raster display system is capable of providing a high resolution, flicker4ree, raster display. In addition, the provision ofthe operator controllable digital to analog converter circuit allows the operatorto vary the intensity level of each channel (i.e., features) being displayed on the CRT independently. For example, if the operatorwants to brighten certain alphanumeric data, he or she can varythe intensity control signal inputto the digital to analog convertercircuitto highlightthis data.This type of fine tuning adjustment is particularly advantageous for an airtrafficwork station where numerous different types of data are being displayed on the screen at one time. Thus, the high speed operation ofthewideband amplifier circuit results in a high resolution display which is especially advantageous for monitoring air traffic. In addition, the circuit ofthe present invention is particularly suitable for use in othertypes of display systems which require a high resolution image. These additional applications might include use in computergraphics display systems, display systems used in medicine (e.g., diagnostic equipment), CAD/CAM systems and complex display systems used in military operations.

Thesetogetherwith other objects and advantages, which will become subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals referto like parts throughtout.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. its a block diagram of one type of display system in which the analog display circuit ofthe present invention can be employed; FIG. 2 is a block diagram of the digital image processing circuit 24 of FIG. 1; FIG. 3 is a block diagram ofthe graphics processor 32 of FIG. 2; FIG. 4is a block diagram of the display memory 34 of FIG.2; FIGS.SAand 5B are flow charts describing the operation of the central processor 22 of FIG. 1 in controlling the graphics data controllers 44 and 46 of FIG. 3to write data into the display memory 34 and to read data from the display memory34; FIG. 6 is a block diagram ofthe attribute look-up table 38 of FIG.2; FIG. 7 is a block diagram ofthe pixel rate converter 40OfFIG.2; FIG. 8 is a block diagram ofthe analog display circuit ofthe present invention which receives display signals from the digital image processing circuit 24 of FIG.1; FIG. 9 is a block diagram ofthe amplifier circuit 108 ofFIG.8;; FIG. is a schematic diagram ofthe digital to analog convertercircuit 116, the current switching circuit 118, the main current source 120 and the currentto voltage converter circuit 122 of FIG. 9; and FIG. 11 is a schematic diagram of the display drive circuit 114Of FIG.8.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. is a block diagram of a display system in which the analog display circuitofthe present invention can be employed. In particular, FIG. is a block diagram of a part of a common console 20 which is used to generate the main displayfor viewing by an airtrafficcontroller. In practice, the common console 20 also includes an auxiliary display, a data entry display, a keyboard, a trackball, an alarm, and touch entry devicesforeach ofthe displays. Each air traffic control center includes a plurality of common consoles, each of which has a central processor 22 connected to one or more center minicomputers. In turn, the center minicomputers are inter-connected to a main host computer.Forconvenience, FIG. 1 only indicates that the central processor 22 is capable of being connected to peripherals and center minicomputers in orderto makeitclearthatthecentral processor 22 is capable of receiving image data which is to be displayed on the main display ofthe common console 20.

Referring to FIG. 1, the central processor 22 provides digital image data (e.g., from the center minicomputer) to a digital image processing circuit 24 which is the subject ofthe present invention. In the preferred embodiment, the central processor 22 is a Motorola MC 68020 microprocessor and is connected to the digital image processing circuit 24 via a bus 26. In the preferred embodiment, the bus 26 is a Motorola VME bus. The central processor 22 is also connected to an analog display circuit 28, via the bus 26, in orderto provide intensity control signals to the analog display circuit 28 under the control of an operator (e.g., an air traffic controller).The digital image processing circuit 24 of the present invention receives the image data from the central processor 22, and generates display signals for a monochrome display or a color display (i.e., red, blue and green display signals) at a rate of 210 mega-pixels per second. The digital image processing circuit 24 also provides a sync signal to the analog display circuit 28. The analog display circuit 28 generates three voltage output signals which are received buy a CRT 30 (which is the main display of the common console 20) for control ofthe red, blue and green color guns which are used to form the display.

The analog display circuit 28 also receives the intensity control signals from the central processor 22 and varies the intensity of selected features displayed on the screen of the CRT 30 underthe control ofthe operator. The analog display circuit 28 also generates a sweep signal in dependence upon the sync signal generated by the digital image processing circuit 24, and the sweep signal is used to control the horizontal sweep ofthe CRT3O.

As discussed above, the system of FIG. 1 was particularly designed as a part of a common console 20 for use in an air traffic control work station. Thus, in orderto meet FAA requirements regarding display size (20" x 20") and resolution, the circuit ofthe present invention was designed to generate data for a picture of 2048 by 2048 pixels with a 2 to 1 interlaced raster, a 40 hertz frame, and an 80 hertz field rate.The horizontal scanning frequency is 82.2 kilohertz and the video bandwidth required is 210 MHz. The use ofthese specifications meets all FAA resolution requirements, provides a color display, and overcomes background shading problems which are present in othertechnologies. Inthepreferredembodiment,theCRT30 incorporates the SonyTrinitron color system which provides significant advantages for use in a high resolution display. At the presenttime, Sony does not produce a commercially available 20" x20" CRT; however, Sony does produce a 30" diagonal CRT which can be used to generate a "scaled down" 1792 by 1792 pixel display of 18" by 18".Thus, the Sony 30" diagonal CRT can be used in conjunction with the digital image processing circuit 24 ofthe present invention to produce a display having substantially higher resolution than is currently available.

FIGS. 2-7 are diagrams ofthe details of the digital image processing circuit 24. The digital image processing circuit 24 is the subject matter of the related U.S.

application entitled "Circuitfor Processing Digital Image Data in a High resolution Raster Display System", by Nelson et al.,filed on the same date as the subject application and assigned to the assignee of the su bject application, the disclosure of which is hereby incorporated by reference.

FIG. 2 is a block diagram ofthe digital image processing circuit 24 of FIG. 1. The digital image processing circuit 24 includes a graphics processor 32 which receives image data from the central processor 22 overthe bus 26. The graphics processor 32 provides address data and write data to a display memory 34 over a graphics bus 36. The display memory 34 is arranged so that memory address is directly related to screen position on the CRT 30. When data is read from the display memory34, underthe control of the graphics processor 32, the image data (8 bits per pixel) which is read from the display memory 34, is used to address an attribute look-up table 38.The attribute look-up table 38 is programmable and stores attribute data which allows the 8 bits per pixel read from the display memory 34to have any desired meaning in terms of the features which appear on the screen of the CRT 30. For example, attributes can be used to designate layers on a map. The layers could include a geographical map layer, a data block layer, a weather layer, a flight plan layer, etc. By selectively changing the attributes stored in the attribute look-up table 38, a layer can be taken away, returned, its color changed, etc. For applications relating to air traffic control, radar aircraft displays are used and text information is often overlaid on the same display (e.g., a flight plan). The operator mightwantto switch immediatelyfrom a map display to a text display and the attributes required would be completely different.

For example, in a text display, it might be desirable to have an underlying reverse video blinking particular data, while the radar display might have different colors forweather, targets, etc. Sets of attributes stored the attribute look-up table can include 256 different colors on the screen, requirements that certain portions of the screen blink, an independent map, an independent set of symbols for aircraft, data, for weather etc. Thus, the provision ofthe programmable attribute look-up table 38 prevents the display system from being rigidly bound to a specific set of attributes. This is in contrast to many prior art displays wherein the display memories are divided into pixel memory planes which are assigned a specific function by hard wiring. For example, two planes might be assigned for red color pixels, two planes for blue color pixels and two for green color pixels, etc. This type of preassignment restricts the flexibility of the display.

For example, ifonlytwo planes per color are assigned, the pixel is then limited to four intensity levels per color, which may be inadequateforcertain colors, and overly adequate for other colors.

The attribute look-up table 38 can be programmed through the central processor 22 to assign attributes tothe 256 codes possiblewhen 8 bits per pixel are employed. That is, the content of each address in the attribute look-up table 38 can be set via software from the central processor22to adjust the meaning to be given to an 8-bit pixel stored in the display memory 34.

This provides enormous flexibility and, for example, allows both monochrome and color modes of operation to be readily available. In the monochrome mode the attribute look-up table 38 can be programmed with a set of data which enables only the green beam in the CRT30 and usesthe 8-bits per pixel stored in the display memoryto provide numerous intensity levels forthe green beam. Then, when a color display isto be generated, the attribute look-up table 38 can be reloaded with different data to trade off some ofthe intensity variation in the green beam for other color variation. This can be done without altering any hardware, merely by changing the data stored in the attribute look-up table 38.

In the preferrred embodiment, 16 pixels of 8 bits each (128 bits) are read from the display memory 34 and are input in parallel to the attribute look-up table 38 which converts the 8 bits of pixel data into 4 bits of intensity data for each color gun (i.e., red, green and blue). Then, attribute signals, consisting of 16 pixels of 12 bits each, are output bythe attribute look-uptable 38.The attribute signals are providedtothe pixel rate converter 40 which includes a master clock oscillator running at MHz. The master clock is divided down and provided to the g raphics processor 32, the display memory 34 and the attribute look-up table 38.The graphics processor 32 generates horizontal and vertical raster synchronization timing for inputto the analog display circuit 28 on the basis ofthe clock signal input to the graphics processor 32.

The primary function ofthe pixel rate converter 40 is the serialization ofthe pixel data atthe2i0 MHzvideo rate, wherein the attribute signals (i.e, pixel data) is transmitted from the attribute look-up table 38 in wide parallel words at a 13 MHz rate. The pixel rate converter 40 decodes the serialized pixel data and outputs the result as the display signals to the analog display circuit 28. As discussed in detail below, there are 10 possible display signals output by the pixel rate converter 40 for each ofthe color guns ofthe CRT30.

Part ofthe coding originating in the attribute look-up table includes data indicating the type of pixel to be displayed (e.g., a data pixel, a map pixel, a background pixel, control target pixel, flight path pixel, etc.) and the type or category of pixel is distinguished because it is necessary to be able to separately adjust each type of pixel regardless of its color. For example, if the map pixels have been assigned a green color and the operator changes the intensity ofthe data blocks, they should all change. If the attribute look-up table 38 is then loaded with information which makes the map pixels blue, then the operator must be able to employ the same intensity control to changethe intensity of the blue map pixels.Thus, there is provided, independent intensity control for nine classifications ortypes of pixel and a background.

In the preferred embodiment, the pixel rate converter40 is housed adjacent a portion oftheanalog display circuit 28 and is physically separated from the remainder ofthe digital image processing circuit 24. In essence, bus data width is traded for clock rate to accommodate the physical separation between the pixel rate converter 40 and the remainder ofthe digital image processing circuit 24. This also allows all ofthe high speed digital and analog circuitry to be confined to one physical location for ease of EMI containment.

FIG. 3 is a block diagram ofthe graphics processor 32 of FIG. 2. The graphics processor 32 operates under the control ofthe central processor 22 and does not control the bus 26, but instead receives data from the bus 26. The bus 26 provides 16 bits of data, 24 bits of address and control signals to a bus interface 42. Two graphics data controllers 44 and 46 are connected to the bus interface 42. In the preferred embodiment, the graphics data controllers 44 and 46 are NEC 7220 LSI Graphics Display Controllers. The graphics data controller46 generates and controls input of symbol, vector, arc and circle pixel patterns which are written into the display memory 34via a write data multiplexer48 and a first in, first out data buffer 50.In addition, a direct access path 52 is provided, soth at the central processor 22 can provide or receive data directly to/from the display memory 34 orthe attribute look-up table 38, via the direct access path 52 and the graphics bus 36. Alternatively, the central processor 22 can provide data to the display memory 34 via the write data multiplexer48,the data buffer 50 and the graphics bus 36. If the central processor 22 is to write data directly intothe display memory34 it mustfirst verify that the graphics data controller 46 is not currently writing data into the display memory 34. The central processor 22 knows when the graphics data controller 46 is writing data in the display memory 34 because the graphics data controller 46 operates under the control of the central processor 22.Thus, the central processor 22 and the graphics data controller 46 share one port to the display memory 34. If the central processor 22 does not provide write data through the direct access path 52 orthewrite data multiplexer48, then command data is provided to eitherthe graphics data controller44orthe graphics data controller 46. The graphics data controller 44 is dedicated to refreshing the screen by sending address data to the display memory 34, via an address multiplexer 45 and the graphics bus 36, for display on theCRT30,sothatthe display memory 34 is sequenced through its storage locations as the screen is refreshed.The central processor 22, the graphics data controller 44 and the graphics data controller 46 share access to the display memory 34 at all times. An address multiplexer 47 is used to select which of the graphics data controller 46 and the central processor 22 is to have access to the display memory 34, and the address data is provided to an address buffer 51. The address multiplexer 45 selects which ofthe output of the address buffer 51 and the graphics data controller 44 is to have access to the display memory 34. The timing is divided into phases, so thatthe graphics data controller44 is able to havethe display memory 34 read out image data which is to be displayed on the CRT 30, because the screen must always be refreshed.

Atiming circuit 54 receives 13 MHzand 26 MHzclock signals from the pixel rate converter 40 and provides a timing signal to a syne ti ming circuit 56 which alternately generates a first clock signal (Clock 1) and a second clock signal (Clock 2) for input to the graphics data controller 44 and the graphics data controller 46, respectively. The first clock signal enables the graphics data controller44to generate a read address signal for reading data from the display memory 34, and the second clock signal enables the graphics data controller46 to write data into the display memory 34.

The timing circuit 54 also provides a row address signal (RAS), a column address signal (CAS) and a read/write signal (RNV) to the display memory 34 via the graphics bus 36.

FIG. 4 is a block diagram ofthe display memory 34 which is mainly comprised of a memory 58 including 256K dynamic RAMS which are organized in 8 pixel planes. Each plane includessixty-four256 K DRAMsto provide the capacity for maintaining four separate images (i.e.,fourindependent 2048x 2048 pixel "pages") in memory 58. Thus, one of the pages can be selected for display, whilethe otherthree may be written into concurrently.The address multiplexer 45 provides address data to an address multiplexer 60 and a page and bank select circuit 62, via the graphics bus 36, to addressthe memory 58. In dependence upon the address data, 64 sequential horizontal pixels of 8 bits each (i.e., one bit from every DRAM in memory 58) are read outduring a single read cycleas determined by a timing/control inputto the memory 58. This occurs at a 3.3 MHz rate. An output buffer 64 provides image data comprising 16 pixels of 8 bits each (128 bits) to the attribute look-up table 38.

The display memory 34 also includes an attribute register 66 for designating the attribute of a pattern to be written on the screen. For example, the data stored in the attribute register indicates whether the type of pixel to be written in memory is a line pixel, character pixel, map pixel, etc. The page and bank (in the page) in memory which are to be written into are selected via the page and bank select circuit 62 and a select/timing circuit 63, and a plane enable mask 68 and a pixel mask 70 are set. Data is written into the memo ry 58 by enabling the memory 58 (E input) for storing the type of data indicated by the attribute register 66 for up to 16 pixel planes.The plane enable mask 68 allows only selected planes of the memory 58 to be written into, while the pixel enable mask performs a similar function with respect to the number of pixels to be written into simultaneously. The central processor 22 and the graphics data controller 46 are capable of writing-in 16 different pixels (128 bits) simultaneously.

Thus, the pixel enable mask can be used to limitthe number of pixels to be written into to less than 16, for example, in dependence upon the width of a character on a particular line, etc. The central processor 22 operates asynchronously with respect to the display system, so that it is necessary for the central processor 22 to monitorthe output ofthe memory 58 through a data output register 72. Due to the large amount of data output by the memory 58, the central processor 22 provides the select signal,via the graphics bus 36, to an output bankselectcircuit74which selectsonlya portion ofthe data from the data output regsiter72.

FIGS. SA and 5B are flow charts for illustrating the operation ofthe central processor 22 and its control of the graphics data controller 44 and the graphics data controller 46 in the graphics processor 32. Referring to FIG. 5A, the central processor 22 initializesthesystem by setting attributes in the attribute look-up table 38, setting the plane enable mask 68, and setting the pixel enable mask 70. After initialization, the graphics processor 36 receives image data for display and determines whether the graphics data controller 44 has been selected.If the graphics data controller 44 has been selected, the central processor 22 formats a command for the graphics data controller44 and transmits the command to the graphics data controller 44using thetransmitcommand subroutine (FIG. 5B).

If the graphics data controller 44 is not selected, the central processor 22 determines whether the graphics data controller 46 has been selected to write data into the display memory 34. If so, the central processor 22 selects the memory access state forthe graphics data controller46,formats a command forthe graphics data controller46 and executesthetransmitcom- mand subroutine. If the graphics data controller46 has not been selected to access the display memory 34, the central processor22 determines whether it will access the display memory 34 directly. If so, the central processor 22 selects the direct access state and stores the data in the display memory 34. The central processor 22 then returns to receive more image data for display.If the central processor 22 is not to access the RAM directly, it also returnsto receive more image data for display.

In the transmit command subroutine (FIG. 5B), the central processor 22 determines whether the selected graphics data controller (44 or46) is not occupied. If it is occupied, then the central processor 22 returns and tests again. Ifthe selected graphics data controller (44 or46) is not occupied, the central processor 22 tests to determine whether the command data buffer is empty (i.e., whetherthere are other commands waiting to be carried out), and if it is not, testing continues until the command data buffer is empty. If the command data buffer is empty, the central processor 22 stores a command in the internal memory of the selected graphics data controller (44 or 46) stores the parameters (i.e., data) in parameter memory locations, and returns to the main program to receive more image data for display.

As discussed above, in the preferred embodiment, the graphics data controllers 44 and 46 are formed by NEC 7220 LSl Graphics Display Controllers. Accor- dingly, once the central processor 22 has provided the graphics data controllers 44 and 46 with the appropriate command and parameters, the graphics data controllers 44 and 46 operate underthe control oftheir own internal programs to output the necessary data.

FIG. 6 is a block diagram ofthe attribute look-up table 38 of FIG.2. The attribute look-up table 38 convertsthe8bitsofpixel data provided by the display memory 34 into 4 bits of intensity data for each ofthethree electron guns ofthe CRT 30 (i.., 12 bits total). The output buffer 64 ofthe display memory 34 provides groups of 16 pixels of 8 bits each in parallel (i.e., 128 bits total) at 13 MHzto an address multiplexer 76. The attribute look-up table 38 includes a red attribute look-up table 78, a green attribute look-up table 80 and a blue attribute look-up table 82. Each of these tables (78,80 and 82) are formed by 1K by 8 RAMS. Due to the amount of data being output by the display memory 34, each of the tables (78,80 and 82) includes 16 identical sets of attributes, so that all 16 pixels read from the display memory 34 at onetime can be used to address a set ofthe attribute look-up table 78,80 and 82 at the same time. Thus, for each pixel, the 8 bits defining the pixel are used to address one set of each of the look-up tables 78,80 and 82.

Based on the 8 bitinputforeach pixel into the tables 78,80 and 82,12 bits are output as an attribute signal to the pixel rate converter 40. The output data stream ofthe attribute look-up table 38 includes 16 pixels of 12 bits each clocked at 13MHz. In an alternate embodiment, the 8-bit input for each pixel is used to generate an 8-bitoutputfrom each ofthetables78,80and82. In this manner,finercolorcontrol can be obtained if desired.

The central processor 22 has access to the tables 78, 80 and 82 to allow the attribute associated with any 8 bit pixel code to be changed by a software modification. The appropriate one ofthe tables 78,80 and 82, and the write address within the tables, are designated by address data sent by the central processor 22 via the address multiplexer76 anda writecolorselect circuit 84. A data buffer 86, and blue, green and red input data circuits 88,90 and 92 are employed to write the new attribute into the indicated address in all 16 sets ofthe designated one ofthe tables 78,80 and 82.

The modification ofthetables 78,80 and 82 occurs only during the vertical retrace and therefore occurs instantaneously without disrupting the display. The blue, green and red input data circuits 88,90 and 92 are shadow RAMS which temporarily store attribute data to be written into the tables 78,80 and 82 and then write the new data into the tables 78,80 and 82 when the screen is not active. In the preferred embodiment, the RAMS forming the look-up tables 78,80 and 82 have sufficient capacityto storeseparate attribute codingforeach of the four pages of the display memory 34. This is particularly advantageous when the display memory 34 stores different kinds of displays (i.e., on each of its four pages) forwhich different attribute tables are desired.Thus, the provi sion or ofstoragefor separate coding offourattribute tables provides significant advantages with respect two displayflexibility. Further, the additional storage may be used to provide different attributes forthe same display. For example, it might be desirableto change colors, etc. for certain portionsofthe display. These sets of attributes could be assigned to different planes in the display memory 34 and the attributes could be readily changed and brought back to vary the color of different features on the display.

FIG 7 is a block diagram ofthe pixel rate converter 40 of FIG. 2 which receives the attribute signals from the attribute tables 78,80 and 82 (FIG. 5). The pixel rate converter includes a 210 clock 94 and a counter 96 for providing timing, not onlyforthe pixel rate converter 40 but also for the graphics processor 32, the display memory34and the attribute look-up table 38. The pixel rate converter 40 includes TTLto ECL converter circuits 98 for converting the attribute signals to a high speed logic family. In the preferred embodiment, Fairchild 100KfamilyECLintegrated circuits are employedfortheTTLto ECL converter circuits 98.The outputs of the TTLto ECL converter circuits 98 arethen fed through sync registers 100 to multiplexers 102. The sync registers 100 are provided fortiming purposes and the multiplexers 102 speed up the data rate by a factor of 16 by receiving 64 bits and outputting 4 bits at 16 times the rate. The outputs of the multiplexers 102 are sentthrough sync registers 104to decoders 106 which decode the 4 bit outputs of the sync registers 104 and provide an output (a display signal) on one often differential line outputs for each ofthe decoders 106.

The outputs ofthesync registers 104comprise 12 bits which are clocked at 210 MHz. Each set of 4 bits corresponds to an input to one of the three color guns in the CRT30, and must be synchronized to better than 0.5 ns to meet the convergence requirements of the display. Each setof4 bits which is input to the decoders 106 must be synchronized to 0.5 ns to ensure proper response ofthe decoders 106 and the analog display circuit 28. In addition, the edges of the pulses input to the analog display circuit 28 must be faster than 1 ns to guarantee proper switching. It is for this reason that 100Kfamily ECL logic circuitry is employed to achieve the desired performance requirements.The pixel rate converter 40 converts (i.e., serializes) a 16 pixel stream down to one pixel which is output at 1 6times the rate. It is because of this high data rate (210 MHz) that the pixel rate converter 40 must be located as close as possible to the wideband amplifier which forms a portion ofthe analog display circuit 28. It is the operation ofthe pixel rate converter 40 which allows the digital image processing circuit to provide210 million pixels per second at4 bits per color gun. In addition, since the pixel rate converter 40 receives input data at a 13 MHz rate, this allows data processing ata slower rate until just prior to inputto the analog display circuitry 28.

FIG. 8 is a block diagram ofthe analog display circuit 28 ofthe present invention. The analog display circuit 28 includes first, second and third amplifier circuits 108, 110 and 112which form a wideband amplifier, so that an amplifier circuit is provided for each ofthe red, blue and green color guns ofthe CRT 30. Each of the amplifier circuits 108, 110 and 112 receives the display signal output by the corresponding one ofthe decoders 106 in the pixel rate converter 40 (FIG. 7) and generates the corresponding red, blue or green drive signal for inputto the CRT 30. The analog display circuit 28 also includes a display drive circuit 114 which receives the sync signal output by the digital image processing circuit 24 and provides a sweep signal for controlling the scan of the CRT 30.

FIG. 9 is a block diagram of one of the amplifier circuits (e.g., amplifier circuit 108) in FIG. 8. The amplifier circuit illustrated in FIG. 9 is provided for each ofthe amplifier circuits 108,110 and 122 in FIG. 8.

The amplifier circuit 108 includes ten channels 115, each of which includes an operator adjustable digital to analog converter circuit 116 (which is connected to the bus 26to receive an intensity control signal from the central processor22) and a current switching circuit 118. Each digital to analog converter circuit 116 provides a voltage output signal to the current switching circuit 118 which is connected to receive a current from a main current source 120. The current switching circuits 118 are respectively connected to the ten differential line outputs of the decoder circuit 106 connected to the amplifier 108. During a raster scan, one ofthe ten differential line outputs is selected for each pixel by the decoder circuit 106 and a display signal is generated, so that only one oftheten current switching circuits 118 is selected at any one time.Each ofthe ten differential line inputs to the current switching circuits 118 (and thus, each of the ten channels 115) corresponds to a particular attribute of the display, for example, background map, symbolo- gy, weather information, alphanumerics, flight paths, radar, etc. The display signal output by each decoder 106 selects one of the ten attributes for each pixel and acts as a switching signal forthe differential line input of only that current switching circuit 1 which is selected. The selected current switching circuit 118 provides a current output signal to a current to voltage converter circuit 122 which generates the drive signal (in this case the red drive signal) forthe CRT 30.

FIG. is a schematic diagram illustrating the details of one channel 115 (i.e., one ofthe digital to analog converter circuits 116 and one ofthe current switching circuits 118) and its connection to the main current source 120 and the cu rrentto voltage converter 122. The digital to analog converter circuit 116 includes an 8 bit D/A converter 124 and an operational amplifier 126. The 8 bit D/A converter 124 receives, as the intensity control signal, an 8 bit digital intensity control setting from the central processor 22, via the bus 26. Since the D/Aconverter 124 is 8 bit, it can be set to 256 different values, so that as the operatorvaries these 256 settings, the corresponding output channel can assume any one ofthe 256 values.Similarly, each ofthe D/A converters 124 in the other digital to analog converter circuits 116 can assume any different set of 256 values. For display purposes, the human eye is capable of distinguishing only approximately 20 different levels, so the capability of providing 256 different levels for each of the channels effectively means that each of the channels is continuously adjustable. The operator is allowed to adjust each of the channels 115 separately (for example, by use of a touch entry display), thereby causing the central processor 22 to send a new 8 bit digital intensity control setting to the channel 1 to be adjusted.

The 8-bit D/Aconverter 124 outputs a current (in dependence upon the 8 bit digital intensity control setting) to the operational amplifier 126 which provides a voltage signal outputto the current switching circuit 118. The current switching circuit 118 comprises high speed ECL switching circuitry, and the voltage across the emitter resistors 119 determines how much current is conducted through each current switching circuit 118. By varying the inputto the D/A converter 124,theoutputvoltageoftheoperational amplifier 126 is varied, and the current capable of flowing through the current switching circuit 118 is varied. The current switching circuit 118 also includes an ECL line receiver 128 which is connected to one ofthe differential line outputs ofthe corresponding decoder 106.If the current switching circuit 118 in the channel 115 illustrated in FIG. is selected, then the ECL line receiver 128 generates a switching signal to cause currentfrom thee main current source 120 to flow through the current switching circuit 118, so thatthe current switching circuit 118 generates a current output signal to the currentto voltage converter 122. It should be noted that the outputs of the current switching circuit 118 are tied together to provide two inputs to the currentto voltage converter 122 because only one of the current switching circuits 118 is selected at a particulartime.In summary, the current switching circuit 118 is switched ON and OFF independence upon the differential line inputfrom the decoder circuit 106, to allow current from the main current source 120 to flow into the current switching circuit 118; and the voltage output ofthe digital to analog converter circuit 116 determines the amount of currentwhich is allowed to flow through and be output by the current switching circuit 118. It is necessary to use a current switching circuit 118 instead of a voltage switch because of the high speed operation requiredforthe high resolution raster display generated by the circuit of the present invention.That is, the current switching circuit 118 must be capable of switching at a rate of 210 MHz (i.e., one oftheten channels is selected for each and every pixel 210 million times a second). Itwould not be possible to have a voltage switch perform this function because ofthe capacitances in such a system.

The current to voltage converters 122 is a common base amplifier, wherein the current outputs ofthe current switching circuit 118 are applied to the emitters of transistors 130 and 132. Thus, the switching circuit 118 acts as a variable current source input to the current to voltage converter 122. The drive signal output of the current to voltage converter (essentially a voltage difference) drives the grid in one direction and the cathode in a different direction, so that there is a voltage difference between the two. This voltage difference is translated into a brightness difference.

If color intensity levels are being used as the only attributes forthe display, at any one time it is possible to have nine different brightness levels (for each color) on the screen; however, any one ofthese nine levels can be varied (via the D/A converter 124) to take on 256 different individual levels. In the preferred embodiment, there are nine differentvariable levels (co rresponding to channels 1 through 9) and a tenth channel which is referred to as "black". This is because the grid output ofthe currentto voltage converter 122 is capacity coupled, so that it cannot carry DC components. Therefore, a diode 134 is used to provide a DC restore level to generate the "black" level. Thus, nine ofthe channels are operator adjustable and the tenth channel provides a maintenance adjustment.In the preferred embodiment, the nine adjustable channels are employed to provide six simultaneous display brightness levels (with the brightness of each level individually and continuously adjustable by the operator) and three adjustable shading levels.

In the preferred embodiment, the pixel rate converter40 and at least a portion of the analog display circuit 28 are built as a hybrid circuit. In particular, it is necessarythatthe outputs ofthe pixel rate converter 40 and the inputs ofthe current switching circuits 118 be essentially in contact with each other because of the high rate at which the data is being processed.

Ideally, the pixel rate converter40 and the amplifier circuits 108,1 10 and 112 are built as a hybridcircuitto ensure the ability of the system to provide 2110 Mhz operation. If the system is instead built from discrete components, then a video bandwidth offrom 160 to 180 MHz can be expected. Whilethis will provide a displaywith substantially higher resolution that is presently available, the use of hybrid circuitry enables the desired high resolution requirements set forth above to be achieved.

FIG. 11 is a block diagram of the display drive circuit 114of FIG. 8. Priorartstrokewriters have used an operational amplifierfeedbackcircuitasa liner deflection amplifier. However, this type of system requires a substantial amountofpowerto movethe currentthrough the deflection yoke quickly. On the other hand, commercial television employs a capacitor and deflection yoke in combination with a switch which is opened and closed to provide a high speed sweep generator. Such a resonant system does not require large amounts of power, but also lacks the control provided by the linear deflection amplifier system used in the stroke writers.

As illustrated in FIG. 11, the display drive circuit 114 used with the present invention is a combination of a linear deflection amplifier and a resonant amplifier. As illustrated in FIG. 11, the display drive circuit 114 includes a geometry correction amplifier 134 and a switching circuit 136 coupledto a transistor 138 which is connected at the output of the geometry correction amplifier 134. Wheneverthe switching circuit 136 is closed and scanning is actuallytaking place, the display drive circuit 114functions as a linearfeedback amplifierwith a current being provided through a deflection yoke 140, and the voltage across a resistor 142 being fed back to an input of the geometrical correction amplifier 134.When rapid flyback is re quired,theinputsyncsignal causes the switching circuit 136 to switch and the display drive circuit 114 becomes a resonant amplifier. Thus, in one circuit, the power conserving advantages of a fastflyback re sonant amplifier and the control advantages of a linear amplifier, are obtained. The central processor 22 provides geometry control signals to the inputs of the geometry correction amplifier134in orderto compen sate forthe different distances which the electron beam musttravel in the CRT 30 before striking the screen. For example, an electron beam focused on a corner ofthe screen travels a much greater distance than a beam striking the center ofthe screen.The geometry control signals provided by the central processor 22 compensate forthis, so thatthe display provided on the CRT30 is not distorted.

The operation ofthe analog display circuit 28 of the present invention is as follows. Amplifier circuits 108, 110 and 112 (FIG. 8) receive intensity control signals from the central processor and display signals which are output by the digital image processing circuit 24.

Each of the amplifier circuits include ten channels 115, a main current source 120 and a currentto voltage converter 122 (FIG. 10). Each channel is connected to one often differential line outputs from a decoder 106 in the digital image processing circuit 24 and is also connected to receive an intensity control signal. The digital to analog converter circuit 116 provides a voltage output signal, in dependence upon the intensity control signal, to the current switching circuit 118. When a display signal is received on the differential line inputto the current switching circuit 118, the voltage output signal from the digital to analog converter circuit determines the amount of currentflowing through the current switching circuit 118, and thus determines the current output signal of the channel.The current to voltage converter circuit 122 receives the current output signal and provides a drive signal for the corresponding color gun in the CRT30.

The analog display circuit ofthe present invention provides significant advantages for high resolution raster display systems because of its wide video bandwidth. Further, the ability of an operatorto vary the intensity of each ofthechannels in thewideband amplifier provides significant advantages with respect to manipulating the display so that selected features ofthe display are made to stand out. While the analog display circuit of the present invention has been described in the context of a common console for an airtraffic control station, the analog display circuit of the present invention is applicable to anytype of raster display system where a high resolution display is required.For example, the analog display circuit of the present invention would be particularly suitable for use in computer graphics display systems, CAD/CAM systems, medical diagnostic systems employing a display, and militarymonitorsystems. Further,while the analog display circuit ofthe present invention has been described in the context of generating a color display,the same circuitry can also be used to generate a monochrome display. In this case, an even greater number of attributes may be made available for display on the screen of the CRT 30.

The manyfeatures and advantages ofthe invention are apparentfrom the detailed specification and thus it is intended by the appended claims to cover all such features and advantages of the system which fall within the true spirit and scope ofthe claims. Further, since numerous modifications and changes will readi ly occurto those skilled in the art, it is not desired to limitthe invention to the exact construction and operation shown and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the claims.

Claims (23)

1. An analog display circuit, operatively connected to receive a display signal for each pixel of an image to be displayed, for driving a CRT in a raster display system, comprising: means for generating intensity control signals; and amplifier means, operatively connected to said generating means, operatively connected to the CRT and operatively connected to receive the display signal, for generating a drive signal for driving the CRT in dependence upon the display signal and one of the intensitycontrol signals, said amplifier means comprising:: a plurality of channels, operatively connected to said generating means and operatively connected to receive the display signal, for generating a current output signal in dependence upon the display signal and oneofthe intensity control signals, each of said channels having a differential line input,the number of channels corresponding to the number of different categories of pixels which can be displayed on the screen ofthe CRT, the display signal for each pixel being input only on the differential line input of a selected one ofsaid channels in accordance with the pixel category to be displayed on the screen, so that only the selected one of said channels generates the currentoutputsignal;; and a current to voltage converter circuit, operatively connected to said channels and to the CRT, for generating the drive signal in dependence upon the current output signal.

2. An analog display circuit as set forth in claim 1, wherein each of said channels comprises: a digital to analog converter circuit, operatively connected to receive one ofthe intensity control signals, for generating a voltage output signal in dependence upon the received intensity control signal; and a currentswitching circuit, operatively connecting to said digital to analog converter circuit, said current to voltage converter circuit and said differential line input of said channel, for providing the current output signal in dependence upon the voltage output signal of said digital to analog converter circuit when said differential line input receives the display signal, the level ofthecurrentoutputsignal being varied in dependence upon the intensity control signal input to the digital to analog converter circuit, so that the intensity ofthe displayed pixels corresponding to the pixel categoryforthat channel, can be varied under the control ofthe intensity control signal.

3. An analog display circuit as set forth in claim 2, wherein saidcurrentswitching circuit is an emitter coupled logic circuit.

4. An analog display circuit as set forth in claim 3, wherein said current switching circuit comprises: an emitter coupled logic line receiver, operatively connected to said differential line input, for generating a switching signal when said differential line input receives the display signal; a switch, operatively connected to said emitter coupled logic line receiver, for providing a current signal in dependence upon said switching signal; and a differential amplifier, operatively connected to said switch, said digital to analog converter circuit and said currentto voltage converter circuit, for providing the current output signal to said currentto voltage converter circuit when said switch provides the current signal.

5. An analog display circuit as set forth in claim 1, wherein said generating means includes means for varying the level ofthe intensity control signals, so thatthe intensity of the displayed pixels corresponding to the pixel category for each channel can be varied independently underthe control ofthe corresponding intensity control signal.

6. An analog display circuit as set forth in claim 1, wherein said analog display circuit is operatively connected to receive a sync signal, further comprising a display drive circuit, operatively connected to the CRT and operatively connected to receive the sync signal,forgenerating a sweep signal in dependence upon the syncsignal.

7. An analog display circuit as setforth in claim 6, wherein said display drive circuit comprises: a linear amplifier having an input and an output; a transistor having a first terminal connected to the output of said linear amplifier at a first node, having a second terminal and having a third terminal; a capacitor having a firstterminal operatively connected at said first node and having a second terminal operatively connected to said third terminal of said transistor at a second node; a deflection yoke having a first terminal operatively connected at the second node and having a second terminal operatively connected to the input of said linear amplifier, the sweep signal being generated through said deflection yoke;; a resistor having a firstterminal operatively connected to the input of said linear amplifier and having a second terminal operatively connected to a reference potential; and switching means operatively connected to receive the syne signal and coupled to said second terminal of said transistor, said switching means for turning said transistor on and off in dependence upon the sync signal.

8. An analog display circuit, operatively connected to receive three display signals for each pixel of an imageto be displayed,for driving first, second and third color guns of a CRT in a raster display system, comprising: meansforgenerating intensity control signals; and first, second and third amplifier circuits, operatively connected to said generating means and respectively, operatively connected to receive the three display signals, each of said first, second and third amplifier circuits operatively connected to a corresponding one ofthefirst, second and third color guns of the CRT, for providing first, second and third drive signals, respectively, in dependence upon the three display signals and the intensity control signals, each of said first, second and third amplifier circuits comprising:: a plurality of channels, operatively connected to said generating means and operatively connected to receive a corresponding one ofthe three display signals, for generating a current output signal in dependence upon the display signal and one of the intensity control signals, each of said channels having a differential line input, the number of channels corresponding to the number of different categories of pixels which can be displayed on the screen of the CRT, the display signal for each pixel being input only on the differential line input of a selected one of said channels for each pixel in accordance with the pixel categoryto be displayed on the screen, so that only the selected one of said channels generates the current output signal; and a current to voltage converter circuit, operatively connected to said channels and to the corresponding one ofthe first, second and third color guns of the CRT, for generating the corresponding one ofthe first, second and third drive signals in dependence upon the current output signal.

9. An analog display circuit as set forth in claim 8, wherein each of said channels comprises: a digital to analog converter circuit, operatively connected to receive one of the intensity control signals, for generating a voltage output signal in dependence upon the received intensity control signal; and a current switching circuit, operatively connected to said digital to analog converter circuit, said currentto voltage converter circuit and said differential line input of said channel, for providing the current output signal in dependence upon the voltage outputsignal of said digital to analog converter circuit when said differential line input receives the display sig nai, the level ofthecurrent output signal being varied in dependence upon the intensity control signal input to the digital to analog converter circuit, so that the intensity ofthe displayed pixels corresponding to the pixel categoryforthat channel, can be varied under the control ofthe intensity control signal.

10. An analog display circuit as set forth in claim 9, wherein said currentswitching circuit is an emitter coupled logic circuit.

11. An analog display circuit as setforth in claim 10, wherein said current switching circuit comprises: an emitter coupled logic line receiver, operatively connected to said differential line input, for generating a switching signal when said differential line input receives the display signal; a switch, operatively connected to said emitter coupled logic line receiver, for providing a current signal in dependence upon said switching signal; and a differential amplifier, operatively connected to said switch, said digital to analog converter circuit and said currenttovoltage convertercircuit,for providing the current output signal to said current to voltage converter circuit when said switch provides the current signal.

12. An analog display circuit as setforth in claim 8, wherein said generating means includes means for varying the level ofthe intensity control signals, so that the intensity of the displayed pixels correspond ing to the pixel categoryforeach channel can be varied underthe control of the corresponding intensity control signal.

13. An analog display circuit as set forth in claim 8, wherein said analog display circuit is operatively connected to receive a sync signal, further comprising a display drive circuit, operatively connected to the CRT andoperatively connected to receive the sync signal, for generating a sweep signal in dependence upon the syne signal.

14. An analog display circuit as setforth in claim 13, wherein said display drive circuit comprises: a linearamplifierhaving an input and an output; a transistor having a firstterminal connected to the output of said linear amplifier at a first node, having a second terminal and having a third terminal; a capacitor having a first terminal operatively connected at said first node and having a second terminal operatively connected to said third terminal of said transistor at a second node; a deflection yoke having a firstterminal operatively connected atthe second node and having a second terminal operatively connected to the input of said linear amplifier, the sweep signal being generated through said deflection yoke;; a resistor having a firstterminal operatively connected to the input of said linear amplifier and having a second terminal operatively connected to a reference voltage; and switching means operatively connected to receive the sync signal and coupled to said second terminal of said transistor, said switching means for turning said transistor on and off in dependence upon the sync signal.

15. An analog display circuit as setforth in claim 13, wherein each of said channels comprises: a digital to analog converter circuit, operatively connected to receive one of the intensity control signals, for generating a voltage output signal in dependence upon the receiving intensity control signal; and a current switching circuit, operatively connected to said digital to analog converter circuit, said currentto voltage converter circuit and said differential line input of said channel, for providing the current output signal in dependence upon the voltage output signal of said digital to analog converter circuit when said differential line input receives the display signal, the level of the current output signal being varied in dependence upon the intensity control signal input to the digital to analog converter circuit, so that the intensity level ofthe display pixels corresponding to the pixel categoryforthatchannel, can be varied underthe control ofthe intensity control signal.

16. An analog display circuit as setforth in claim 15, wherein said current switching circuit is an emitter coupled logic circuit.

17. An analog display circuit as set forth in claim 16, wherein said current switching circuit comprises: an emitter coupled logic line receiver, operatively connected to said differential line input, for generating a switching signal when said differential line input receives the display signal; a switch, operatively connected to said emitter coupled logic line receiver, for providing a current signal in dependence upon said switching signal; and a differential amplifier, operatively connected to said switch, said digital to analog converter circuit and said currentto voltage converter circuit, for providing the current output signal to said current to voltage converter circuit when said switch provides the current signal.

18. An analog display circuit as setforth in claim 17, wherein said generating means includes means for varying the level of the intensity control signals, so that the intensity ofthe displayed pixels corresponding to the pixel category for each channel can be varied under the control ofthe corresponding intensi ty control signal.

19. An analog display circuit, operatively connected to receive display signals corresponding to pixels to be displayed, for driving a CRT in a raster display system in dependence upon the display signals, comprising: means for providing a plurality of voltage output signals; a plurality of current switching means operatively connected to said means for providing a plurality of voltage output signals, said plurality of current switching means operatively connected to receive the voltage output signals and respectively operatively connected to receive the display signals, each of said plurality of current switching means for providing a current output signal in dependence upon the respective display signal and the voltage output signals received by said each current switching means; and a plurality currentto voltage converter means, respectively, operatively connected to said plurality of current switching means and operatively connected to the CRT,forconverting the current output signals output by said plurality of current switching means to corresponding drive signals for driving the CRT.

20. An analog display circuit as set forth in claim 19, further comprising means for providing a plurality ofvariable intensity control signals, wherein said means for providing a plurality of voltage output signals comprises a plurality of digital to analog converter means, operatively connected to said means for providing a plurality of variable intensity control signals and respectively operatively connected to said plurality of current switching means, wherein each of said plurality of digital to analog converter means receives said variable intensity control signals and provides the voltage output signalsto the corresponding one of the said plurality ofcurrentswitching means, and wherein the voltage output signals arevaried in dependence upon the variable intensity control sig nals, so thatthe drive signals output by said plurality ofcurrentto voltage converter means are varied to change the intensity of a portion ofthe display on the screen ofthe CRT.

21. An analog display circuit as setforth in claim 20, wherein each ofthe said plurality of digital to analog converter means comprises a plurality of digital to analog converter circuits, operatively connected to said means for providing a plurality of variable intensity control signals, wherein each of said plurality of digital to analog converter circuits generates one ofthe voltage output signals in dependence upon the variable intensity control signal inputto said digital to analog converter circuit, wherein each of said digital to analog converter circuits corresponds to a predetermined category of pixel to be displayed on the screen of the CRT, wherein each of said plurality of current switching means comprises a plurality of current switching circuits, each of which has a differential line input capable of receiving the corresponding one of the display signals, and wherein said current switching circuits are respectively operatively connected to said digital to analog converter circuits to receive the voltage output signals ofthe digital to analog converter circuits and to provide the current output signal in dependence upon the one of said current switching circuits which receives the display signal on its differential line input.

22. An analog display circuit as setforth in claim 21, wherein said analog display circuit is operatively connected to receive a sync signal, further comprising drive means, operatively connected to receive the sync signal and operatively connected to the CRT, for generating a sweep signal to control the scanning of the CRT.

23. An analog display circuit as setforth in claim 22, wherein said drive means comprises: a linear amplifier having an input and an output; a transistor having a first terminal connected to the output of said linear amplifier at a first node, having a second terminal and having a third terminal; a capacitor having a first terminal operatively connected at said first node and having a second terminal operatively connected to said third terminal of said transistor at a second node; a deflection yoke having a firstterminal operatively connected at the second node and having a second terminal operatively connected to the input of said linear amplifier, the sweep signal being provided through said deflection yoke; ; a resistor having a first terminal operatively con nected tothe input of said linearamplifier and having a second terminal operatively connected to a reference potential; and switching means, operatively connected to receive the sync signal and coupled to said second terminal of said transistor, said switching means for turning said transistor on and off in dependence upon the sync signal.