GB2149581A - Mounted integrated circuit chip carrier - Google Patents

Mounted integrated circuit chip carrier Download PDF

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Publication number
GB2149581A
GB2149581A GB08330160A GB8330160A GB2149581A GB 2149581 A GB2149581 A GB 2149581A GB 08330160 A GB08330160 A GB 08330160A GB 8330160 A GB8330160 A GB 8330160A GB 2149581 A GB2149581 A GB 2149581A
Authority
GB
United Kingdom
Prior art keywords
chip carrier
solder resist
solder
mounted chip
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08330160A
Other versions
GB8330160D0 (en
GB2149581B (en
Inventor
Crofton John Brierley
David John Pedder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB08330160A priority Critical patent/GB2149581B/en
Publication of GB8330160D0 publication Critical patent/GB8330160D0/en
Publication of GB2149581A publication Critical patent/GB2149581A/en
Application granted granted Critical
Publication of GB2149581B publication Critical patent/GB2149581B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0577—Double layer of resist having the same pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A mounted chip carrier comprising a ceramic substrate (3) on which an integrated circuit chip (1) is supported and which embodies contact pads (4) electrically coupled to the chip and soldered to conductive pads (10) on a circuit board (9) fabricated of a plastics material, thereby to provide solder links (11) by means of which the circuit board is mechanically coupled to the carrier substrate, the circuit board being spaced apart from the carrier substrate by a plurality of regions of solder resist (12, 13) which are at least about .004 of an inch thick whereby the thickness of the solder links is defined correspondingly so that the thickness of the solder links is sufficient to withstand the stress associated with thermal cycling in use of the mounted chip carrier. <IMAGE>

Description

SPECIFICATION Mounted chip carrier This invention relates to chip carriers and more especially it relates to mounted chip carriers.
A chip carrier comprises a ceramic substrate on which an integrated circuit chip is supported and which embodies contact pads electrically coupled to the chip and adapted and arranged to be soldered to a circuit board thereby to provide solder links by means of which the substrate and the board are mechanically coupled, as well as affording electrical interconnections between the substrate and the board.
A chip carrier mounted as just before described on a board must be capable of satisfactory operation over a wide range of temperatures and in particular the solder links between the carrier substrate and the board on which it is mounted must withstand various operating temperatures without any tendency to mechanical failure.
It has been found that the solder links are perfectly satisfactory provided the board and the carrier substrate have the same or similar temperature coefficients of expansion. Thus if the carrier substrate and the board are both fabricated of the same material, which is usually a ceramic material, the solder links therebetween give no trouble when subjected to temperature cycling.
If on the other hand the carrier substrate is made of ceramics material but the board is made of a plastics material such as epoxy/glass then since the temperature coefficient of these two materials is significantly different, differential movements between the board and the carrier substrate occur with temperature cycling, which stress the solder links and which accordingly may cause mechanical and electrical breakdown of the solder links.
It is an object of the present invention to provide a mounted chip carrier wherein the chip carrier substrate is made of ceramic material and the board on which it is mounted is made of an epoxy/ glass material, and wherein the risk of breakdown of solder links therebetween with temperature cycling is obviated or at least significantly reduced.
According to the present invention a mounted chip carrier comprises a ceramic substrate on which an integrated circuit chip is supported and which embodies contact pads electrically coupled to the chip and soldered to conductive pads on a circuit board fabricated of a plastics material, thereby to provide solder links by means of which the circuit board is mechanically coupled to the carrier substrate, the circuit board being spaced apart from the carrier substrate by a plurality of regions of solder resist which are at least about .004 of an inch thick whereby the thickness of the solder links is defined correspondingly so that the thickness of the solder links is sufficient to withstand the stress associated with thermal cycling in use of the mounted chip carrier.
It will be appreciated from the following disclosures that by defining the spacing between the board and the carrier substrate with regions of solder resist whereby the thickness of the solder links is defined as aforesaid, the solder links are appropriately lengthened whereby stress in the links produced consequent upon temperature changes is effectively reduced to an acceptable level.
One layer of currently available solder resists would be insufficient to provide the required thickness, and although special resists could be produced which would be suitable, it is probably preferable to achieve the required thickness by defining the regions with more than one layer.
Preferably the regions comprises two layers.
The two layers may comprise two layers of dry film solder resist.
Alternatively the two layers may comprise one layer of silk screen applied solder resist and one layer of dry film solder resist.
The layer of silk screen applied solder resist may be applied before the dry film layer.
The regions may comprise a plurality of small pillars of solder resist.
The regions may be about .05 of an inch square.
The regions may be about .008 of an inch thick.
One embodiment of the invention will now be described solely by way of example with reference to the accompanying drawing which is a somewhat schematic sectional view of a part of a mounted chip carrier.
Referring now to the drawing, a mounted chip carrier comprises an integrated circuit chip 1 which is bonded to a gold flashed nickel coated tungsten pad 2 on a ceramic substrate 3. The ceramic substrate 3 embodies a number of gold flashed nickel coated tungsten contact pads 4 only one of which is shown in the drawing to which a terminal 5 on the integrated circuit chip is connected by means of a contact wire 6. One surface part of the contact pad 4 is protected by means of a ceramic layer 7 but an edge portion 8 of the contact pad 4 is exposed. The ceramic substrate 3 of the chip carrier is mounted on an epoxy/glass printed circuit board 9 which includes a copper printed conductor 10 to which the contact pad 8 is bonded with solder 11.
In order to define the spacing between the ceramic substrate 3 of the chip carrier two layers 12 and 13 of dry film solder resist are laid down on a surface 14 of the printed circuit board 9 and photo-etched away to define a spacer pillar 15. Although only one spacer pillar 15 is shown in the drawing, a plurality of spacer pillars will be provided which serve to define the thickness of solder between the ceramic substrate 3 of the chip carrier and the conductors 10 on the surface of the printed board 9.
As has been hereinbefore explained, if the thickness of solder is not sufficient, excessive sheer stresses are set up in the solder due to differential movements produced between the ceramic substrate 3 and the printed circuit board 9 consequent upon temperature changes. These movements are due to the fact that the temperature coefficient of expansion of the printed circuit board material 9 is significantly different from the temperature coefficient of expansion of the ceramic substrate 3.
However, by providing spacers such as the spacer pillars 15, the thickness of the solder 11 be tween the contact pad 8 and the conductor 10 is arranged to be at least .004 of an inch which has been found to be sufficient to reduce sheer stresses, which would otherwise cause the solder to fracture, to an acceptable level.
Although the solder resist spacer pillar 15 may be fabricated in any convenient manner it has been found particularly convenient to fabricate the pillar using two layers of dry film solder resist which are laid one upon the other in a conventional manner and etched. Alternatively however the layer 15 could be laid down using silk screen techniques and overlaid with a layer of dry film resist to form the layer 12.
Various modifications may be made to the arrangement shown in the drawing without departing from the scope of the invention and for example a cover may be provided which serves to protect the chip.

Claims (9)

1. A mounted chip carrier comprising a ceramic substrate on which an integrated circuit chip is supported and which embodies contact pads electrically coupled to the chip and soldered to conductive pads on a circuit board fabricated of a plastics material, thereby to provide solder links by means of which the circuit board is mechanically coupled to the carrier substrate, the circuit board being spaced apart from the carrier substrate by a plurality of regions of solder resist which are at least about .004 of an inch thick whereby the thickness of the solder links is defined correspondingly so that the thickness of the solder links is sufficient to withstand the stress associated with thermal cycling in use of the mounted chip carrier.
2. A mounted chip carrier as claimed in claim 1 wherein the regions of solder resist each comprise more than one layer.
3. A mounted chip carrier as claimed in claim 1 or claim 2 wherein the regions of solder resist comprise two layers of dry film solder resist.
4. A mounted chip carrier as claimed in claim 1 or claim 2 wherein the regions of solder resist comprise a layer of silk screen applied solder resist and a layer of dry film solder resist.
5. A mounted chip carrier as claimed in claim 4 wherein the layer of silk screen applied solder resist is applied before the dry film layer.
6. A mounted chip carrier as claimed in any preceding claim wherein the regions of solder resist comprise a plurality of pillars of solder resist.
7. A mounted chip carrier as claimed in claim 6 wherein the pillars are about .05 of an inch square.
8. A mounted chip carrier as claimed in any preceding claim wherein the said regions are about .008 of an inch thick.
9. A mounted chip carrier substantially as hereinbefore described with reference to the accompanying drawing.
GB08330160A 1983-11-11 1983-11-11 Mounted integrated circuit chip carrier Expired GB2149581B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08330160A GB2149581B (en) 1983-11-11 1983-11-11 Mounted integrated circuit chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08330160A GB2149581B (en) 1983-11-11 1983-11-11 Mounted integrated circuit chip carrier

Publications (3)

Publication Number Publication Date
GB8330160D0 GB8330160D0 (en) 1983-12-21
GB2149581A true GB2149581A (en) 1985-06-12
GB2149581B GB2149581B (en) 1987-05-28

Family

ID=10551629

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08330160A Expired GB2149581B (en) 1983-11-11 1983-11-11 Mounted integrated circuit chip carrier

Country Status (1)

Country Link
GB (1) GB2149581B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0322121A1 (en) * 1987-11-28 1989-06-28 British Aerospace Public Limited Company Surface mounting leadless components on conductor pattern supporting substrates
EP0352183A1 (en) * 1988-07-20 1990-01-24 Matra Marconi Space France Process for mounting electronic micro components on a support, and intermediate product
EP0376055A2 (en) * 1988-12-27 1990-07-04 Asea Brown Boveri Ag Method of soldering a wireless component and circuit board with a soldered wireless component
EP0631461A1 (en) * 1993-06-24 1994-12-28 Kabushiki Kaisha Toshiba Electronic circuit device
US5684677A (en) * 1993-06-24 1997-11-04 Kabushiki Kaisha Toshiba Electronic circuit device
EP0888037A1 (en) * 1997-06-25 1998-12-30 Ford Motor Company Anti-tombstoning solder joints
WO2021144067A1 (en) * 2020-01-13 2021-07-22 Delphi Technologies Ip Limited Printed circuit board and fabrication thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0322121A1 (en) * 1987-11-28 1989-06-28 British Aerospace Public Limited Company Surface mounting leadless components on conductor pattern supporting substrates
EP0352183A1 (en) * 1988-07-20 1990-01-24 Matra Marconi Space France Process for mounting electronic micro components on a support, and intermediate product
FR2634616A1 (en) * 1988-07-20 1990-01-26 Matra METHOD FOR MOUNTING ELECTRONIC MICRO-COMPONENTS ON A SUPPORT AND PRODUCT REALIZABLE BY THE METHOD
EP0376055A2 (en) * 1988-12-27 1990-07-04 Asea Brown Boveri Ag Method of soldering a wireless component and circuit board with a soldered wireless component
EP0376055A3 (en) * 1988-12-27 1990-10-10 Asea Brown Boveri Ag Method of soldering a wireless component and circuit board with a soldered wireless component
EP0631461A1 (en) * 1993-06-24 1994-12-28 Kabushiki Kaisha Toshiba Electronic circuit device
US5684677A (en) * 1993-06-24 1997-11-04 Kabushiki Kaisha Toshiba Electronic circuit device
EP0888037A1 (en) * 1997-06-25 1998-12-30 Ford Motor Company Anti-tombstoning solder joints
WO2021144067A1 (en) * 2020-01-13 2021-07-22 Delphi Technologies Ip Limited Printed circuit board and fabrication thereof
CN114514799A (en) * 2020-01-13 2022-05-17 德尔福知识产权有限公司 Printed circuit board and its manufacture

Also Published As

Publication number Publication date
GB8330160D0 (en) 1983-12-21
GB2149581B (en) 1987-05-28

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PCNP Patent ceased through non-payment of renewal fee