GB2148069A

GB2148069A - Video processing circuit

Info

Publication number: GB2148069A
Application number: GB08327566A
Authority: GB
Inventors: Nicholas James Richards
Original assignee: Marconi Avionics Ltd
Current assignee: Allard Way Holdings Ltd
Priority date: 1983-10-14
Filing date: 1983-10-14
Publication date: 1985-05-22
Also published as: GB2148069B; GB8327566D0

Abstract

A video processing circuit receives a video signal consisting of alternate video fields relating to two different information channels. The two channels are separated by routing each video field to a common field store and to a respective output port. The gaps in each channel at the output port are filled by repeating a field from the store. The store is organised so as to minimise the required storage capacity. <IMAGE>

Description

SPECIFICATION Video processing circuit This invention relates to a video processing circuit, and is specifically concerned with the handling of a video signal which includes information relating to more than one video channel.

According to this invention a video signal processing circuit includes means for receiving a video signal comprising sequential video fields relating to two different video channels; means for routing each received video field to a common store in turn in the order in which video fields are received, and for directly routing the video fields relating to particular channels to respective output ports; means for reading out from the common store a stored video field relating to one of said channels when a video field relating to the other channel is received, and for routing the stored video field to its respective output port, so that the two output video signals each consist of a regular stream of video fields some of which repeat.

Preferably the common store has a capacity which is in excess of one video field by an amount which is small compared with a video field, and is arranged such that the commencement of a video field is read into the excess capacity whilst a preceding video field is read out.

In this way a succeeding video field is stored in a different region of the store which largely overlaps the previously used store region. This permits efficient usage to be made of the available storage capacity, and allows a new video field to be entered into the store whilst the old video field is being read out. The store capacity required to hold an entire video field is substantial. In an embodiment of the invention, the video fields are connected to a digital format for storage, and this requires a store capacity of about 1.5 Ambits.

In one example of the invention, the received video signal contains two channels, one of which relates to a colour signal originating from one source, and the other channel of which relates to a monochrome signal originating from another source. The two channels are combined to form a single video signal with alternate video fields of the video signal relating to the different channels.

The invention is further described by way of example, with reference to the accompanying drawing, in which: Figure 1 shows in schematic form a video signal processing circuit, and Figures 2a and 2b are explanatory diagrams.

Referring to Figure 1, a video signal is received at terminal 1, and is fed to a time base corrector 2, where its chrominance carrier is brought into synchronism with that of a reference frequency from a master sync pulse generator 3. The received video signal comprises two quite separate channels; channel A which is a full colour channel and channel B which is a monochrome channel, and video fields of the two channels occur alternately in the video signal. Thus each channel contains only half the number of video fields, and the unwanted video fields are discarded prior to transmission.

The re-timed video signal is fed directly to two switches 4 and 5, switch 4 of which allows channel A to pass to an output terminal 6, and switch 5 of which allows channel B to pass to an output terminal 7 via respective output power stages 8 which also ensure that the output signals are correctly timed in accordance with the master sync pulse generator. Thus sync. blanking, clamp and colour burst pulses are inserted at this point.

The received video signal is also fed directly to a digital store 9, via an analogue-to-digital converter 10, the latter being necessary as the video signal is received in analogue form. The store 9 is a random access memory (RAM) having read and write facilities, and a capacity of about 1.5 Mbits, so that the store can accommodate an entire video field with some spare capacity. The output of the store is fed via a digital-to-analogue converter 11 to the two switches 4 and 5. The timing and operation of the store 9, the converters 10 and 11, and the two switches 4 and 5 are controlled by an address control logic 12, which receives line and field tuning pulses from the master sync pulse generator 3 via lead 13.

A colour signal detector 14, also receives the output of the time base corrector 2, and its function is to detect whether the colour video field (channel A) is being received, or the monochrome video field (channel B), and to inform the address control logic 12 accordingly, so that the operation of the store 9 is correctly controlled.

The operation of the video signal processing circuit is as follows. The interleaved sequence of colour video fields and monochrome video fields, which originate from two separate remote sources, are fed to the colour detector 14 which detects which field is currently being received. Assuming it is a colour field of channel A, then the address control logic 12 renders the switch 4 conductive so that the colour field is made available at output terminal 6. Simultaneously, the colour field is entered into the store 9. Clearly it takes a whole field period to enter it into the store, and as soon as it is begun to be written into the store, the previous contents of the store 9 are read out. The previous contents related to the monochrome field, and this is routed via the switch 5 to the output terminal 7.

The next video field received at terminal 1 is a monochrome field, assuming that the colour and monochrome fields occur alternately, and its nature is detected by the colour detector 14. It is routed directly, to the output terminal 7 via the switch 5, and is also written into the store 9, asthe previous colour field is read out and passed via the switch 4 to the output terminal 6. Thus a continuous sequence of colour video fields is made available at terminal 6 at the correct rate, to enable a proper video picture to be presented on a monitor.

However, in the sequence, each video field is repeated once, i.e. two consecutive fields are identical, but in practice, this causes very little degradation of the displayed video picture.

A similar sequence of events occurs for the monochrome video signal made available at output terminal 7.

The organisation of the store 9 which permits the simultaneous writing and reading of a video field is explained with reference to figures 2a and 2b. The solid line 20 represents diagrammatically the total capacity of the store 9. In practice, of course, the store 9 will consist of many separate memory devices which are appropriately interconnected with the address control logic 12. The capacity of the store occupied by a video field is represented by the shaded area. Assuming that the store is initially empty, the first video field is entered into the store to occupy the shaded region 21 of Figure 2a.

As it is then read out of the store, starting at the top 22, the next video field commences and is read into the spare capacity 23 of the store. By the time this spare capacity, has been filled, the top 22 of the store is vacant, and the process thus proceeds so that the second video field occupies the shaded regions shown in Figure 2b. It will thus be appreciated that as successive video fields pass through the store, the notional location of the spare or excess capacity of the store moves through the store until it reaches the top, and then reverts to its initial position. The size of the spare capacity 23 needed will depend upon the actual configuration of the individual memories which constitute the store 23. Although in theory, a single video line capacity is sufficient, in practice it is more convenient to allow for three or four lines, but even so the spare capacity is very small as compared with the total capacity 20 of the store 9.

The two different channels A and B need not be interleaved alternately, but can occur in bursts of short sequences of one channel followed by the other channel, as the colour detector 14 responds to the channel which is actually received.

Claims

1. A video signal processing circuit including means for receiving a video signal comprising sequential video fields relating to two different video channels; means for routing each received video field to a common store in turn in the order in which video fields are received, and for directly routing the video fields relating to particular channels to respective output ports; means for reading out from the common store a stored video field relating to one of said channels when a video field relating to the other channel is received, and for routing the stored video field to its respective output port, so that the two output video signals each consist of a regular stream of video fields some of which repeat.

2. A circuit as claimed in claim 1 and wherein the common store has a capacity which is in excess of one video field by an amount which is small compared with a video field, and is arranged such that the commencement of a video field is read into the excess capacity whilst a preceding video field is read out.

3. A circuit as claimed in claim 1 or 2 and wherein a channel detector is provided to determine which of the two video channels is currently being received.

4. A video signal processing circuit substantially as illustrated in and described with reference to the accompanying drawings.

5. A video signal processing circuit including means for receiving a video signal comprising sequential video fields relating to two different video channels; means for routing received video fields to a common store, and for directly routing the video fields relating to particular channels to respective output ports; means for reading out from the common store a stored video field relating to one of said channels when a video field relating to the other channel is received, and for routing the stored video field to its respective output port, so that the two output video signals each consist of a regular stream of video fields some of which repeat.