GB2140617A - Methods of forming a field effect transistor - Google Patents

Methods of forming a field effect transistor Download PDF

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GB2140617A
GB2140617A GB08402263A GB8402263A GB2140617A GB 2140617 A GB2140617 A GB 2140617A GB 08402263 A GB08402263 A GB 08402263A GB 8402263 A GB8402263 A GB 8402263A GB 2140617 A GB2140617 A GB 2140617A
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layer
source
forming
semiconductor
gate electrode
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GB8402263D0 (en
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Wolfgang M Feist
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Raytheon Co
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Raytheon Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H01L29/6678—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates on sapphire substrates, e.g. SOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8086—Thin film JFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8126—Thin film MESFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A method of forming a FET includes the step of forming an elongate buried region 30 below, and spaced from, the gate electrode 44. The buried region is electrically connected to the gate electrode 44 where it breaks through to the electrode at the edges of a mesa layer. The method includes the step of forming a pair of masking strips 14, 16 of insulating material on the surface of the semiconductor. An ion implantation masking layer is formed between the pair of masking strips to enable the selective implantation of particles in the semiconductor to establish the source and drain regions 22, 24. With such method a single masking step is used to define the source, drain and gate regions of the device, namely the masking to define the strips 14 and 16. The buried layer is formed by deep ion implantation with the source and drain masked or without masking so that there is shallow implantation under the strips 14, 16 and deep implantation elsewhere. Gate oxide may be deposited between the strips before implantation. The device may be formed in a semiconducting mesa on a sapphire or similar substrate. <IMAGE>

Description

SPECIFICATION Methods of Forming a Field Effect Transistor This invention relates to methods of forming a field effect transistor.
As is known in the art, metal gate and junction gate field effect transistors, sometimes referred to as MESFET and JFET devices, have been formed on high resistivity silicon, gallium arsenide, or silicon on sapphire substrates. In order to achieve efficient operation at microwave frequencies in excess of 1GHz the gate length should be 1 micrometer or less, the gate capacitance should be small, the depth of the conducting channel should be substantially smaller than the length of tine gate in order to avoid increasing the effective conductive channel length of the device because of fringing fields, the conductive channel doping should be relative high, (e.g. N=10'7 atoms/cm3), the carrier mobility in the conductive channel region should be high to achieve a low onresistance of the device, the source-drain spacing should be small (e.g. less or equal to 3 micrometers), the contact impedance should be small, and the gate leakage current should be small in order to avoid excessive loading of a drive circuit.
While the requirement of a very shallow conductive channel depth of 0.2 to 0.3 micrometers may be met using gallium arsenide material by forming an appropriately doped, shallow epitaxial layer on an insulating gallium arsenide substrate, and using silicon by an epitaxial or ion implanted layer on a highly resistive single crystal silicon substrate, meeting such shallow channel depth requirement is difficult where the epitaxial layer is of one material, such as silicon, and the substrate is of a different material such as sa#pphire. That is, complications arise in forming very shallow conductive channel depths for MESFET or JFET devices using silicon on sapphire substrates because of the fact that the electrical properties of the silicon film on the sapphire substrate are generally poor at and near the silico9-sapphire interface.Consequently, while silicon on sapphire devices are theoretically highly desirable since they have greatly reduced parasitic capacitances and readily lend themselves to the fabrication of microwave monolithic integrated circuits, when such devices utilize the full thickness of the silicon the minimum thickness of the silicon, and hence the minimum thickness of the channel depth, is typically 6000 A and therefore the depth of such conductive channel is only slightly shorter than the gate length. However, if the conductive channel depth is only slightly shorter than the gate length fringing fields spread, increase the effective gate length of the device, and thereby reduce the operating frequency bandwidth of the device.
As is already known in the art, devices of the type described above are generally made by positioning a gate, 1 micrometer or less in width, with a very high degree of masking accuracy precisely between the source and drain regions, which are typically spaced 3 micrometers apart.
This is a particularly difficult task, especially if the device is shaped so that registration in two dimensions must be achieved, e.g. in an interdigitated structure. Such technique is usually a so-called "lift-off" technique where a layer of photoresist is deposited on the surface of the semiconductor and patterned to expose the gate of the semiconductor region. Metal is then deposited over the photoresist and onto the exposed gate region. The photoresist with metal on its surface is then lifted off to leave the metal gate on the semiconductor. Such technique may be useful in some applications.However in those applications where it is desired to form a Schottky contact using a platinum deposition and a high temperature process to form plantinum-silicide prior to deposition of an aluminium metal gate contact, the photoresist is not generally capable of withstanding such high temperature process thereby limiting the use of this "lift-off" technique.
The present invention is defined by the claims hereinafter.
In a preferred embodiment of the invention the semi-conductor body is disposed on an insulating substrate, preferably a semiconductor of silicon on a sapphire substrate. A region in the semiconductor disposed between the gate and the buried doped region provides the conductive channel for the device. The buried doped region may be formed by implanting particles deeply through the surface of the semiconductor. During subsequent heat treatment the separation between the portion of the surface of the semiconductor body disposed over the conductive channel and the buried doped region is controlled to provide the desired, very small conductive channel depth. With such an arrangement a shallow conductive channel in a silicon on sapphire device has the conductive channel spaced from the silicon-sapphire interface so as to obtain increased operating bandwidth.
In the preferred practice of the invention, two spaced, masking members, preferably thick insulating strips, are formed on the surface of the semiconductor. A mask is deposited between the spaced insulating strips. Particles are introduced into unmasked surface portions of the semiconductor to provide the source and drain regions. The mask is then removed and a complementary mask is then formed to cover the previously unmasked portions of the semiconductor surface and to expose the region of the-semiconductor surface between the insulating strips.This complementary mask provides an ion implantation mask and particles capable of establishing a conductivity type opposite to the conductivity type of the semiconductor are ion implanted through the exposed portion of the semiconductor into the underlying semiconductor to form the buried doped region of such particles spaced from the exposed portion of the semiconductor surface. An additional mask is then formed between a portion of the pair of strips and over a central portion of the semiconductor. Particles capable of establishing the opposite type conductivity of the semiconductor are ion implanted into exposed surface portions of the semiconductor to provide a conductive region along the exposed surface portions of the semiconductor and into exposed portions of the buried doped region.Source and drain electrodes are provided for the source- and drain regions. A gate electrode is provided having a first portion thereof disposed on the surface of the semiconductor between the insulating strips, a second adjacent portion thereof disposed on the surface of the insulating strips and a third portion thereof electrically connected to the buried doped region through the conductive region formed along surface portions of the semiconductor.
With such arrangement the gate electrode capacitance is kept to a minimum since the portion of the gate electrode extending beyond the gate region is deposited on the thick insulating strips adjacent to the gate area. In addition, alignments of the gate region with respect to the source and drain regions is facilitated since these regions are defined simultaneously by a single mask made up of the spaced masking strips and which-allows one level of masking in forming the source, drain and gate regions of the device.
Further, the use of a pair of spaced, thick masking strips enables the fabrication of a selfaligned gate MOS structure where, after forming the thick masking surfaces with vertical-walls and before or after implanting source and drain contact regions, a thin gate oxide layer is grown over the gate area between the spaced masking strips. Particles are then implanted at energy levels which place them in a shallow region directly under the thick masking surfaces but at a much greater depths in other regions of the semiconductor, including the gate region.
Therefore the doping characteristics of the gate region of the semiconductor are-retained. The gate electrode is then formed on the thin oxide layer formed in the region between the spaced masking strips and the source and drain regions are electrically connected to the gate region by the portions of the ion implanted region which were implanted at a shallow depth in the semiconductor beneath the thick masking surfaces.
The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figs. 1 A to 6A are plan views of a field effect device at various steps in the manufacture thereof; Figs. 1 B to 6B are cross-sectional elevation views of the field effect device at various steps in the manufacture thereof, such cross-sectional elevation views being taken along the lines 1 B1 B to 6B-6B respectively in Figs. 1 A to- 6A; Figs. 3C to 6C are cross-sectional elevation views of the field effect device at various steps in the manufacture thereof, such cross-sectional elevation views being taken along the lines 3B3B to 6B-6B respectively in Figs. 3A to 6A; and Figs. 7A to 7F are sectional views of a MOSFET device at various stages in the manufacture thereof.
Referring now to Figs. 1 A and 1 B, a single crystal insulating substrate 10 of sapphire, having thereon a single crystal semiconductor film 12 of silicon, is shown. The silicon film is an initially undoped epitaxial layer of silicon having a thickness of 0.5 to 1.5 micrometers. The silicon film 12 is next implanted with phosphorus (having a dose range of N=2 to 8x 1012 atoms per cm2) through a thin, 800 A thick, thermally grown silicon dioxide layer, not shown. The implant damage is then annealed out by heating the substrate in argon, for approximately twenty minutes at 10000 C, and at the same time the phosphorus deposit is driven deeper into the silicon film to form an N type conductivity epitaxial layer or film of silicon.The 800A thick silicon dioxide layer, not shown, is then photolithographically etched to serve as a mask for forming a mesa structure of silicon in a conventional manner, shown as the silicon layer 12 in Figs. 1A and 1B.
Next, the 800 A thick silicon dioxide layer is removed and the exposed surfaces of the mesashaped silicon layer 12 are oxidized in steam at 8500C to form a new 800 A thick insulating layer of silicon dioxide. Thereafter a 1 micrometer to 1.5 micrometer thick layer of silicon dioxide is chemically vapour deposited at 4500C over the entire structure, the combined silicon dioxide layers being shown in Fig 1 B as layer 13. A photoresist mask 15, is then applied to the surface of this thick silicon dioxide layer 1 3 and patterned to protect a pair of strip shaped surface portions of the deposited silicon dioxide layer 1 3.
Then this silicon dioxide layer 13 is etched into silicon dioxide strips 14, 16 having a separation of 0.7 to 1.0 micrometers, a height H of 1 to 1.6 micrometers, and each one having a width W of 1.0 to 1.5 micrometers across the mesa structure and portions of the sapphire substrate 10 as shown in Figs. 2A and 2B, using reactive ion etching in a CHF3 atmosphere. When done in a parallel plate ion etching system the silicon dioxide layer 1 3 is formed into silicon dioxide strips 14, 15 having substantially vertical walls without undercutting the photoresist mask.
Because of the vertical etching the relatively small dimensions of the photoresist mask 1 5 are accurately transferred onto the silicon dioxide layer 13. As will be described hereinafter the pair of silicon dioxide strips 14, 16 are used to provide a pair of masking surfaces during formation of the source region, the drain region, and the gate region, the region 18 disposed between the strips 14, 16 providing a gate window. It is noted that the relative positions of the source, drain and gate regions are defined to a very high degree of accuracy by a single- mask, here of photoresist layer 15.
Referring to Figs. 3A, 3B, 3C, the region 18 (Fig. 2B) is next covered by a relatively noncritical photoresist mask 20 using conventional techniques. the source and drain regions 22, 24 are formed in the upper exposed surface portions of the silicon film 12, as shown in Fig. 38, by ion implanting arsenic or phosphorus with a dose of N""Sx 1014 atoms per cm2 to form N+ type conductivity regions 22, 24.
Referring now to Figs. 4A, 4B and 4C, the photoresist' layer#20 is removed and a photoresist mask 26, complementary to photoresist mask 20 (Fig. 3A) is formed over the structure as shown and is used to provide an ion implantation mask to cover the source and drain regions 22, 24. Boron ions are implanted into the portion of the silicon film exposed by the photoresist mask 26, i.e. into the portion exposed by window 28 to form a buried region 30. The photoresist mask 26 thereby provides a cover or mask to shield such source and drain regions 22, 24 against the deep boron implant. The buried region 30 is thus formed in the silicon film 12 beneath the portion of the surface of such silicon film disposed between strips 14, 1 6 and exposed by a window 28 formed in mask 26.It is noted that the buried region 30 is buried beneath the exposed surface of the silicon film 12 and is separated from such surface a depth D, here~5000 A. The boron is implanted into the exposed portion of the silicon film 12 with a dosage of N""'5x 1013 atoms per cm2 at an implantation energy level of 180 KeV. It is also noted that portions 30a of such regions are actually implanted into the sapphire substrate, as indicated, because the silicon film is thinner at the side peripheral portions than in the central, upper portions.
Referring now to Figs. SA, SB and 5C, a photoresist mask 32 is formed over the central surface portion of the silicon mesa, as shown with, the photoresist layer 26 remaining on the structure as shown. That is, the mask 32 covers a portion of the window 28 Figs. 4A, 4B in mask 26 to expose separated upper and lower portions 28a, 28b of the surface of the silicon film 12, as shown in Fig. 5A. The masks 26, 32 together provide an ion implantation mask.In particular, boron is implanted into upper surface portions of the exposed upper and lower portions 28a, 28b of the silicon film to provide conductive regions 38 which extend over portions of the upper surface and side surface of the silicon film 12 and onto electrical connecting peripheral portions of the buried region 30 as shown in Fig. SC.
Any implant damage resulting is then annealed again by heating the structure in argon at 10000 C. During this heating step the implanted boron is activated to form a p-type conductivity region. The p-type doped regions diffuse into the silicon film 12 and, in particular, the portion of the p-type doped region buried beneath the silicon surface, i.e. region 30, diffuses towards the upper outer surface of the silicon film 12.The heating is terminated when the depth of the junction between buried region 30 and the silicon film 12 has moved to a depth D', equal to the desired conductive channel depth, here 2000 to 3000 A below such outer surface as shown in Fig. 6B. It is noted that the channel depth D', here 2000 to 3000 A is much smaller than the gate length, here 7000 to 10,000 A with the conductive channel region 31 being disposed between the upper surface of the silicon film 12. It is further noted that the buried region 30 is spaced from the silicon film 12~sapphire substrate 10 interface and hence such conductive channel region 31 is in the portion of the silicon film 12 having good electrical characteristics.
Referring now to Figs. 6A, 63 and 6C, source and drain electrodes 40, 41 are formed in ohmic contact with the source and drain regions 22, 24, respectively, using conventional techniques. A gate electrode 44 is formed with a Schottky contact to the portion of the surface of the silicon film disposed between silicon dioxide strips 14, 16, as shown. It is noted that such gate electrode 44 is in ohmic contact with the p-type doped regions 38 and hence is electrically connected to the buried p-type buried doped region 30 as shown-in Fig. 6C.
Here the gate electrode 44 is formed by first depositing a layer of platinum, not shown, heating such platinum to form platinum silicide in gate region, removing the remaining portions of the platinum layer and then depositing a titaniumtungsten layer followed by an aluminium layer, all in accordance with well known practice to form a Schottky barrier contact.
Because of the use of a pair of relatively thick masking surfaces, i.e. because of the use of insulating silicon dioxide strips 14, 1 6 (Fig. 2B), it has been found that it is possible to confine the gate metallization entirely to the narrow gate region even through the photoresist mask for the gate metal may be somewhat wider than the gate length. This is accomplished by using photoresist of relatively low viscosity. When this is spun on at sufficient speed, the photoresist layer is correspondingly thin.Because of the vertical and deep silicon dioxide strips 14, 1 6 adjacent to the gate region, photoresist is drained into the narrow space between the strips 14, 1 6 forming a thicker coating over the gate, and a very thin or discontinuous coating on the surface of the thick silicon dioxide strips. When the metal is etched, the thin portion of the photoresist coating offers little protection, and thus the metal overlap on the surface of the strips is automatically removed but the metal between the strips is additionally protected by the drained photoresist.
Instead of platinum silicide, other methods can be used to form Schottky barriers. One consists of simple depositing aluminium, silicon doped aluminium, Ti-W-Al, or CrAu onto the bare silicon in the gate region. A more reliable Schottky contact offering a reduced leakage current can be made by first forming a very thin oxide layer,20~60 A thick, on the silicon before deposition of the metal. This thin oxide layer can be formed conveniently in an oxygen plasma, or by thermal oxidation (e.g. in steam at 5006000C). In another variation of gate formation a very shallow p-n junction may be formed instead of a Schottky barrier to provide a JFET device.
The device described in this disclosure is also suitable for enhancement type MESFET's or JFET's. To this end, the depth of the channel region is made sufficiently shallow, and the doping of the active channel region is made sufficiently light so that the channel is depleted at zero applied gate voltage on account of the contact potential between the gate and the n-type channel. With the buried region present, the depletion of the channel region is very efficient since it occurs from two sides.
The fabrication method and structure described in this disclosure can be employed to fabricate self-aligned gate MOS structures.
Referring to Fig. 7A a p-type conductivity silicon film 1 2' is shown formed as a mesa type structure on a sapphire substrate 10' as shown using processing techniques described above in connection with Figs. 1 A and 1 B. A layer of silicon dioxide 13' is formed over the surface of the structure as shown. A mask is formed of a layer 15' of photoresist as shown in Fig. 7A. A suitable etchant is then brought into contact with the portions of the silicon dioxide layer 13' exposed by the photoresist layer 15' to form a pair of silicon dioxide strips 14', 16' as shown in Fig. 7B.
Here such etchant is the reactive ion etching process described above in connection with Figs.
2A and 2B. As noted above the mask provided by the photoresist layer 15' defines the source, drain and gate regions of the device. Next, a layer 20' of photoresist is disposed in the region between the pair of strips 14', 1 6' as shown in Fig. 7C.
Phosphorus or arsenic ions are then implanted to form the n-type conductivity source and drain regions 22', 24' of the device as shown in Fig. 7C A gate oxide, here a layer 50 of silicon dioxide, is grown over the surface and then removed except from the portion of the surface over the gate region to provide the structure shown in Fig. 7D.
Phosphorus ions 52 are then ion implanted at an energy which puts them into shallow regions 54 of the silicon film 12' located directly under the thick silicon dioxide strips 14', 1 8' as shown in Fig. 7E. In contrast, since the gate region is covered only by a thin silicon dioxide layer 50, the implant will go deep into the gate region and beneath the source and drain regions 22', 24' as shown. Therefore, the p-type conductivity of the silicon 12' is retained in a region under the gate oxide and it will determine the threshold of the MOSFET. The source, drain and gate electrodes are applied in any conventional manner as shown in Fig. 7F. Having described preferred embodiments of this invention, it is now evident that other embodiments incorporating these concepts may be used. For example, while the devices described herein are silicon on sapphire devices, a fieíd effect device formed with a buried doped region may be formed on devices made of other materials such as gallium arsenide epitaxial layers formed on semi-insulating gallium arsenide substrates. Further, while the insulating strips are here shown as silicon dioxide strips, they may be formed of insulating polycrystalline silicon material.
Matter described herein is described and claimed in copending application No. 8102529, from which the present application is divided, and in copending application No. 8326563.

Claims (3)

1. A method of forming a field effect transistor having a layer of semiconductor material disposed on a surface of a substrate of insulating material with source and drain regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over a portion of such upper surface of the semiconductor layer between the source and drain regions comprising the steps of forming a doped region buried within a portion of the semiconductor layer disposed beneath, and spaced from, the gate electrode.
2. A method of forming a field effect transistor having a layer of semiconductor material with source and drain regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over such upper surface of the semiconductor layer between the source and drain regions comprising the steps of: a) forming a doped region buried within a portion of the semiconductor layer disposed beneath, and spaced from, the gate electrode; and b) electrically connecting the buried doped region and the gate electrode forming a conductive channel in the portion of the semiconductor between the portion of the upper surface of the sem-iconductor layer between the source and drain regions and the buried doped layer.
3. A method of making a field effect transistor substantially as hereinbefore described with reference to and as illustrated in Figs. 1 A to 6C of the accompanying drawings
3. A method of making a field effect transistor substantially as hereinbefore decribed with reference to and as illustrated in Figs. 1 A to 6C or Figs. 7 to 7F of the accompanying drawings.
New Claims or Amendments to Claims Filed on 3 August 1984 Superseded claims 1 to 3 New or Amended Claims:~
1. A method of forming a field effect transistor having a layer of semiconductor material disposed on a surface of a substrate of insulating material with source and drain regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over a portion of such upper surface of the semiconductor layer between the source and drain regions comprising the steps of forming a doped region buried within a portion of the semiconductor layer disposed beneath, and spaced from, the gate electrode, and connecting the gate electrode to the buried doped region.
2. A method of forming a field effect transistor having a layer of semiconductor material with source and drain regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over such upper surface of the semiconductor layer between the source and drain regions, the layer of semiconductor material being disposed on a surface of a substrate of insulating material, comprising the steps of: a.)-forming a doped region buried within a porti~n'of t'he semiconductor layer disposed beneath, and spaced from, the gate electrode; and b) electrically connecting the buried doped region and the gate electrode forming a conductive channel in the portion of the semiconductor between the portion of the upper surface of the semiconductor layer between the source and drain regions and the buried doped region.
GB08402263A 1980-03-03 1984-01-27 Methods of forming a field effect transistor Expired GB2140617B (en)

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GB08402263A GB2140617B (en) 1980-03-03 1984-01-27 Methods of forming a field effect transistor

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Application Number Priority Date Filing Date Title
US12678780A 1980-03-03 1980-03-03
GB08402263A GB2140617B (en) 1980-03-03 1984-01-27 Methods of forming a field effect transistor

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GB8402263D0 GB8402263D0 (en) 1984-02-29
GB2140617A true GB2140617A (en) 1984-11-28
GB2140617B GB2140617B (en) 1985-06-19

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GB08402263A Expired GB2140617B (en) 1980-03-03 1984-01-27 Methods of forming a field effect transistor

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238857A (en) * 1989-05-20 1993-08-24 Fujitsu Limited Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure
US5294555A (en) * 1982-04-13 1994-03-15 Seiko Epson Corporation Method of manufacturing thin film transistor and active matrix assembly including same
US5904508A (en) * 1994-09-27 1999-05-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1060731A (en) * 1962-10-15 1967-03-08 Rca Corp Semiconductor devices and methods of preparing them
GB1465244A (en) * 1974-04-19 1977-02-23 Rca Corp Deep depletion insulated gate field effect transistors
GB1507091A (en) * 1974-03-29 1978-04-12 Siemens Ag Schottky-gate field-effect transistors
GB2052155A (en) * 1979-06-29 1981-01-21 Philips Nv

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1060731A (en) * 1962-10-15 1967-03-08 Rca Corp Semiconductor devices and methods of preparing them
GB1507091A (en) * 1974-03-29 1978-04-12 Siemens Ag Schottky-gate field-effect transistors
GB1465244A (en) * 1974-04-19 1977-02-23 Rca Corp Deep depletion insulated gate field effect transistors
GB2052155A (en) * 1979-06-29 1981-01-21 Philips Nv

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294555A (en) * 1982-04-13 1994-03-15 Seiko Epson Corporation Method of manufacturing thin film transistor and active matrix assembly including same
US5238857A (en) * 1989-05-20 1993-08-24 Fujitsu Limited Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure
US5904508A (en) * 1994-09-27 1999-05-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same

Also Published As

Publication number Publication date
GB2140617B (en) 1985-06-19
GB8402263D0 (en) 1984-02-29

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