GB2136613A - Data recorder with non-volatile solid state memory - Google Patents

Abstract

An electricity billing recorder has a controller for processing pulses from an electric meter. The resulting data is temporarily stored in random access memory as data words representative of energy consumed in predetermined time ("demand") intervals. The accumulated measurement ("event") data and time data are transferred to a non-volatile, solid state memory module after relatively long collection periods comprising a number of demand intervals. The solid state memory is energized only during data transfers. The entire memory module is replaceable for processing at a central location. During replacement the controller writes a special Removal Record in predetermined locations on the memory module being removed, and prepares a special Insertion Record for the new module. The cumulative counts recorded on these special records in addition to the normal records establish reliable data continuity. After any collection period in which a power outage has occurred, the controller transfers the current data to a secondary portion of RAM. Subsequent demand intervals, until power is restored and including any memory thermal recovery periods, are assigned chronological index numbers and event data is stored only for those demand intervals in which power consumption actually occurs. After return to normal operation, the data in secondary RAM is transferred to the solid state memory and the compact format data in primary RAM is re-constructed into normal storage format with all intervals during which no event data was stored being zero filled. As this data is transferred to secondary RAM for storage in the solid state memory, the remaining data in primary RAM is re-located to provide as much space as possible for data storage should another power outage occur before conversion of all the compact format data. <IMAGE>

Description

1

SPECIFICATION

Data recorder with non-volatile solid state memory GB 2 136 613 A 1 The present invention relates to recording apparatus for recording measured event data along with a time 5 referenceforthe eventdata; and more particularlyto a recorderof thetype used by electrical utilitiesto record energy consumption by customers.

Billing or survey recorders are used by electrical utility companies for recording the event data provided by an electrical meterwhich indicates the amount of energy used by a consumer. The billing recorder accumu lo lates data for a period of time called a read or billing period, typically a month long, and it also stores time lo signals or "marks", generated bythe billing recorder. Atime mark is simply a signal recorded at a predeter mined interval (called "demand" period) during which the associated event data occurred. That is, the distance between time marks on the tape defines a predetermined time period, assuming the tape speed is constant and the same for both recording and playback. Demand periods conventionally are 5, 15, 30 or 60 minutes.

The event data and the time marks of conventional recorders aretypically recorded on magnetictape in a cartridge to allow processing or analysis of the data at a central translation center which is remote from the point of service. The recorded data provides time marks and event data pulses for cutomer billing and load analysis, but it does not provide data representative of a particular start time or the source (recorder) from which it came. Start and stop times, customer identification such as meter or recorder number (I.D.), and 20 beginning and end meter register readings are all recorded in writing by the exchange personnel, thereby leaving considerable room for human error. When such error does occur, any loss must be suffered by the utility, not the customer.

Most billing recorders in use today employ magnetic tape as the storage medium, even though magnetic tape hastemperature and humidity limitations which make it less reliable as a storage mediumthan is desired 25 in the demanding environment of use by a utility. The tape must be advanced pastthe record head continu ously and at a precise speed during recording. Accordingly, a complex mechanical tape drive system is required to ensure proper operation at all environmental specifications. The requirement of drive motors for advancing the tape adds considerable cost and limits miniaturization of the unit. Also, periodic servicing is required to maintain the recording mechanism drive elements, battery carryover system, and to periodically 30 clean the recording head.

It will be appreciated that such recorders are required to operate in a wide range of temperatures (typically -20' C to +65' C.), due to the worst cases of heat and cold they are likely to encounter over the large geographical area in which a given model is marketed.

A further consideration affecting cost, reliability and performance is, that billing recorders employed for 35 recording data representing electrical energy usage are occasionally subjected to power interruptions. In recent years, there has been a trend to employ power outage circuits which provide transfer to an auxiliary power source, such as a battery during intervals of primary power loss. It is evidentthat maintaining the drive tothetape advance motors during primary power loss results in a heavy drain on the battery,thereby limiting the carryovertime forwhich recording can be continued. This is particularly disadvantageous in cold climates. 40 According to one aspect of this invention there is provided a demand recorder comprising controller circuit means receiving data pulses representative of measured events and including random access memory means having primary and secondary storage locations, said controller circuit means being arranged to generate data words representative of received event data for predetermined demand intervals and to storethe same in said primary storage locations for a collection period comprising a predetermined number of said demand 45 intervals; and non-volatile, solid state memory means removably associated with said controller circuit means and adapted for remote processing; said controller circuit means being arranged to transfer said event data from said random access memory means atthe end of a collection period for more permanent storage in said solid state memory means, said controller circuit means being responsive to a power outage to inhibit data transfers from said random access memory means to said solid state memory means, and said controller 50 circuit means being arranged to transfer the data from said primary storage locations to said secondary storage locations at the end of the first collection period during which a power outage has occurred and thereafterto store incoming event data in said primary storage locations in a compacted format comprising an index data word representative of a demand interval and event data associated with that demand interval.

According to another aspect of this invention there is provided a method for recording event data in a 55 demand recorder comprising transmitting data pulsesto controller circuit means representative of measured events and including random access memory means having primary and secondary storage locations, generating data words representative of received event data for predetermined demand intervals and storing the same in said primary storage locations for a collection period comprising a predetermined number of said demand intervals, transferring said event data frorn said random access memory means at the end of a 60 collection period for more permanent storage in a non-volatile solid state memory, inhibiting data transfers from said random access memory means to said solid state memory during a power outage, transferring the data from said primary storage locations to said secondary storage locations at the end of the first collection period during which a power outage has occurred, andthereafter storing incoming event data in said primary storage location in a compacted format comprising an index data word representative of a demand interval 2 GB 2 136 613 A 2 and event data associated with that demand interval until said power outage has ended.

Abilling recorderin accordance with this inventionwill now bedescribed, bywayof example,with reference to the accompanying drawings, in which:Figure 1 is a functional block diagram of the billing recorder; Figure 2 is a block diagram of a magnetic bubble memory for the system shown in Figure 1 Figure 3 is a diagrammatic representation of a removable memory card used in the billing recorder; Figure4 is a blockcliagram of a system which permits readoutofthe memory data bywayof a communication link; Figure 5 is a diagrammatic front view of the recorder; 1() Figure 6 is a timing diagram illustrating power fail modes; Charts 1 and 11 are flow charts describing the overall system operation; Chartill is a flowchart describing the operation of the system during PowerFail Mode 11 for recording power outage data in the bubble memory; and Chart IV describes the operation of the system during Power Fail Recovery Mode 11 for storing data in Random Access Memory during a power outage.

Referringto Figure 1,thebiiiing recorder provided by the present invention records quantized measurement or "event" data provided by an electric utility meter which measures electrical energy consumption. Each pulse from the meter represents the consumption of a predetermined amount of energy or reactive power. At periodic billing intervals, typically a month, the event data recorded is processed at a translation canter for billing the customer orto provide load analysis data. The recorder may be a multichannel recorder; and in the 20 exemplary embodimentthe recorder is illustrated as a two-channel system which receives measurement data from two sources over separate data channels A and B. Briefly, the event data is fed to the recorder circuits overtwo data channels A and B (which may be separate sources ortwo different quantities from the same source), and stored in a non-volatile solid state memory 23, such as a magnetic bubble memory, under the control of a controller which includes a microprocessor 11. 25 Alternatively, the data from two sources may betotalized before preparation of the record to be stored, and then stored in a totalized format. The controller processesthe incoming data by accummulating itin predeter mined time intervals called "demand" intervals prior to storage in the bubble memory 23 and controls the writing of the processed data into the memory 23.

Referring to Figure 1 the microprocessor system 11 includes a central processing unit (CPU) 16, a read only 30 memory (ROM) 17, a random access memory (RAM) 18, a time reference generator 13, and an inputloutput 0/0) interface 19. The CPU 16, which may be a Type CDP1802 Microprocessor manufactured by RCA, Inc.

which uses CMOS circuits to conserve power, processes the event data pulses received from the inputloutput interface 19 via data bus 51 and stores the processed data in the RAM 18 for each demand interval over a complete collection period beforewriting itinthe magnetic bubble memory 23. The ROM 17 stores the control 35 instructions for the CPU 16.

The eventdata suppliedtothe recorder circuits is coupled overthe data channelsA, B, C and D (which are latches) in the form of pulses generated by conventional pulse initiator devices (not shown), one for each channel. The illustrated embodiment may accommodate one ortwo separate input channels, such as A and B, designated 19A and 1913, atthe option of the customer. In addition, if desired, additional channels 19C and 19D 40 may be provided for and totalized respectively with 19A and 1913. The initiators may be of the type sold by Samgamo Weston, Inc., under the designation SPI. Each level change atthe output of the initiator represents the consumption of a predetermined quantity of electrical energy. Thistrain of pulses is fed to the controllervia inputloutput circuit 19.

The incoming data is processed by the micro-processor which accumulates the quantized data in predeter- 45 mined demand intervals and provides temporary storage in the RAM 18 for a fixed number of demand intervals (it could be any number, one or more) which comprise a collection period. During this time, the microprocessor preparesthe event data andtime reference and other information, which will be described, in a format for recording; and the bubble memory is not energized. The bubble memory is energized only as necessary for writing data at the end of a collection period. Such write times are referred to as access times. 50 The controller includes a digital clocklcalendar which provides time reference information for defining the demand intervals in real time. The controller stores date andtime information representative of the beginning of a collection period. For the two-channel recorder illustrated, the microprocessor accumulates the pulses transmitted over each data channel for demand intervals of fifteen minutes duration for a collection period of four hours; and generates data words representing the number of pulses accumulated for each channel for 55 each of the sixteen demand intervals of a collection period.

For a "normal" collection period (i.e. one in which there is no power outage or no insertion or removal of a memory module), these data words are formlatted together with time reference data (month, day and hour) and a running total count. The normal record data istransferred fromthe RAM 18tothe bubble memory atthe end of each collection period during the access time.

To conserve storage space in the bubble memory, time reference data is not stored for identifying each demand interval; rather, the event data is formlatted by the microprocessor such that the event data for successive demand intervals is assigned to and stored in predetermined memory locations. If additional memory space is available, of course, or if it is otherwise found to be desirable, additional time reference data maybe stored for each normal record. Twelve bits of memory (4095 resolution) are allocated for each demand 1 t 3 GB 2 136 613 A 3 interval per channel. This is one and one-half bytes. In the case of a two-channel recorder, the event data for one demand interval for Channel B is followed by the event data forthe same demand interval for Channel A.

In addition to the normal record data described above, the microprocessor prepares a separate Removal Record for storage in predetermined locations of the bubble memory when it receives an indication from the exchange personnel that a memory module is being replaced. Further, after an erased memory module is inserted, the microprocessor prepares a special Insertion Record which is recorded at the beginning of the newly inserted bubble memory. Both of these records will be explained in further detail below.

The bubble memory 23 of this exemplary embodiment is capable of storing data accumulated over a period of approximately thirty-five days (i.e. 213 4-hour collection periods). The bubble memory module is mounted on a removable card, represented bythe dashed line 24, in Figure 1,to facilitate replacement of the "recorded"10 memory module with an erased (zeroed) memory module atthe end of each billing period. After removal, the recorded memory is transported to a translation centre where the data is translated. The memory is then preferably erased for reuse, althoughthis is not absolutely necessary sincethe microprocessor could have an erase subroutine before writing.

Referring to Figure 3, the memory card or module 24 contains the bubble memory itself, designated 23, a 15 Read Only Memory 45 which contains the information identifying usable minor loops, a memory readout circuit 46 which may include a sense amplifier, and a temperature- compensating write resistor. The card includes printed circuit conductors which providethe necessary interconnections betweenthe elements of the bubble memoryeard and terminals 24a of an edge connector 24b which is insertable into a respectacle 24c (see Figure 5) on the front of the billing recorder unit.

A device generally deignated 49 is used to signal the microprocessor that the recorded memory module is going to be removed and an erased module inserted. This definesthe end of a collection period. Preferablythe device 49 requires some action bythe operatorto be accomplished a shorttime before actual removal. This delay may be as short as 100 milliseconds, and the purpose is to give the microprocessor sufficient time to prepare the Removal Record and transfer it to the memory module before actual removal. In the form 25 illustrated, the device 49 includes a handle 49Awhich is rotatable between a locking position shown in solid line which prevents removal of the module 24, and a removal position shown in dashed line which permits removal of the module. The handle 49A is mounted on a shaft 49B which contains a cam 49C. In the locking position, the cam 49C engages a first contact49E and may provide a ground forthat contact. When the handle 49A is moved to the removal position,the microprocessor preparesthe Removal Record andtransfers itto the 30 memory module 23. When the new module is inserted andthe handle 49A is moved to the locking position, the microprocessor senses this signal and prepares an Insertion Record and transfers that record to a predeter mined location in the newly inserted memory (preferably, the first four pages thereof, as will be described).

Devices other than the locking handle 49A could equally well be employed, for example, a cover or lid pivotally mounted to the face of the recorder unitwhich would be requiredto be opened before removal of the 35 module could also be used. It is not necessary that it be directly associated with and lockthe module in place, but it is believed that such a device would minimize error on the part of the replacement personnel, which could cause loss of data.

Tofurther minimize error,the memory module is providedwith a visual indicatorsuch asthatshown at47 in Figure 3 for indicating whether or not a particular memory module is recorded or erased. Such devices are 40 commercially available and may comprise a magnetic bi-stable element which, if magnetized in one polarity will exhibit a first color and, if magnetized in the opposite polarity will generate a second, easily distinguish able color. This may be accomplished by transmitting the write current in one direction in a loop or coil associated with the indicator 47 to generate the first color during insertion, and be transmitting the erase current through the coil in the opposite direction, thereby generating the second color, upon erasing.

Alternatively, a mechanical indicator responsiveto being inserted in the recorderto give one visual indication (of recorded date) and responsive to being inserted in the reader to give a second visual indication of being erased, may be used. The Removal Record which is recorded just prior to the time the recorded memory module is removed and after operator actuation of the device 49, includestime reference data representing the month, day, hourand minute of module removal as well as partial period event data. The event data is stored in 50 particular memory locations as defined by a predetermined memory map, which are preassigned to the respective demand intervals. Those locations associated with demand intervals for a partial collection period after removal are filled with zeros (that is, no event measurement data is inserted). The partial collection period event data is stored temporarily in RAM 18 and transferred just prior to removal of the memory module as indicated. The Removal Record also includes an identifier code which identifies a customer or customers by 55 correlating the memory modulewith a particular billing recorderfrom which the memory has been removed. Total pulse counts for the two channels A and B are also recorded as part of the Removal Record.

The Insertion Record is recorded at the end of the partial collection period following insertion of an erased memory module. This record includes time information, month, day, hour and minute of module insertion, and a five digit BCD identifier code. In addition, time data representing the month, day and hour defining the 60 current collection period is recorded as part of the Insertion Record along with any event data stored in RAM 18 atthe end of the collection period. The event data is stored in particular memory locations associated with the respective demand intervals; those memory locations associated with demand intervals for the collection period prior to insertion are filled with zeros.

The recorder circuits normally obtain power from an AC line source, but include battery carryover to 65 4 GB 2 136 613 A 4 maintain selected circuits energized in the event of an AC power outage. A power supply circuit 14 provides the required DC levels forthe microprocessor system 11 via a power bus 50. ADC to DC converter 28 is energized by the AC line power or, if that is not present, the battery, via solid state switch 29 under control of the CPU 16 which continuously senses forthe presence of the 60 Hz. line signal for determining whether a power outage or failure is present. The converter provides the required DC levels for the bubble memory and its associated drive circuitry, which comprise the magnetic bubble memory system 12. By means of the switch 29, the microprocessor de-energizesthe bubble memory system during collection periods and selectively energizes it only for data transfers at access times atthe end of normal collection periods or at removal/insertion times.

In the casewherethe operating temperature specifications ofthe bubble memory meet or exceed those for the entire recording system, the solid state switch 29 may be energized bythe CPU 16 atthe end of every data collection period for writing whatever data might have been accumulated during that period, without depleting the battery substantially since ittakes less than about 100 milliseconds to write all of the data for a complete collection period. However, where the temperatures specifications for the bubble memory do not meet the overall operating temperature specifications forthe recorder system, particularly wherethe recorder system is required to operate at a temperature below the manufacturer's specification for the bubble memory, the 15 presentsystem does not permitthe writing of any data intothe bubble memory (duetothe possibility that data might be lost or errors might occur if the temperature of the bubble memory has in fact fallen below its operating specification), and the CPU 16 further initiates a thermal recovery period which may be 45 minutes upon the return of AC line power by sensing a 60 Hz. signal on the line 30. As will be described more fully below, a special power recovery orpowerfailure mode is implemented bytheCPU and such a system will have 20 additional Random Access Memory 18 in which to store eventdata betweenthe occurrence of a poweroutage and the termination of a thermal recovery period in a manner that will optimize the use of the additional memory, as will be understood from subsequent description.

Time reference data is generated under program control by the microprocessor in units of minutes, hours, days, months, day of the week and year. The time base generator 13 includes a 60 Hz. signal received directly from the power line by the CPU. A crystal oscillator 32 and digital countdown circuit 31 provide an auxiliary timing signal inputto the CPU in the event of loss of primary AC power. The latter signal has a frequency of approximately 61 Hz.

The CPU 16 counts the pulses transmitted over each data channel A and B separately for the demand intervals. During each demand interval, the number of pulses received from each channel is encoded into a 30 twelve bit binary word (one and one half bytes) representative of the total count, and this word is stored in the RAM 18. Atthe end of each full collection period, the sixteen data words (fora four-hour collection period and minute demand interval) for each channel together with a] 1 other data comprising a complete record, as will be described, are transferred via data bus 51 from the RAM 18 to the bubble memory 23, under the control of the CPU 16. 35 The magnetic bubble memory system 12 includes a memory control circuit 21, a drive circuit 22 and the bubble memory module 23. The bubble memory system is commercially available, and accordingly its structure and operation are not described in detail. Bubble memory systems are available from Texas Instruments, Inc., Dallas, Texas; and they are described in a publication by the same company entitled "Magnetic Bubble Memories and System Interface Circuits", 1977 which is incorporated herein by reference. 40 The drive circuit 22 includes a function driver 43 and coil driver 44. A memory controller 41 responds to commands from the microprocessor system 11 and enables the necessary control functions to a function timing generator 42 to access a page (or pages) of the memory 23.

Fora write operation,the CPU 16 supplies an addresstothe controllervia an address bus, andwritesthe data into an input buffer41 a ofthe memory controller41. The memory controller41 accessesthe properpage and 45 effectswriting ofthe data intothe memory. Fora read operationthe CPU 16 generates an addressto selectthe module locations, loads the controller 41 with the proper page number and generates a read command. The memory controller accesses the designated page and stores the data in its buffer 41 a. The memory controller 41 also synchronizes the operation of the memory control circuits and the operation of the bubble memory module.

The function timing generator 42 provides input timing control to a function driver 43, a coil driver 44 and a readout circuit 46 on a per cycle basis. The function timing generator, under the control of the memory controller41, generates five functions, including generate, replicate, annihilate, transfer in, and transferoutfor the two function drivers. The function timing generator also provides control signals to the coil drivers to maintain the proper phase relationship between the coils in each of the memory modules.

The function driver 43 converts logic level signals from the function timing generator into an analog form usable by the memory module 23. The coil drivers 44 respond to outputs of the function timing generator 42, and generate the proper current waveforms for driving the bubble memory devices.

GB 2 136 613 A 5 The bubble memory module for the two channel system comprises a Texas Instruments Type TBM0103 bubble memory modulewhich provides641 pages on non-volatile, solid state memory having 18 bytes of data per pagewith 8 bits perbyte. The assignment of the bubble memorystore locations is illustrated in Tables 1, 11 and 111which show, respectively, memory assignmentsfor pages 14(lnsertion Record); pages 5-7 (comprising one Normal Record), and pages 638-641 (Removal Record). In all cases, otherthan module insertion/removal 5 (and power recovery after an outage),the information is written from the RAM 18tothe bubble memory atthe normal access time at the end of collection periods. In the illustrated embodiment, these occur every four hours starting at midnight.

TABLE 1 - INSERTION RECORD Page Data N o. of Bytes 1 Month, day, hour, min. (of Insertion) 4 Identifier Number O.D.) 5 20 Insertion Total Count (Channel A) 3 Insertion Total Count (Channel B) 3 (zero-filled) 3 2 Month, day, hour (Start of Current Collection Period) 3 Event Data for Channels A and B for five Demand Intervals 15 25 3 Event Data for Channels A and B for six Demand Intervals 18 4 Event Data for Channels A and B for five Demand Intervals 15 Running Total (Channel A or B, depending on 2 which had been written last) Status 30 TABLE 11 - NORMAL RECORD Month, day, hour (Start of Current Collection Period) 3 Event Data (A and B for five Demand Intervals) 15 35 6 - Event Data (A and B for six Demand Intervals) 18 7 Event Data (A and B for five Demand Intervals) 15 Running Total (A or B, alternatively) 2 Status 40 TABLE Ill - REMOVAL RECORD Page Data N o. of Bytes 638 Month, day, hour, min. (Removal Time) 4 45 Identifier Number (LD) 5 Channel A Removal Total Count 3 Channel B Removal Total Count 3 (zero-filled) 3 639 Month, day, hour (Collection Period Start Time) 3 50 Event Data (A and B for five Demand Intervals) 15 640 Event Data (A and B for six Demand Intervals) 18 641 Event Data (A and B for five Demand Intervals) 15 Running Total (A or B) 2 Status -1z 55 The records to be discussed presently are illustrations for a two channel (A and B) recorder since the single channel device is more simple. With reference to Table 1,the first page of an Insertion Record contains the time (current month, day, hour and minute) of module insertion in the first four bytes and a five-digit Identifier Number (in BCD format and comprising the 1D. referred to throughout) is contained in the nextfive bytes. The 60 Channel A and Channel B Insertion total counts (i.e. cumulative counts of event data as of thetime of insertion) are each contained in three bytes and the remaining bytes of the first page are zero-filled. The remaining three pages of an Insertion Record are the same as a Normal Record, to be discussed presently, except that the memory locations associated with demand intervalsthat have expired priorto insertion forthe current access period are zero-filled up to the location associated with the current demand interval. The event data for 65 1200 1415 1421 40 1600 2000 0000 0400 45 0430 6 GB 2 136 613 A 6 remaining demand intervals for the current collection period are entered in the normal fields for that record.

With reference to Table II which illustrates a Normal Record, data for each collection period is recorded on three pages of the bubble memory in the following order. The first three bytes of the first page store the time (month, day, and hour) of the commencement of the collection period for which the associated event data is stored. The next forty-eight bytesrecord the measured event data for Channel A and Channel B forthe sixteen 15-minute demand intervals comprising the four-hour collection period. It takes twelve binary digits (one and one-half bytes) to record up to 4096 (2 12)event pulses fora given channel in one demand interval. Hence, in the case of a two-channel recorder, the twelve bits for Channel A are recorded in one full byte (memory word location) andthefirstfour bits ofthe nextsucceeding byte. The eventdata forChannel Bforthe same interval is 1C stored in the last four bits of the second byte mentioned and the full eight bits of the next byte. The order of storage makes no difference as long as it is accounted for in the software of the translator (actually Channel B data is recorded first).

Running Total countfor Channels A and B is recorded in alternate Normal Records in two and one-half of the last three bytes of the third page. Thus, the Running Totals are cumulative counts of measured event data which are up-dated at the end of each collection period.

One-half byte (four bits) of storage is reserved for status information. Bits B20 and B21 are reserved for failure indication of the Read-AfterWrite test. Bit B22 indicates whether the accompanying Running Total for that record is associated with Channel A or Channel B. Bit B23 indicates whether a powerfailure has occurred during the collection period associated with that record.

Referring to Table Ill which defines a Removal Record, upon removal of the memory card,the partial period 20 data is written into pages 638-641. Page 638 contains the time (month, day, hour and minute) of module removal in the first four bytes and the LD. code in the next five bytes. The Channel A Removal Total count is recorded in bytes 8-10 and the Channel B Removal Total is recorded in bytes 11-13. The remaining bytes of page 638 arezero-filled. The lastthree pages are similarto a Normal Record (Table 11) exceptthatthe partial data forthe period of removal iswritten intothe memory locations associated with demand intervals priorto removal, and the remaining locations representing subsequent demand intervals are filled with zeros.

To illustratethe various recordsjust described, reference is madeto ChartA in whichthe left-hand column indicates running time. Assuming four-hour collection periods, attime 1200, a Running Total for Channel Ais transferred as part of a Normal Record (Table 11) to a firstsolid state memory module. Assuming thatthefirst memory module is to be replaced at 1415, when the handle 49A (Figure 5) is turned to the removal position, the 30 contacts 49C, 49E open; and the microprocessor prepares a Removal Record (Table 111). The Removal Record includes, on page 638, Removal Total counts for Chart A Normal Record-Running Total for Channel A Removal Record-Running Total for Channel 8, Removal Total for Channel A, Removal Total for ChannelB Insert New Module Insertion Record-Running Total for Channel A, Insertion Total for Channel A, Insertion Total for 40 ChannelB Normal Record-Running Total for Channel 8 Normal Record-Running Total for Channel A Normal Record-Running Total for Channel 8 Removal Record-Running Total for Channel A, Removal Totals for both Channels A and B 45 Channel A and for Channel B, each comprising three full bytes. In addition, the Removal Record includes a Running Total forChannel B (sincethe Running Totals are alternated forthe two channels).The Running Totals comprise two and one-half bytes- in otherwords, the lower ordertwenty bits of the Removal Total (which is three full bytes or twenty-four bits). In other words, in this case, the Running Total for Channel B will 50 correspond to the lower order twenty bits of the Channel B Removal Total count.

When the new memory module is inserted, at 1421 in the example, the microprocessor prepares an Insertion Record (Table 1) in RAM; and this Insertion Record is transferred to the memory module at the end of the collection period during whichthe new memory modulewas inserted- namely, at 1600 hours. Atthistime,the Insertion Record includes a Running Total for Channel A (twenty bits) as well as Insertion Totals (twenty-four bits) for both Channels A and B. The Insertion Totals on the Insertion Record will be identical to the Removal Totals stored on the first module, but the Running Total for Channel A will include any measured event data occurring between removal of the first module (at time 1415) and the end of the collection period (time 1600).

At the end of each subsequent collection period, Normal Records are stored with Running Totals for alternate channels. Assuming that this memory module is removed at 0415 hours, a Running Total (twenty 60 bits) would be partof the Removal Record forthat partial period; and Removal Totaiswould also be stored for both Channel A and Channel B. By thus storing both Removal Totals and Insertion Totals, as well as Running Totals, complete data continuity can be maintained forthe records, and if an error does occur, it can be isolated to a given demand period, so as to minimize the loss of data.

7 GB 2 136 613 A 7 Referring now to Figures land 5, the recorder includes a five digit LED type display 37 for displaying various information provided by the microprocessor. The display data is coupled from the CPU 16 via 1/0 device 34 and the data bus 51.

Therearetwo push button switches designated 39and40 in Figures 1 and5whichare usedto selectthedata that is to be displayed on the display 37 as well as to set the I.D., time and calendar data. It is considered an important advantage thatthis data can be set by maintenance personnel on site. For example, if it appearsthat the recorder is inoperative orfaulty, the system can be built such that eithera complete new unitor individual circuit boards may be replaced. Hewould then setthe identification numberof the old recorder, as well astime and calendar information, without having to return tothe factory. This not only saves a maintenance trip, but it reduces that loss of billing data.

Normally the system displays the hour and minutes. If the operator wants to set data he first sequentially presses switch 40 (orsimply leaves itdepressed in which casethe itemsto besetwill be sequenced in thesame order, but bythe internal clock of the system). Referring to Table IV, the firsttimethat switch 40 is depressed, the five-digit [.D. number will be displayed, and the first digit (the most significant digit or digit 5) will be flashed. Ifthe display is left inthis state, subsequent depressions of switch 39will sequence that digitto the ten 15 possible states (decimal digit 0-9).

If, before setting that digit, the operator had continued depressions of switch 40, the system would cycle through the parameters shown in the middle column of Table IV. For example, on the eighth depression of switch 40,the month and datewould be displayed,the month would beflashed onthe display, and subsequent depressions of switch 39would sequencethe month (1-12). Ultimately, with sequential depressions of switch 20 40, the system reverts to program control in which the hour and minute are displayed.

If switch 39 is depressed first, the system goes into a Command Display Mode. In this mode, sequential depressions oftheswitch 39 causethe display of the following information in the orderlisted: (1) word 1: I.D.:

(11) word 2: year/day of week; (111) word 3: month/day; (]V) word 4: hours/minutes; and (V) word 5: "PULSES" (which represents the Field Test Function). If switch 39 is held down in the Command Display Mode, the system 25 will cycle through these words in the above order with a display time long enough to perceive the Field Test

Function on the five-digit display 37.

To implementa field test function, the operatorsimply pushesswitch 39first. The controller, which normally displays hours and minutes, immediately displays the information the CPU has received from the 1/0 circuits 19 on data bus 51 and stored in a register. Channel A is displayed in one digit location (the further one on the 30 left, for example), Channel B on another, and so on, if more channels are employed. As the state of the associated pulse initiator changes responsive to the consumption of energy, the signal being displayed alternates between a "I" and a "0" to indicate operativeness to the operator.

In its cyclic operation of the program,the CPU looks atthe contents of the register and if they have changed from the data previously stored in RAM memory, thereby indicating a change of state in the associated pulse initiator, then a display subroutine is entered which changes the digit being displayed in the display location associated with that particular channel. It is an important function of this type of test that not only is the pulse initiator working, but also the data input channel electronics and microprocessor and RAM storage, etc., are also functioning properly, as well as the display logic and display.

To describe the Read-After-Write test in more detail, after a complete record is written in the bubble 40 memory,the data is read out in a first-in first-out (FIFO) register in the memory controller. The data in the FIFO register is then transferred a byte at a time to a D register in the microprocessor which then compares the contents of the D register with the data that had been written to the bubble memory. Any detection of non-equality indicates a failure of the test. This procedure is repeated three times. If the Read-After-Write test fails three successive times, bits B20 and B21 are setto l's in RAM to indicate such failure, and this record is 45 written into the bubble memory a fourth time for permanent storage. A visual indicator 48 of Figure 5, which may be an LED, may be caused to flash to alert personnel.

TABLE]V so 50 Word Selected Parameter Set By Switch 40 Parameters Displayed By Switch 39 1 5 Digit ID Digit 5 2 5 Digit [D Digit 4 3 5 Digit ID Digit 3 55 4 5 Digit ID Digit 2 5 Digit]D Digit 1 6 Year/Day of Week Year 7 Year/Day of Week Day of Week 8 Month/Date Month 60 9 Month/Date Date Hours/Minutes Hours 11 Hours/Minutes Minutes 12 Reverts to program control and starts internal clock 65 8 GB 2 136 613 A 8 As indicated above, the device 49A is operator-actuated and has two states indicating respectively whether the memory module is in operative relation with the recorder or not. When the operator actuates it to permit the memory module to be removed, it generates a signal for enabling the CPU 16to writethe special Removal Record (Table 111) into a predetermined location of the bubble memory. This tables only about 100 ms.

Similarly, when the new module is inserted andthe lever49Ais movedtothe positionshown in solid in Figure 5, it generates a signal to cause the CPU to preparethe Insertion Record (Table 1) in RAM. It is noted thatthis record is notwritten into the firstfour pages of the new memory until the end of the collection period during which the new module is inserted. Briefly, the device 49 operates contact 49E of switch 61 (Figure 1) which triggers a sensing circuit 62 for generating a control signal which is transmitted to the CPU 16 via 110 circuits 34, which may be conventional peripheral interface adapter circuits.

The foregoing description of the magnetic bubble memory system 12 describes a two-channel billing recorder. For a single channel recorder, the bubble memory module provides data storage for 213 8-hour collection periods. The assignment of memory locations for a single channel recorder is similar to that illustrated in Tables 1-111 for a two channel recorder in that 12 bits (one and one-half bytes) are provided for each demand interval. Hence, the 48 bytes which contain event data provide storage for 32 demand intervals for a15 single channel input, rather than 16 demand intervals as in the two channel recorder. Also, those bytes assigned for storage ofthe Running Total forthe second channel of atwo-channel recorder contain the single channel Running Total in the case of a single channel recorder.

Referringto Figures 1 and 3, each billing period (comprising a pluralityof collection periods) is commenced when an erased (zeroed) bubble memory module is inserted into the recorder. By way of example, let it be 20 assumed thatthe erased module is inserted on December 18 at 8:35 A.M. Upon operation of the device 49 to latch the memory card 24 into place, the cam 49C engages contact 49E causing the sensing circuit 62 to generate a control signal which is transmitted to the CPU 16via 1/0 circuit 34, causing itto preparethe Insertion Record in RAM. Specifically, itstores data representingthe month, day, hourand minute in RAM 18 along with the identifier code word for su bseq uent transfer to the bubble memory. TheCPU 16 causeszerosto bewritten 25 into RAM 18 in storage locations allocated to demand intervals of the current collection period for the two intervals which have already expired, namely, the two demand intervals from 8:00 A.M. to 8:30 A.M.

Afterthe module insertion time has been stored in RAM 18, the CPU 16 accumulates data pulses forthe rest of the current access interval. The CPU 16, via input/output interface 19, scansthe outputof the data channels A and Band maintains a running count of the numberof event pulses received for each channel forthe balance 30 of the collection period. The running count is also maintained in the RAM 18.

Atthe end of each demand interval, as indicated bythe digital clock of the microprocessor system 1 1,the CPU undercontrol of instructions stored in ROM 17 selects different storage locations intheRAM 18forstoring datawords representing respectively the total numbersof pulses received over channels A and B during each demand interval. Twelve bits are allocated for each channel for each demand interval. The CPU 16 also 35 maintains a running total of the data pulses received over each data channel A and B in separatetotal count registers. These totals are continuously updated for each timing pulse derived from the line frequency, in the normal case (i.e., where there is no power outage).

Atthe end of the partial period following insertion of the new memory module,the CPU 16transfersthe data stored in RAM 18to the bubble memory 23 to providethe Insertion Record in accordance with Table 1. First,the 40 CPU 16 generates a signal for enabling solid state switch 29to apply DC powerto the DCto DC converter28for energizing the memory system 12. The CPU 16 also generates an address forthe bubble memory system 12to address the first page of the bubble memory module 23.

The four data words representing the month, day, hour and minute of insertion aretransferred as a pageto a FIFO register in the memory controller 21. A write command is then issued by the CPU 16 to cause the data to be written into the bubble memory. The memory controller 21 responds to the control signals provided by the CPU 16 to enable the function timing generator 42 to generate the control signals for effecting the write operations for application to the function driver 43 and coil drivers 44. The identifier code word as well as all other data of page one of an Insertion Record is transferred to the memory controller at the same time. The rea d-afte r-w rite test described above is performed after each complete record is transferred to the bubble 50 memory.

When this first page of Insertion Record has been written into the memory 23, the CPU 16 then effects the transferto the memory 23 of the demand data forthe current collection period. The CPU generates an address for the bubble memory system to access the second page of the bubble memory module 23 and causes data representing the month (December), the day (18), and the hour (12 o'clock), defining the end of the current demand interval, to be written into the first three bytes of page 2 as shown in Table V. The memory locations (bytes 4-9) allotted to event data from the time 8:00 until the end of the demand interval immediately preceding insertion are zero- filled- namely, the demand intervals beginning at 8:00 and 8:15 for each channel. The data for channel B forthe first partial demand interval (8:30-8:45) is recorded in thetenth byte and the firstfour bits of the eleventh byte. The corresponding data for channel A is recorded in the lastfour bits of the eleventh byte 60 and the eight bits of the twelfth byte. Event data for the demand intervals up to 9:15 A.M. are entered in the normal fields for that record on page 2 of the memory.

i z 9 GB 2 136 613 A 9 TABLE V - INSERTION RECORD - Page 2 Byte Information Data 1 Month 12 2 Day 18 5 3 Hour 12 4 8:00-8:15 (B) zero OO(B)/OO(A) zero 6 8:00-8:15 (A) zero 7 8:15-8:30 (B) zero 10 8 15(13)/15(A) zero 9 8:15-8:30 (A) zero 8:30-8:45 (B) partial 11 30(B)130(A) partial 12 8:30-8:45 (A) partial 15 13 8:45-9:00 (B) filled 14 45(B)/45(A) filled 8:45-9:00 (A) filled 16 9:00-9:15 (B) filled 17 OO(B)/OO(A) filled 20 18 9:00-9:15 (A) filled The CPU 16 then addresses page 3 of the memory and causes the remainder of the data for succesive demand intervals up to the demand interval beginning at 10:30 for both channels to be recorded. The first fifteen bytes of page 4 then record event data for demand intervals up to the demand interval beginning at 25 11:45 A.M. The running total count forthe data for channel A is written as the first twenty bits of the last three bytes in page 4, as explained above.

After the partial data forthe first collection period has been written into the bubble memory and verified by recall in the CPU, the CPU 16 disables the solid state switch 29 thereby de-energizing the bubble memory system 12 during the next four-hour collection period. Also, the insertion of the bubble memory is sensed by 30 the CPU which generates a currentto change the state of the bistable indicator 47 to indicate thatthe bubble memory now stores data.

When a new (i,e,, erased) bubble memory is inserted in the recorder, the CPU decrements an interval timer register which is originally set to represent a predetermined thermal time period representative of the worst-case time for the bubble memory to achieve its operating temperature. The wtiting of data into the 35 bubble memory is inhibited until the end of thethermal recovery period. Thethermal recovery period could be implemented mechanically, and would not even be required, of course, if the bubble memory specifications permitted operation through the full range. If the thermal recovery period overlaps the access time (i.e., extends into the next collection period), the CPU transfers the Insertion Record to an unused section of RAM until the time-out signal is generated, and itthen transfers the Insertion Record data for storage in the bubble 40 memory, even though it is not at the normal access time.

During the next collection period, the data is accumulated in the RAM 18 and transferred to the bubble memory 23 as a Normal Record, as shown in Table 11. It will be observed that for this collection period the running total count for channel B is recorded in the first twenty bits of the last three bytes of page 7 of the bubble memory. The remaining pages are filled with Normal Records in like manner such that a total of up to 45 213 four-hour collection periods are recorded, including the two partial intervals when the memory card is inserted and removed. The total count register of each channel is updated at the occurrence of each timing pulse.

Should a power failure occur (that is, the loss of 60 Hz. line voltage) during a collection period, an oscillator 32 (which may be the internal oscillator of the CPU) is used to generate the time base. The frequency of the 50 oscillator signal is counted down by a divider circuit 31 to supply a time reference for the CPU 16. The CPU determinesthe power outage by sensing forthe 60 HZ. line signal. Briefly, the 60 Hz. line signal is shaped into a pulse, and the CPU enters a loop comprising an interval timer. If the interval timer times out before the line frequency pulse is detected, the CPU defines it as a power outage and switchesto crystal clock of oscillator32 divided by divider circuit 31. This signal has a repetition rate of approximately 61 Hz. The DC power maintains 55 the controller circuits energized during the power outage preventing loss of stored data and allowing the CPU to continue generating its time reference. However, the displays are disabled to conserve battery power.

When it istimeto removethe memory card 24atthe end of the billing period, the device 49 is actuated bythe exchange personnel and the CPU effects the recording of the Removal Record in accordance with the format set forth in Table Ill. If the memory module is removed before the end of an access period, the partial record, 60 which is recorded in the last four pages of the bubble memory includes all of the data recorded in RAM during the access period. The CPU 16 also energizes an indicator 35 to indicate that a data transfer operation is in progress.

As illustrated in Table Ill, the month, day, hour and minute of module removal are recorded in the first four bytes of page 638. The data in the partial demand interval is transferred to RAM. Whenever event data is 65 GB 2 136 613 A written in the bubble memory and has been verified, whether atthe end of a normal collection period or atthe end of a billing period when the memory is being replaced, the interval counters are reset to zero. The total counters remain updated at all times, and they roll over at a predetermined cumulative count. However, upon the first application of power, whether as a result of a power outage or recorder instal lation or replacement, the total counters are initialized be setting the contents to zero. Then the event data for both channels is written into pages 639-641 of the memory, preceeded by the five digit identifier and the running total counts for channels A and B as illustrated in Table Ill.

The customer has an option as to whether or not to account for daylight saving time changes via the Select D.S.T. input 33B of Figure 1. In this embodiment, a computation is madeto definethe lastSunday of the month 1() during which a DST/STchange is implemented. If he selectsthis option, inthe spring when the change isto be implemented, two functions are performed: (1) the clock is incremented by one hour at 2:00 A.M. on the Sunday in which daylight saving time is implemented; and (2) the four demand intervals for each channel (assuming a 15 minute demand interval) associated withthe hour2:00 A.M.to 3:OOA.M. ofthatday haveto be zero-filled. This is accomplished, briefly, by loading zeros into the associated demand interval portions of RAM and then writing that information into the bubble memory. Thus, the bubble memory is zero-filled for the demand intervals between 2:00 A.M. and 3:00 A.M. The event data is collected for the daylight saving time hour 3:00 A.M. to 4:00 A.M., and this data is written into the bubble memory in association with the proper demand intervals at the end of the next collection period.

In the fall, the clock is turned back an hour in switching from daylight saving time to standard time. Two separate records are prepared. In the first record, the four demand intervals forthe hour between 12:00 and 20 1:00 as well asthe four intervals forthe hour between 1:00 A.M. and 2:00 A.M. have normal event data. The remaining two hours for that collection period are zero-filled to comprise record R1. This is written into the bubble memory at or shortly after 2:00 A.M. At the same time, the second record, namely record R2, is prepared by zero-filling the first four demand intervals comprising the hour 12:00 to 1:00, and thereafter, normal data is collected and stored. This record is written intothe bubble memory at4:00 A.K,the end of the current collection period.

In the foregoing description, the recorded bubble memory modules are exchanged foran erased module at the end of each billing period, and the recorded modules are transported to a translating center for reading.

In Figure 4there is illustrated a block diagram of a system which permits remote readout ofthe recorded data over a communication link 70, such as atelephone link, established between thetranslating center71 andthe 30 point of service 72 where the billing recorder is located.

An interrogate controller 73 at the translating center generates audio frequency interrogate signals which aretransmitted overthe link and coupled via line coupler74to a data transponder75 associated withthe billing recorder. The data transponder receiver 81 detects the audio frequency interrogate signals and generates suitable logic level control signals for application to the billing recorder circuits to effect readout of the 35 recorded data. The data transponder includes a transmitter82 which converts the logic level data signals read out into audio frequency signals, coded to represent the data, for transmission to the translating center.

Aconventional telephone set78 at the translating center is used to place a call tothe numberassigned to the telephone line coupler 74 causing the data transponder 75 to be coupled to a telephone line 79 which forms part of the telephone link. When the link is established, a read signal at a preselected audio frequency fO is 40 transmitted from the translating centre to the data transponder and detected by audio frequency receiver 81 which includes a line detector which converts the received audio signal to a logic level read command signal.

The command signal is extended to the billing recorder controller by way of 1/0 circuit 34 (Figure 2), for example.

The CPU 16 responds to the read command to effect sequential readout of the data stored in the bubble 45 memory 23. The data read out is extended via the 110 circuit 34 to the transmitter 82, which responds to the logic 1 and logic 0 level data signalsto generate audio frequency reply signals at different audio frequencies fl and f2 respectively, for transmission to the translating center, where the frequency coded audio signals are converted to a data format suitable for processing and transferred to a suitable storage medium.

Referring to the flow charts, Charts 1 and 11 describe the overall system operation. Chart Ill takes the data 50 including the index and event data recorded in RAM during Power Fail Mode 11 to establish the necessary format for recording that data in the bubble memory. Chart W describes the operation of the program during Power Failure Recovery mode 11 for storing index numbers identifying associated demand intervals and the event data in RAM. The connectors shown on Charts Ill and IV reference backto the main flow chart- namely, Charts 1 and 11 as applicable.

In orderto minimizethe chances of data loss during a power outage, a separate section of Random Access Memory is provided. For convenience, this is sometimes referred to as RAM 11. If a power outage (plus the thermal recovery period) would span into a collection period subsequenttothe collection period in whichthe power outage first occurred, the system enters into a special power outage recovery mode.

Briefly, according to this recovery technique, atthe end of the collection period in which the power outage 60 occurred, the event data is transferred to RAM 11 portion of memory in the controller, and the portion of Random Access Memory thus evacuated, called RAM 1, is used for storing data in a different format. The microprocessor is programmed such that when a power outage is detected, it uses its own internal clock to generate time reference data, and an index counter is incremented each demand interval. If power is not returned during a demand interval, the index counter is incremented but event data is not stored (since the 65 i d; 11 GB 2 136 613 A 11 power outage continues). Thus, memory space is not used for those demand intervals during which line power is not available. If power is returned for a period of time less than the thermal recovery period (for those systernswhich requirethermal recovery periods dueto manufacturer's specifications on the bubble memory), the contents ofthe index register representative of a demand interval andthe associated eventdata are stored in RAM 1. In this manner, storage is used mostefficiently only for those demand intervals during which power was being applied. The system then writes the data into the bubble memory atthe end of a thermal recovery period bytransferring the contents of RAM lifirst andthen re-constructing the data temporarily stored in RAM 1 into the required format in RAM 11 and then writing that data into the bubble memory. As data is taken from RAM 1, converted into the original format and transferred from RAM 11 for storage in the bubble memory, the remaining data in RAM 1 is advanced in memory, similar to the operation of a stack memory, so that as much 10 space as possible is made available for data storage in the event of a subsequent power outage prior to the time all of the data in RAM 1 is converted and stored in the bubble memory.

Turning then to flow chart 1, terminator block 101 indicates that on initial system power up the program proceedsto address 0 which then branchesto process block 102which isa cold start subroutine, proceedingto block 103, in which the registers (demand and total) and Random Access Memory are initialized. After the 15 registers are initialized,the program proceeds as indicated in process block 104to maintain the system in its present state (i.e., no data transfers to bubble memory) until a service operator removes the bubble memory, sets the clock, [D and time of the system, and then inserts a new bubble memory.

In process block 105,two RAM pointer registers and a constant zero registerare reset. In decision block 106, the system determines whether the Magnetic Bubble Memory is being removed (this is done by sensing 20 whether the contacts 49E, 49C have changed state). If it is removed, the program proceeds via process block 107to setthe "MBM removed" flag and to clear a fatal errorflag, and itthen proceedsto a junction point above a block labeled 115, to be described.

If the bubble memory is determined to be in place in block 106, the program proceeds to decision block 108 where it is determined whether a removed- flag has been set. If it has not, the program proceeds to the 25 junction point above block 115. If the "removed" flag has been set,the program proceedsto decision block 109 to determine whether the removal had been a normal removal, and if so, the program proceeds to block 113 where it compilesthe data forthe insertion or removal page comprising a portion of the previously described Insertion Record or Removal Record. A "normal" removal is defined as one in which the set mode is not entered indicating that the operator did not have to set any of the clock or calendar or ID parameters. 30 If in block 109 the system determinedthat removal had not been under normal circumstances, the event data counter for demand intervals is cleared in block 110. Next, the program determines in decision block 111 whether the memory is being inserted or removed. If in block 111 the program had determined that it is an Insertion Record, then it proceeds to process block 112 which clears the RAM area designated RAM 1 which is the normal portion of RAM in which the event data is accumulated according to demand interval. For purposes of explanation, the data of RAM 1 is transferred to RAM 11, a corresponding 48-byte portion of Random Access Memory used for storage of the event data while it is associated with the necessary data that accompanies a Normal Record (which also is included in the Removal and Insertion Records). A separate 18-byte portion of RAM is reserved for compiling the additional necessary data for Insertion Records and Removal Records.

Proceeding from block 113 to block 114, the program initializes the parameters associated with the newly 40 inserted bubble memory. In block 115, outputsignals are generated forcontrolling all of the external devices associated with the system such as indicators, the demand interval termination indicator, etc.

Following the generation of output signals, exclusive of transferring data to the bubble memory, the program proceedsto decision block 116 in which it is determined whether Power Fail Mode 1 (PFI) is entered.

Referring to Figure 6, Power Fail Mode 1 is defined as commencing with the determination bythe CPU that a 45 poweroutage has occurred, see arrow81. PowerFail Mode 1 extendstotheend of the current collection period in which the power outage occurred (see 82). The program proceedsto process block 117 in which the power outage parameters are set up both for Power Fail 1 and 11, sometimes referred to as PFI and PHI for short.

If, in block 116, it has been determined that PFI had not been entered, the program decrements the PFI timeout counter in block118andin 119thesystem determines whether the 60 Hz. linesignal is present.Thisis 50 determined in a program loop time by the main crystal oscillator of the CPU. If the 60 Hz. clock is not present within the time allotted (Le. the counter of block 118 is decremented to zero), it is taken as an indication that power has been lost. Thus, once a power outage has been detected, the program proceeds to block 117, described above. Afterthe power fail mode parameters have been set in block 117, the program proceeds to process block 120 and waits for the power outage clock (namely, the crystal oscillator 32 and divider 31) and 55 continues to check for return of power by continuing to look for the 60 Hz. timing signal from the external source.

When eithertiming signal is detected, the program jumps via connector No. 4to block 122. Returning backto decision block 119, if it is determined that the normal 60 Hz external clock is not overdue (i.e. it is detected before the counter of block 118 is decremented to zero), the program proceeds to decision block 121 inwhichit 60 is determined whetherthe actual clock signal has been detected. If not, the program loops backto the junction point prior to block 115 via connector No. 3.

Ifthe external clockis detectedto haveoccurred in block 121,the program proceedsto block 122. Whenthe clock does arrive, data counts accumulated in a register are transferred to RAM.

Next, in block 123, it is determined whether the system is being operated in a SET MODE, and if it is, the 65 12 GB 2 136 613 A 12 program proceeds via connector No. 6 to instruction number 246 of the clock-calendar subroutine represented by process block 125 on Chart 11, to be described.

If, in decision block 123, ithas been determined thatthe system is notbeing operatedin SETmode,thenthe program proceedsto cleara SetModeflag in block124,and proceedsvia connectorNo. 5to block125of Chart II.Theclockcalendar routine updates the clock and calendar information andkeeps itcurrent.The reasonthat 5 there is a branch from the decision block 123 into the clock-calendar routine is in the case where an operator may be setting the date of a month, the program will not enable him to enter a non-existent date.

Next, in block 126,the system checksto see whether it is operating in daylightsaving time as well aswhether it is time to implement a switch to or from daylight saving time, and implements the appropriate function.

Next, in decision block 127,the system determines whether it has arrived atthe end of a demand interval, and if so it proceeds to block 128 to initialize certain RAM pointers.

The program then proceedsto block 129 in which it is determined whetherthe system is operating in Power Fail Mode 11. If it is, the system proceeds to block 130 and saves the non-zero data in PHI format as will be described more fully below. Next, the system determines whether the thermal recovery period has termi- nated, and if so, it proceedsto thejunction above block 142 via connector No. 7. If thethermal recovery period 15 has not terminated, the program loops back to block 105.

If in block 129the system has determinedthat Power Fail Mode 11 has not been entered, in block 132, itsaves the event data in normal format, and proceeds to decision block 133 to determine whether it is the end of a collection period. If it is notthe end of a collection period, the program proceeds to decision block 144, to be described.

Returning backto block 127, if the program had determined that itwas notthe end of a demand period, the program proceeds to decision block 134 to determine whether a complete data record has been recovered sufficient to transfer to the bubble memory. If itis notcomplete,the program proceedsto a powerfail recovery routine as indicated in block 135 and described further in connection with Chart Ill.

If, in block 134, the system had determined that complete data had been accumulated or compiled for PF 11 25 recovery, the system proceeds to block 136 to determine whether it is in Power Fail Mode 1, and if so, it jumps via connector No. 2 to block 105 of Chart 1. If in block 136 it is determined that the system is not in Power Fail Mode 1, it proceeds to a subroutine in block 137 to compile the output data for display on the five-segment digital display 37 of Figures 1 and 5.

Entry of the system into PF 11 mode occurs wheneverthe system is readytowrite intothebubble module but 30 is unabletodo so. Itwould not beableto do so ifthe powerwas off, in which case a temperature badflagwould be set, or while in a thermal recovery period, where the temperature bad flag would still be set.

Referring to Chart 11, in block 133 the processor has determined that the end of a collection period has been reached, meaning that the system is now ready to write to the bubble module. In block 138, the processor moves the data, calendar information, and a channel total to RAM 11 in anticipation of writing to the bubble 35 module. A removal page is also assembled fortransferral if the module is aboutto be removed in blocks 139 and 140. In block 141, the temperature bad flag is checked and if it is determined thatthe temperature prohibits the writing of the information to the bubble the system will enter PF 11 mode.

Returning to block 133, if it had been determined that it is the end of a collection period, the program proceedsto process block 138 in which a record is compiled fortransferring the eventdata and associated data 40 forone ofthe recordstothe bubble memory. In particular,the event datawhich has been accumulated in RAM 1 is transferred to RAM 11 where it is associated with the necessary time, date and total data for storage in the bubble memory. Next, in decision block 139, the system determines whether the bubble memory is being removed, and if it is,the system compiles data forthe last page of a Removal Record in block 140. The system then proceeds to block 141. Itwould have proceeded directlyto block 141 if it had been determined in block 139 that the bubble memory is not being removed. In block 141, a determination is made as to whether a thermal recovery period has ended; and if it has, in block 142, a subroutine is entered ortransferring data from RAM to the bubble memory, whether it is a Normal Record, an Insertion Record, or a Removal Record. If in block 141 it had been determined that a thermal recovery period is still present, the program proceeds to block 143 where it enters Power Fail Mode It, and jumps via connector No. 2 to block 105 of Chart 1.

Returningto block 144, a determination is made asto whetherthe system haschangedfrom daylightsaving time to standard time and if it has, the DST-STD time change flag is cleared in block 145. If the change is determined notto have been made in block 144, a determination is made in block 146 whetherthe system is operating in a "Cold Start" mode, and if it is, it proceeds via connector No. 1 to block 104 of Chart 1.

A cold start will be entered only under three circumstances. The first one will be the initial application of 55 power upon system installation. Another time a cold start could be entered is immediately following re application of power after a prolonged power outage with the battery fully discharged. A cold start requires operator intervention to setthe clock and ID, andto removethe old bubble modulefromthe recorder before it will again begin normal operation.

If in block 146 it had been determined that a "Cold Start" mode is not being implemented, the system 60 proceedsto block 147 to determine whether the system is in athermal recovery period; and if itis,the program jumps via connector No. 2 to block 105 of Chart 1. If the bubble memory is operating within temperature specifications, the system determines whether the bubble memory power is on in block 148, and if it is, it jumps via connector No. 8 to block 141 on Chart 11.

If the bubble memory power is not on as determined in block 148, the system determines in block 14965 Q 13 GB 2 136 613 A 13 whether the bubble memory is inserted, and if so, it jumps by a connector No. 2 to block 105 of Chart 1. If the bubble memory is not inserted, the system implements a routine in block 150 for initializing removal parameters, and jumps via connector No. 9 to block 128 of Chart 11.

Referring now to Chart IV, which formats the data for storage in Power Fail Mode 11, this chart is a more detailed flow chart of block 130 of Chart 11 described above.

This subroutine commences in terminator 154 and proceeds to process block 155 for intializing address registers and pointers. In block 156the program determines whetherthere is any portion of RAM 1 leftto store additional data, and if there is not, it proceedsto block 157, it enters zeros in the register holding the event data for the current demand interval, and jumps via connector No. A3 to block 159. If there is additional storage room in RAM 1 as determined in block 156,the program proceedsto block 158where it is determined whether 10 any event data has been detected forthe current demand interval, and if it has not been detected,the program proceeds to block 159 to determine whether a thermal recovery period is being implemented. If it is, the program proceeds via connector No. 2 to block 105 of Chart 1, and if the operating temperature of the bubble memory is within specifications, the program jumps via connector No. 7 to block 142 of Chart 11.

If in block 158 the program determines that there is current event data, then it proceeds to block 160, a 15 register pointer is set as will be described. Next, in block 161, the address associated with the location for storing the data is loaded into the address register. This isthe next sequentially occurring address available for storage in RAM 1. Next, in block 162, an index number associated with the address defined in block 161 is stored. This index number, as indicated above, is representative of the demand period following the entry into Power Fail Mode 11. In block 163, the demand interval event data is stored in RAM, and in block 164, the 20 incremented address for storing data is saved, and the program proceeds to block 157 to reset the demand interval register for the next demand interval.

To summarize operation of the system in Power Recovery Mode 11, the CPU determines whether there is non-zero data associated with a current demand interval. Ifthe data is all zeros, it istaken as an indication that power is still out, and no data is stored, butthe contents of the index register are incremented atthe end of that 25 demand interval. Thus, the contents of the index register are representative of the number of a demand interval following thetime atwhich the system enteredthe Power Failure Mode It. Two bytes (16 bits) identify an index number and two bytes are used for recording non-zero event data for each demand interval per channel. If it is determined thatthe data associated with a given demand interval during PF 11 is otherthan zero, then the data is stored as follows: the contents of the index register representative of the demand interval is 30 stored in two bytes, andthe event data is stored in two bytes. Itwill be appreciated that power may return fora time less than the thermal recovery period, in which case the event data is not lost, but preserved in RAM.

The time and calendar data is not reconstructed in going from the compacted storage format of PF 11 to a normal record. Thetime and calendar information can be reconstructed in thetranslation system based on the calendar and time data contained in the preceding and following records that are written before the power 35 failure and afterfull recoveryfromthe powerfailure. Thetime data fora reconstructed normal record is relative to the position of the data within the record as referenced to the preceding and following data.

After a powerfailure which causes the system to enter PF 11 mode, application of powerwill start a thermal recovery period. Atthe end of tile first demand interval following the end of the thermal recovery period the processorwill writethe data contained in RAM litothe bubble module. When finished with the writing ofthat 40 datathe processorthen determines if data is stored in PF 11 format. If it determines that data is in PF 11 format, it then sets a flag causing the software to proceed through the power failure recovery routine on successive passes through the program. Entry to the routine occurs at block 167 on Chart 111. The program then proceeds to process block 168 which sets up register No. 4as an additional RAM pointer. In block 169, register No. 1 is set up to point at the number of demand periods that have, to this point, been recovered from the PF 11 format in 45 RAM 1. This also includes the---allzero" demand intervals (i.e., no power consumption because power has not returned) that have not been recorded anywhere, butwhich have been accounted for by incrementing the P17 11 index number.

Proceeding to process block 170, the program loads, increments and saves the number of demand periods for which data has been recovered from the PF 11 format, and proceeds to block 171 in which pointer register 50 No. 1 is set to the next available location in RAM 11. Next, in decision block 172 it is determined whether the system is recovering a record and formatting it in RAM 11. A complete record would be for a full collection period. If it is recovering a record, the program proceeds to process block 175. If it is not in the process of recovering a record as determined in block 172,the program proceedsto process block 173tofill with zeros all locations of RAM 11 exceptthe lastthree bytes. The reason forthis is that as the locations are filled with event 55 data and eventually the record becomes complete, which may be a partial record, the remaining demand intervals are filled with zeros priorto transferto the bubble memory for storage, or backto RAM 1. That is, if recovery occurs during the same collection period for which the data stored in RAM 11 is current, then the system transfers the data in RAM 11 backto RAM 1 and continuesto record eventdata forthat current collection period prior to transferring the data to the bubble memory.

Next, the program proceeds in block 174to point register 1 to the fourth byte of RAM 11 which is the starting point for storing event data to be transferred as a record to the bubble memory.

14 GB 2 136 613 A 14 In block 175, the program points register 4 to an index number representative of a demand interval associated with data being recovered from RAM 1 and transferred to RAM 11. This is used as a check, when comparing with the actual index numbers stored in RAM 1 as a validity check forthe data being formatted inthe RAM 11.

Proceeding to process block 176, the program then points register 2 to the address value identifying, if such is the case, the index number associated with the demand interval atwhich a time change is being made from daylight saving time to standard time. If such a change occurs Power Fail ModeH, an indication must be stored thatthespecial records mentioned above haveto becompiled before transfer of datatothe bubble memory.

Proceeding then to block 177, a determination is made whetherthe period number being recovered (that is, 0 the index number for which data is being recovered), equals the period number of the time change described in connection with blockl76. If the two are the same, the reset index number identified in block 176issettoO, and in block 179, the index number being recovered is decremented by 4. So that room is left on the next record to betranferredto bubble memory to "zero fill" the first four demand intervals associated with the first hour prior to a switch back to standard time - i.e. 12:00 A.M. to 1:00 A. M. - as described above.

The program then proceeds to block 188 to update the indicator which establishes whetherthetotal count 15 forthe current collection period being composed is associated with channel Aor B sothatwhen power returns, thetwowill not have been interchanged. Next, in blockl89,the lastthree bytes associated with the total count in RAM 11 are zeroed, andthe program proceedsto block 190to cleartheflag associated with incomplete record recovery as described above, Returning now to block 177, if the time change identified in block 176 is not being effected, the program 20 proceeds to block 180 to point register 2 at the start address of RAM 1 which, it will be recalled, is an index number associated with the first demand interval following the entry of PF 11 mode.

Next, in block 181, it is determined whetherthe index numberthus recovered is equal to the index number forwhich presentdata is being recovered. If it is not,the program proceedsvia process blockl82to storezeros in RAM 11 forthe associated demand interval. If the index number is the same asthe period forwhich data is being recovered,the program proceeds in block 183, it resetsthe nextstorage location in RAM Itothe location next available for storage. The program then proceeds via block 184 to store the event data recovered from RAM 1 to RAM 11 in the normal format. That is, the system is composing the record for storage in bubble memory and transferring itto RAM 11. Next, the program proceeds to shiftthe data in the remainder of RAM 1 which has notyet been recovered and shiftedto RAM litofill the available storage vacated byvirtue ofthe data 30 recovered from RAM 1 and stored in RAM 11. This facilitates having the index number always in the start location and frees up some of RAM 1 for additional storage should the system encounter another power outage.

Next, in process block 186,the system zero-fillsthe unused portion of RAM 1, and proceedsto decision block 187to determine whether RAM 11 isfilled. If RAM 11 isfilled,the system proceedsto block 188 described above, 35 and if RAM 11 is not filled, the system proceeds to block 191 in which it is determined whether the recovery period is beyond the current real time period. If it is, the program loops to block 194; however, if it is not, the program proceeds in block 192 to determine whetherthe recovery period is the same as the current period; and if it is, it proceedsto block 194. If the recovery period is notthe same asthe current period, the program sets an incomplete record recovered flag in block 193, as described above, and jumps via connector No. 2 to block 40 of Chart 1.

In block 194,the program setsthe recovered period index numberto 0, and proceedsto block 195to move from RAM Ilto RAM 1 in an effortto re-initiate normal system operation. Next,in block 196, the program clears theflag forPower Fail Mode 11 as well astheflag forincompiete record recovery and proceedsto block 197to branchtothe bubble controller subroutine to turn the bubble memory off, and then jumps via connector No. 2 45 to block 105 of the main program.

There are three user options in the system, and they are diagrammatically represented in Figure 1 byblocks designated respectively 33A, 33B and 33C. These represent selections of: (a) one or two input channels; (b) DaylightSaving or Standard Time Select; and (c) FiftyorSixtyHz. linefrequency. Each of these selectors may comprise a wired logic state, a toggle switch, or a binary circuit. 50 According to the first option, nameiyChannel Select,the user has the option of determining whether one or two inputchannels are stored inthe bubble memory. The output signal, referredto as EF2issensed bytheCPU 16and used as appropriate throughoutthe data processing. Forexample, in Chartil block132,theCPU hasto determine whether there are one or two input channels for storing demand interval data in the appropriate RAM locations, as described in detail elsewhere. Similarly, the DST/ST Select generates a logic signal EF3 55 which is used bythe CPU 16 in block 126 of Chart 11 to effect changes asthey occur and as selected bythe user.

Finally, block 33C generates a signal as selected by the user and designated EF4 which accommodates the systernto eitherfifty or sixty Hz. linefrequency; andthis information is used in block 125 of Chart lito generate clock and calendar data. Briefly, this data is generated by incrementing a register to a predetermined count (namely, to sixty in the case of 60 Hz. line frequency or to fifty in the case of 50 Hz. line frequency) for 60 incrementing a register which counts seconds and determines the program execution time.

Referring to Figure 1, there are four input channels designated respectively A, B, C, and D. Each of these channels is associated with a conventional pulse initiator for receiving input data; and each of the input channels, designated respectively 19A, 19B, 19C and 19D comprises a latch circuit responsiveto incoming data from an associated pulse initiatorfor storing ittemporarily. The output signals of the data channels are fed in 65 parallel to the input/output circuits 19 of the microprocessor which also are latching circuits.

Data channels C and D are shown in chain line because, as indicated above, the system may be a single channel oratwo channel recorder. Inthe case where channels C and D are used,thesystem maybe atotalizer that is, the event data from two input channels is accumulated and stored. Where data channels C and D are present, and it is desired to sum or"totalize"the inputs, for example, the inputs on channel A can be totalized 5 with those on channel C, and those on channel B can betotalized withthe data inputs on channel D. In this case, the microprocessor reads the data on channel A, and the data on channel C and adds either zero, one or two counts to the appropriate Running Total count for the current demand period and separately, the cumulative counts for Insertion and Removal Totals, as described above. This updating of the registers happens every input data sample period which, in the illustrated embodiment, is derived from line frequency.

Because of the high speed atwhich the microprocessor is capable of sampling input data relative to the time periods during which input data is expected to change, this capability of totalizing is inherent in the system.

That is, the problems associated with coincidence of data inputs in conventional totalizers are inherently overcome due to the structure of the system.

Attention is directed to our co-pending Patent Application No. 8103 454 (Serial No. 2 071885) from which 15 this application is divided.

GB 2 136 613 A 15

Claims (10)

1. A demand recorder comprising controller circuit means receiving data pulses representative of meas- 20 ured events and including random access memory means having primary and secondary storage locations, said controller circuit means being arranged to generate data words representative of received event data for predetermined demand intervals and to storethe same in said primary storage locations for a collection period comprising a predetermined number of said demand intervals; and non- volatile, solid state memory means removably associated with said controller circuit means and adapted for remote processing; said controller 25 circuit means being arranged to transfer said event data from said random access memory means atthe end of a collection period for more permanent storage in said solid state memory means, said controller circuit means being responsiveto a poweroutageto inhibit data transfers from said random access memory means to said solid state memory means, and said controller circuit means being arranged to transferthe data from said primary storage locations to said secondary storage locations at the end of the first collection period 30 during which a poweroutage has occurred andthereafterto store incoming eventdata in said primary storage locations in a compacted format comprising an index data word representative of a demand interval and event data associated with that demand interval.

2. The apparatus of claim 1 wherein said controller circuit means stores no event data during demand intervals of a power outage during which no event data is present.

3. The apparatus of claim 2 wherein said controller circuit means comprises a microprocessor including an index register and said microprocessor indexes said index regisrer each demand interval during a power outage whereby the contents of said index register are representative of sequentially occurring demand intervals in a power outage.

4. The apparatus of claim 3 wherein said microprocessor is responsive to said systems' being operative 40 after return of primary power to transfer the data from said secondary storage locations to said solid state memory means and thereafter to re-format the data in said primary storage locations and store the reformatted data in said secondary storage locations for subsequent storagee in said solid state memory means in the order in which the event data was received.

5. The apparatus of claim 4, wherein said microprocessor further sequentially transfers the index and 45 event data in said primary storage locations to the first-occurring addresses to thereby make room in said primarystorage locations for subsequent poweroutages shouldthey occurpriorto a complete reformatting of the data in said primary storage locations.

6. A method for recording event data in a demand recorder comprising transmitting data pulses to controller circuit means representative of measured events and including random access memory means 50 having primary and secondary storage locations, generating data words representative of received eventdata for predetermined dernand intervals and storing the same in said primary storage locations for a collection period comprising a predetermined number of said demand intervals, transferring said event data from said random access memory means at the end of a collection period for more permanent storage in a non-volatile solid state memory, inhibiting data transfers from said random access memory means to said solid state 55 memory during a power outage, transferring the data from said primary storage locations to said secondary storage locations at the end of the first collection period during which a power outage has occurred, and thereafter storing incoming event data in said primary storage locations in a compacted format comprising an index data word representative of a demand interval and event data associated with that demand interval until said power outage has ended.

7. The method of claim 6 further comprising the steps of incrementing the contents of an index register each demand interval from the commencement of a collection period during a power outage so that the contents of said register are representative of a demand interval and then storing the contents of said index register and associated event data in said primary storage locations only for those demand intervals during which event data is detected.

16 GB 2 136 613 A 16

8. The method of claim 7 further comprising detecting the return of line power and then transferring the data from said secondary storage locations to said solid state memory and thereafter reformatting the data in said primary storage locations and storing the reformatted data in said secondary storage locations for subsequent storage in said solid state memory means in the order in which the event data was received.

9. The method of claim 8 further comprising sequentially transferring the index and event data in said 5 primary storage locations to the firstoccurring addresses to thereby make room in said primary storage locations for subsequent power outages should they occur priorto a complete re-formatting ofthedata in said primary storage locations.

10. A method for recording event data in a demand recorder, substantially as herebefore described with 10 reference to the accompanying drawings.

Printed in the UK for HMSO, D8818935, 7184, 7102. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which Copies may be obtained.

g

10. A method for recording event data in a demand recorder, substantially as herebefore described with reference to the accompanying drawings.

New claims or amendments to claims filed on 3014/84 Superseded claims All New or amended claims:- 1-10.

CLAIMS 1. A demand recorder comprising controller circuit means receiving data pulses representative of measured events and including random access ' memory means having primary and secondary storage locations, said controller circuit means being arranged to generate data words representative of received event data for predetermined demand intervals andto storethe same in said primary storage locations for a collection period 20 comprising a predetermined number of said demand intervals; and non- volatile, solid state memory means removably associated with said controller circuit means and adapted for remote processing; said controller circuit means being arranged to transfer said data words representative of received event data from said random access memory means atthe end of a collection period for more permanent storage in said solid state memory means, said controller circuit means being responsive to a power outage to inhibit data word transfers from said random access memory means to said solid state memory means, and said controller circuit means being arrangedto transferthe data words from said primary storage locations to said secondary storage locations at the end of the first collection period during which a power outage has occurred and thereafter to store data words representative of incoming event data in said primary storage locations in a compacted format comprising an index data word representative of a demand interval and data words 30 representative of event data associated with that demand interval.

2. The apparatus of claim 1 wherein said controller circuit means stores no data words representative of received event data during demand intervals of a power outage during which no event data is present.

3. The apparatus of claim 2 wherein said contoller circuit means comprises a microprocessor including an index register and said microprocessor indexes said index register each demand interval during a power 35 outage whereby the contents of said index register are representative of sequentially occurring demand intervals in a power outage.

4. The apparatus of claim 3 wherein said microprocessor is responsive to said systems' being operative after return of primary power to transfer the data words from said secondary storage locations to said solid state memory means and thereafterto re-formatthe data words in said primary storage locations and storethe 40 re-formatted data words in said secondary storage locations for subsequent storage in said solid state memory means in the order in which the event data was received.

5. The apparatus of claim 4, wherein said microprocessor further sequentially transfers the index data words and data words representative of received event data in said primary storage locations; to the first-occurring addresses to thereby make room in said primary storage locations for subsequent 45 power outages should they occur prior to a complete reformatting of the data words in said primary storage locations.

6. A method for recording event data in a demand recorder comprising transmitting data pulses to controller circuit means representative of measured events and including random access memory means having primary and secondary storage locations, generating data words representative of received event data for predetermined demand intervals and storing the same in said primary storage locations for a collection period comprising a predetermined number of said demand intervals, transferring said event data words representative of received data from said random access memory means at the end of a collection period or more permanent storage in a non-volatile solid state memory, inhibiting data word transfers from said random access memory meansto saidsolid state memory during a power outage, transferring the data words 55 from said primarystorage locationsto said secondary storage locations atthe end of the first collection period during which a power outage has occurred, and thereafter storing data words representative of incoming eventdata in said primarystorage locations in a compacted format comprising an index data word representa tive of a demand interval and data words representative of event data associated with that demand interval until said power outage has ended.

7. The method of claim 6 further comprising the steps of incrementing the contents of an index register each demand interval from the commencement of a collection period during a power outage so that the contents of said register are representative of a demand interval and then storing the contents of said index register and associated data words representative of received event data in s.M primary storage locations only for those demand intervals during which event data is detected.

z i 7i e li 17 GB 2 136 613 A 17 8. The method of claim 7 further comprising detecting the return of line power and then transferring the data words from said secondary storage locations to said solid state memory and thereafter re-formatting the data words in said primary storage locations and storing the re-formatted data words in said secondary storage locations for subsequent storage in said solid state memory means in the order in which the event data 5 was received.

9. The method of claim 8 further comprising sequentiallytransferring the index data words and data words representative of received event data in said primary storage locations to the first-occurring addresses to thereby make room in said primarystorage locations for subsequent power outages should they occur priorto a complete re-formatting of the data words in said primary storage locations.