GB2135847A - Amplifier arrangement - Google Patents

Abstract

A differential amplifier comprises two transistors (T1, T2) whose emitters are connected through respective resistors (R1, R2) to a first current source (S1). The collector circuits of the transistors (T1, T2) comprise resistors (R3, R4). The collector of one transistor (T1) is connected to a second current source (S2) and is also connected to a first transistor (T3) of a pair forming a switch the other transistor (T4) of which is connected to the collector of the other (T2) of the two transistors. A switching signal is applied to the transistor switch which changes the currents flowing through collector circuits of the two transistors (T1, T2) to change the amplitude at the output of the amplifier. <IMAGE>

Description

SPECIFICATION Amplifier arrangement The invention relates to an amplifier arrangement comprising first and second transistors coupled to form a differential amplifier with the emitters of said transistors being conected to a first current source, the collectors of said first and second transistors being respectively connected to first and second collector loads, the currents through said first and second transistors from said first current source being determined by an input signal applied between the bases of said transistors.

Such amplifier arrangements are well known and are used to amplify the difference between the components of a signal applied between the bases of the transistors. The currents in the collector loads of the transistors are however set by the current conveyed by each transistor.

It is an object of the invention to provide an amplifier of the type described in the opening paragraph in which the current in the collector loads can be changed.

The invention provides an amplifier arrangement comprising first and second transistors coupled to form a differential amplifier with the emitters of said transistors being connected to a first current source, the collectors of said first and second transistors being respectively connected to first and second collector loads, the currents through said first and second transistors from said first current source being determined by an input signal applied between the bases of said transistors, characterised in that said first collector load is also connected to a second current source whilst a switching circuit, in response to a switching signal, connects a third current source either to said first collector load or to said second collector load in such manner that when said switching circuit occupies a first switching position the current through said first collector load is determined by the currents through said first transistor from said second current source and the current though said second collector load is determined by the currents through said second transistor and from said third current source whilst when said switching circuit occupies a second switching position the current through said first collector load is determined by the currents through said first transistor and from the second and third current sources and the current through said second collector load is determined by that through said second transistor whereby the d.c. component in the output from the differential amplifier changes with the switching signal.

The switching circuit may comprise third and fourth transistors whose emitters are connected to the third current source whilst their collectors are respectively connected to the first and second collector loads, the switching signals being applied between the bases of said third and fourth transistors. This switching circuit may however additionally comprise fifth and sixth transistors whose emitters are connected to the second current source and whose collectors are both connected to the first collector load, the bases of the fifth and sixth transistors being respectively connected to the bases of the third and fourth transistors.The first collector load will then be connected via the fifth or the sixth transistor to the second current source, the voltage drop across a conducting transistor always being present between each collector load and its associated current source or sources.

The second and third current sources may each comprise a further transistor the base of which is coupled to the input signal such that changes therein produce a corresponding change in the current of the second and third current source.

The above and other features of the invention will now be described by way of example with reference to the accompanying drawing in which: Figure lisa circuit diagram of an amplifier arrangement according to the invention, and Figure 2 is a circuit diagram of a modification of the amplifier arrangement of Figure 1.

Figure 1 shows an amplifier arrangement with a differential amplifier having transistors Ti, T2 whose emitters are connected through equal value resistors R1, R2 to a current source S1. The collectors of transistors T1 and T2 are respectively connected through collector load resistors R3 and R4 to a terminal 1 which is connected to the positive terminal of a supply and whose negative terminal is connected through a terminal 2 to the side of current source S1 remoter from resistors R1 and R2. The bases of transistors T1 and T2 are respectively connected to signal input terminals 3 and 4 to which a signal to be amplified is applied.In one particular application terminals 3 and 4 may respectively receive the zero level of chrominance reference and the black level reference present in a received C-MAC television signal as disclosed in the Independent Broadcasting Authority's Experimental and Development Report 118/82 "MAC - A Television System for High-Quality Satellite Broadcasting", August 1982 - see especially Figure 11 and accompanying text. The voltage difference between these two references is nominally 0.5 volt which is to be amplified to produce at output terminals 5 and 6 references which differ successively by the maximum amplitude of the compressed chrominance component (1.3 volt peak-to-peak) and the maximum amplitude of the compressed luminance component (1 volt peak-to-peak) for use within a signal demodulator.The applied difference signal determines the relative proportions of the current from the current source S1 which flow through transistors T1 and T2 to their collector loads.

The collector of transistors T1 and T2 are respectively connected to the output terminals 5 and 6 whilst the collector of transistor T1 is also connected to a second current source S2 whose other side is connected to the terminal 2. Current from the second current source S2 therefore also flows through resistor R3 in addition to the current through transistors T1 . The collectors of transistors T1 and T2 are additionally connected to the respective collectors of transistors T3 and T4 whose commoned emitters are connected to a third current source S3 whose other side is connected to terminal 2.Transistors T3 and T4 function as a switch in response to a switching signal applied between terminals 7 and 8 such that the current from source S3 appears at the collector of one or other of these transistors.

When used with a MAC television signal transistor T3 may be arranged to conduct in the presence during each line period of the compressed chrominance component whilst transistor T4 will conduct during the remaining portions of each line period in response to the switching signal. With transistor T4 conducting and with the cu rrent from sou rce S1 divided such that cu rrent il' flows throug h transistor T1 and current il" flows through transistor T2 due to the input signal then current (il' + i2) will flow through load resistor R3 whilst (i" + i3) will flow though load resistor R4 where i2 and i3 are respectively the currents from sources S2 and S3.

When transistor T4 is rendered non-conducting and transistor T3 is conducting then the currents (il' + i2 + i3) will flow through resistor R3 whilst that through resistor R4 will be i". If resistors R3 and R4 have the same value of R ohms and currents i2 and 3 have the same magnitude i then the voltage difference V' between output terminals 5 and 6 with transistor T4 conducting will be: V' = (i1, + i)R - (it" + i)R V' = (ir - i1,,)R (1) whilst the voltage difference V" between these terminals with transistor T3 conducting will be:: V" = (i,' + 2i)R - i,"R V" = (i1, - i1')R + 2 iR (2) From (1) and (2) the relationship between the outputs for the two conducting conditions of transistors T3 and T4 can be found such that: V" = (ia - il")R + 2 iR V' (i1, - i1,,)R V" ~ 1 2i V - (i, i1,,) and from which the relative current values can be found for a desired change at the output. For the described application with MAC television signals 2iR will correspond to 0.3 volts.

Figure 2 shows a modification of the arrangement of Figure 1 and in which corresponding components have been given the same references. The collector of transistor T1 is connected to current source S2 (formed by a transistor) through two further transistors T5 and T6 switched from terminals 7 and 8 in synchronism with transistors T3 and T4. In this way the same voltage will be defined for the collector of the transistor forming the current source S2 as will that for the collector of a transistor forming the current source S3, this voltage being Vbe below the switching voltage.The input signal at terminals 3 and 4 is also applied to the bases of respective transistors T7 and T8 forming a further differential amplifier, the emitters of these transistors being connected through respective resistors R5 and R6 to a current source S4 whose other side is connected to the terminal 2. The collector load for transistors T7 and T8 is formed by a current mirror circuit comprising pnp transistors T9, T10 and Tri 1 with the collector of transistor T8 being connected to a second current mirror comprising pnp transistors T1 2, T13 and T14. The mirrored current from the collector of transistor T14 is connected to an inverting current mirror comprising transistors T15 and T16 which are of the npn type as are the remaining transistors in the Figures. The arrangement of the differential amplifier T7, T8 and its associated current mirrors is such as to increase the current from the current source transistors S2 and S3 in the event that the input difference signal increases to proportionally change the voltage at the output terminals 5 and 6. To this end the emitter of transistor T16 is connected to the bases of the current source transistors S2 and S3.

Claims (5)

1. An amplifier arrangement comprising first and second transistors coupled to form a differential amplifier with the emitter of said transistors being connected to a first current source, the collectors of said first and second transistors being respectively connected to first and second collector loads, the currents through said first and second transistors from said first current source being determined by an input signal applied between the bases of said transistors, characterised in that said first collector load is also connected to a second current source whilst a switching circuit, in response to a switching signal, connects a third current source either to said first collector load or to said second collector load in such manner that when said switching circuit occupies a first switching position the current through said first collector load is determined by the currents through said first transistor and from said second current source and the current through said second collector load is determined by the currents through said second transistor and from said third current source whilst when said switching circuit occupies a second switching position the current through said first collector load is determined by the currents through said first transistor and from the second and third current sources and the current through said second collector load is determined by that through said second transistor whereby the d.c. component in the output from the differential amplifier changes with the switching signal.

2. An amplifier arrangement as claimed in Claim 1, characterised in that said switching circuit comprises third and fourth transistors whose emitters are connected to said third current source whilst their collectors are respectively connected to the first and second collector loads, the switching signal being applied between the bases of said third and fourth transistors.

3. An amplifier arrangement as claimed in Claim 2, characterised in that said switching circuit additionally comprises fifth and sixth transistors whose emitters are connected to the second current source and whose collectors are both connected to said first collector load, the bases of said fifth and sixth transistors being respectively connected to the bases of said third and fourth transistors.

4. An amplifier arrangement as claimed in Claim 1,2 or 3, characterised in that said second and third current sources each comprise a further transistor the base of which is coupled to the input signal such that changes therein produce a corresponding change in the current of the second and third current sources.

5. An amplifier arrangement substantially as herein described with reference to the accompanying drawing.