GB2135551A - Optical receivers - Google Patents

Abstract

In a PIN-FET optical receiver for digital transmission the reverse bias on the PIN photodiode 11 is shifted with increasing incident optical intensity towards and into the non- linear region of the PIN photodiode operating characteristics. This is conveniently achieved by a resistor/capacitor parallel circuit (22, 23) connected in series with the PIN photodiode resister series circuit (15) of the photodetector circuit. This bias shift increases the dynamic range of the photo detector circuit. <IMAGE>

Description

SPECIFICATION Optical receivers This invention relates to optical receivers and in particular to optical receivers employing PIN FET photo detector circuits.

Optical receivers are commonly used in optical fibre communications to receive and convert the incident optical signals into corresponding electrical signals which can then be processed by electronic circuits.

In a conventional optical receiver employing a PIN-FET photo detector circuit, the photo detector circuit comprises a PIN photo-diode detector and a high value bias resistor connected in series, and a field effect transistor, wherein the outer terminals of the detector circuit are connected to a power supply, and the node between the diode and the resistor is connected to the gate of the field effect transistor (FET).Alternatively, instead of being connected to a voltage rail of the power supply, the outer terminal of the bias resistor may be connected to a control circuit which applied to the bias resistor a feedback voltage proportional to the mean photo current so as to maintain a mean voltage at the gate of the FET at a defined value, for example OV, (see, e.g., Electronics Letters Vol. 16, No. 2, January 17th 1980, pp. 69 to 71, "PIN/FET" Hybrid Optical Receiver for Longer Wavelength Optical Communication System", D. R. Smith et al). Amplifying and signal processing circuits are provided as necessary downstream of the FET.

One of the disadvantages of conventional optical receivers having PIN-FET detector circuit is the rather limited dynamic range of the detector circuit of not more than about 20db, even with the aforementioned feedback arrangement. This limited dynamic range presents comparatively little difficulty in permanent installations, in which the optical fibre between transmitter and receiver is of a fixed length so that the incident optical signal is always within a well defined range.

However, in some systems applications, e.g.

mobile systems, data bus systems, etc., a much higher dynamic range may be required, since the transmitter and receiver may be connected at various times by fibre links of widely different lengths. In such circumstances it is difficult to ensure that, for a given transmitter power, the dynamic range of the PIN-FET detector circuit is not exceeded. Thus, while the sensitivity of the detector circuit must be sufficiently great to give reliable operation even at the longest envisaged distance between transmitter and receiver, the detector circuit must also operate satisfactorily at very short distances, when there is little attenuation of the optical signal in the fibre so that the received optical signal is of much greater intensity.

One solution to the problem of extending the dynamic range of a photo detector with a photo diode has been proposed in an article by V. A.

Druchevskii et al., "Extension of dynamic range of a photoreceiver based on a photo diode", in "Instruments and Experimental Techniques", Vol.

23, No. 3, part 2, May-June 1980, pp. 758- 760. The circuit described in this article increases the dynamic range of a photo diode detector by supplying the bias voltage to the photo diode from the output of an operation amplifier downstream of the photo diode, the bias voltage being varied once the output voltage of the operational amplifier exceeds a preset threshold level.

According to the present invention in a highimpedance integrating photo detector circuit, having a photo diode of which one terminal is a common terminal with an input to first amplifying means and with a biassing circuit arranged to cause the photo diode to operate in a substantially linear region of its operating characteristics, the photo diode is connected to a voltage supply rail by an impedance in series with and connected to the other terminal of the photo diode, the impedance being of a sufficiently high value to cause the operating point of the photo diode to shift with increasing photo diode current towards and into the non-linear operating region of the photo diode.

This signal strength dependent shift of the operating point may conveniently be achieved with an impedance comprising a high value resistor and a decoupling capacitor, connected as aforesaid in series with the photo diode.

The signal strength dependent shift of the operating point leaves sensitivity at low optical signal levels nearly unaffected, while at higher signal levels, the shift progressively reduces sensitivity and thereby extends the upper limit of the dynamic range.

As is well known, PIN-FET receivers normally operate with the light detecting diode being reverse biased, but it has been found that for digital systems satisfactory signal detection at high signal levels can be obtained even if the operating point has been shifted into the forward bias region of the detector diode.

The invention shall now be described further by way of example only and with reference to the accompanying drawings of which: Figure 1 is a circuit diagram of a conventional PIN-FET photo detector circuit; Figure 2 is a circuit diagram of a photo detector circuit according to the present invention; and Figure 3 shows the operating characteristics of a PIN-FET photo diode as a function of bias voltage.

Referring first to Figure 1, a conventional prior art PIN-FET photo detector circuit 10 comprises a series circuit 1 5 of a PIN diode 11 and a resistor 12, and a field effect transistor (FET) 1 3 whose gate electrode is connected to the node 1 4 between the resistor 1 2 and the diode 1. The outer terminals 16 and 18 of the series circuit 1 5 are connected respectively to the positive voltage rail 1 7 and the negative or grounded voltage bias is applied to the diode 11.The outer terminals 1 6 and 18 of the series circuit 15 are connected respectively to the positive voltage rail 17 and the negative or grounded voltage rail 1 9 of a power supply, the polarity being such that a reverse bias is applied to the diode 11. Typically, the voltage on voltage rail 17 is about 10 V.

To avoid saturation of the FET 13 at high signal levels, the terminal 18, instead of being connected to the voltage rail 19, may be connected to D.C. feedback arrangement which maintains the mean voltage at the gate of the FET 13 at approximately 0 V by applying to terminal 1 8 a negative D.C. feedback voltage proportional to the mean photocurrent through the PIN diode 11. The feedback arrangement (not shown) supplies the feedback voltage along the line 1 9a (shown dashed) which then replaces the voltage rail 1 9 for the voltage supply to the bias resistor 12. The maximum feedback voltage is normally about 5 V.The bias resistor 12 is normally in the region of 1-10 mQ. The photo diode may, for example, be an InGaAs PIN diode of the kind described by D. R. Smith et al in Electronics Letters of May 27th, 1 982, Vol. 1 8, No. 11, pp.

453-454 under the title "Experimental Comparison of a Germanium Avalanche Photodiode and InGaAs PIN-FET Receiver for Longer Wavelength Optical Communication Systems".

The operation of the photo detector circuit 10 will be described below with reference to Figure 3.

Referring now to Figure 2, the photo detector circuit 20 is in many respects similar to the circuit 10 of Figure 1, comprising a series circuit 1 5 of a PIN photo diode 11 and a bias resistor 12, and a FET 1 3 whose gate is connected to the node 14.

Additionally, however, the circuit 20 includes a resistor 22 and a decoupling capacitor 23 connected in parallel between the outer terminal 15 of the series circuit 1 5, and the positive voltage rail 1 7.

Figure 3 illustrates the dependency of current flow through the PIN photo diode 11 of Figures 1 and 2 on bias voltage and incident optical power.

In the Figure, curve 3a represents the leakage current, curves 3b to 3h the current-bias voltage relationship for a stepwise increase Ap in the optical power, and curves 3i and 3j respectively the operation of the circuit 10 and 20.

Referring now also to Figure 1, it is assumed that the bias voltage applied to the PIN photodiode 11 is 10 V. As the optical power incident on the PIN photodiode 11 is increased in successive steps of Ap, the current I flow through the diode 11 also increases substantially linearly, as can be seen from curve 3i, until a maximum current is reached corresponding to curve 3h, at which the maximum feedback voltage is applied to 19a. In general for any bias voltage more negative than -lV, say, light incident on the diode 11 causes a current flow proportional to the intensity of the light incident, so that variations in the intensity of the incident light generate a corresponding electrical signal appearing at node 14.The electrical signal at node 14 controls current flow through the field effect transistor 13, whose output will normally be further amplified in conventional amplifier circuitry (not shown).

Referring now to Figures 2 and 3, the effect of the resistor 22 is a gradual reduction in the bias voltage applied to the PIN photodiode 11 as indicated by curve 3j. For small incident optical power, the bias votlage is nearly unaffected and the current flow I through the diode 11 is still substantially linear with optical power in view of the fairly flat gradients of curves 3a to 3h at high bias voltages.

As the incident optical power increases, however, the bias voltage applied to the PIN photodiode is gradually reduced as a result of the increasing voltage drop across the resistor 22, and for high incident optical power the bias voltage becomes inverted so that the PIN diode 11 operates in forward bias. The current no longer varies linearly with incident optical power and increases much less for a given step increase Ap than for low intensity optical signals, thereby extending the upper limit of the dynamic range.

The effects of the gradual reduction of reverse bias and forward biasing of the diode 11 are to cause an increase in the generated noise and a reduction in the quantum efficiency of the diode 11 It has been found that, nevertheless, satisfactory reception of digital signals results even under forward bias condition, because an acceptable signal to noise ratio is still maintained.

In tests at 140 Mbit/s the prior art circuit 10 of Figure 1 operated satisfactorily, that is with a bit error rate (b.e.r.) of less than 10-9 between46 dBm and -26 dBm, while the circuit 20 of Figure 2 operated over a range of between46 dBm and more than 0 dBm with a b.e.r. of 10-9 or better.

The circuit 20 of Figure 2 may also include a feedback arrangement as described above in relation to Figure 1. Unlike the case of Figure 1, the range of feedback bias voltages supplied via line 1 9a has to be limited, to between 0 and -2 V for example, because the effect of the increasingly negative bias voltage is to counteract the effect of the resistor 22. This leads to a steeper gradient of the curve 3j, as indicated by the steeper portion of the curve 3j to the right of its intersection with curve 3b. Thus the limitation of the range of feedback bias voltage is required to ensure that the bias voltage is sufficiently reduced at high incident optical power to cause the diode to operate in its non-linear region.

Claims (8)

1. A photodetector circuit comprising a high impedance integrating photodetector having a photo diode of which one terminal is a common terminal with an input to first amplifying means and with a biasing circuit arranged to cause the photo diode to operate in a substantially linear region of its operating characteristics, wherein the photodiode is connected to a voltage supply rail by an impedance in series with and connected to the other terminal of the photo diode, the impedance being of a sufficiently high value to cause the operating point of the photo diode to shift with increasing photo diode current towards and into the non-linear operating region of the photo diode.

2. A circuit as claimed in claim 1 wherein the impedance comprises a high value resistance and a capacitance in parallel.

3. A circuit as claimed in claim 1 or claim 2 wherein the biasing circuit comprises a resistance of the order of 10 MQ and the high impedance has a resistive component of the order of 50 MQ.

4. A circuit as claimed in any preceding claim wherein the photo diode is a PIN photo diode.

5. A circuit as claimed in any one of claims 1 to 4 in which the photo detector comprises a PIN FET photo detector.

6. An optical receiver comprising a photo detector circuit as claimed in any preceding claim.

7. A digital optical transmission system including an optical receiver as claimed in claim 6.

8. A photo detector circuit substantially as hereinbefore described with reference to and as illustrated by Figures 2 and 3 of the accompanying drawings.