GB2132430A

GB2132430A - Phase locked loop circuit

Info

Publication number: GB2132430A
Application number: GB08330193A
Authority: GB
Inventors: Hiroyuki Sigiyama; Yoshiaki Amano; Yuichi Koseki; Mitsuyoshi Yamashita
Original assignee: Victor Company of Japan Ltd; Nippon Victor KK
Current assignee: Victor Company of Japan Ltd; Nippon Victor KK
Priority date: 1982-11-12
Filing date: 1983-11-11
Publication date: 1984-07-04
Also published as: DE3340969A1; GB8330193D0; FR2536226A1; JPS5989038A; FR2536226B1

Abstract

A phase locked loop circuit is disclosed which is usable for processing a reproduced digital signal in a digital audio and video system. In addition to a phase detector (12), a low-pass filter (14) and a voltage controlled oscillator (16), the phase locked loop includes frequency detectors (20, 22) for respectively detecting an increase of the output oscillation frequency of the voltage controlled oscillator beyond a predetermined upper limit and a decrease thereof below a predetermined lower limit, in which case control signals are generated to maintain the output frequency between the said limits. Output frequency drift to those limits is envisaged during periods of input signal dropout and faster reacquisition is enabled by the prevention of drift in the phase lock loop. <IMAGE>

Description

SPECIFICATION Phase locked loop circuit Background of the invention The present invention relates to a reproduced digital signal processing apparatus for use with a digital audio and video system. More particularly, the present invention relates to an improved phase locked loop (PLL) circuit usable for reading and reproducing digital audio and video signals which are recorded as pits in a disc.

We have proposed a system for subjecting an analog video signal to digital pulse modulation to generate a digital video signal as pixel data which individually correspond to pixels of a picture arranged in a form of matrix, the video signal being written into a disc. In this system, the digital video signal for representing a series of color still picture in the reproduction is written in addition to the digital audio signal into a same track on the disc as a train of pits.

Meanwhile, the pit train on the disc is detected as, for example, a variation in electrostatic capacity to read the recorded signal and play it back. The reproduced video signal is FM (frequency modulation) demodulated by an FM demodulator, locked in phase by a PLL circuit, and then allowed for MFM (modified frequency modulation) demodulation. In phase-locking with a PLL circuit, it has been customary to supply an input signal to a phase detector, supply an output of the phase detector to a voltage controlled oscillator via a low-pass filter, and control an output oscillation frequency of the oscillator such that the phase of the oscillator output always coincides with that of the input signal.A problem encountered with such a PLL circuit is that, once the input signal is lost for a certain period of time due to signal dropout or the like, the output oscillation frequency of the oscillator deviates and falls out of a predetermined frequency range.

This causes the oscillator requiring a significant amount of time to bring the deviated output oscillation frequency back into the predetermined range when the input signal is restored.

Summary of the invention It is therefore an object of the present invention to provide an improved PLL circuit which maintains the output oscillation frequency of the voltage controlled oscillator within a certain frequency range during the absence of an input signal due to dropout or the like, so that it may be quickly confined into the predetermined range in response to restoration of the input signal.

A phase locked loop circuit for processinga reproduced digital signal of the present invention comprises a phase detector responsive to the reproduced digital signal for producing a difference signal a low-pass filter for converting the difference signal into a DC voltage signal, a voltage controlled oscillator for generating an output signal having an oscillation frequency which corresponds to the DC voltage signal, the output signal being fed to the phase detector and compared with the reproduced digital signal in phase, and a control circuit for controlling a level of the DC voltage signal fed to the voltage controlled oscillator such that, while the voltage controlled oscillator is in a free-run condition, the oscillation frequency of the output signal thereof being held between a predetermined upper frequency limit and a predeermined lower frequency limit.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings.

Brief description of the drawings Figure 1 is a block diagram of a PLL circuit embodying the present invention; Figure 2 is a diagram of an example of an essential part of the PLL circuit shown in Figure 1; and Figure 3 is a diagram showing waveforms which appear in various portions of the circuitry of Figure 2.

Description of the preferred embodiment While the PLL circuit of the present invention is susceptible of numerous physical embodiments, depending upon the environment and requirements of use, a substantial number of the herein shown and described embodiment have been made, tested, and used, and all have performed in an eminently satisfactory manner.

Referring to Figure 1, a PLL circuit in accordance with the present invention has an input terminal 10 to which is supplied a synchronizing signal component SIN (the center frequency of which is 5.733 MHz) derived from a digital video signal. From the input terminal 10 the signal comonent SIN is fed to a phase detector 1 2 the output of which is delivered to a low-pass filter 14 to be converted thereby into a DC voltage signal SDCV which is then delivered to a voltage controlled oscillator (VCO) 1 6. A signal So5c whose frequency corresponds to the signal SDCV appears at an output terminal of the VCO 1 6. The output oscillation frequency of the VCO 1 6 is preselected to be several times the frequency of the input signal.The VCO output So5c is routed to the phase detector 1 2. The output oscillation frequency of the VCO 16 is controlled such that the output signal So5c of the VCO 1 6 coincides in phase with that of the input signal SIN.

A characteristic feature of the present invention resides in the provision of unique frequency detectors 20 and 22 which are individually supplied with an output signal So5c of the VCO 1 6 to detect its output oscillation frequency. The frequency f1 which the frequency detector 20 is capable of detecting is predetermined to be higher than the upper limit of the VCO output oscillation frequency which is susceptive to jitter components possibly introduced into the input signal during playback, e.g. 5.915 MHz. The frequency f2 assigned to the other frequency detector 22 is predetermined to be lower than the lower limit of the VCO output oscillation frequency, e.g. 5.551 MHz.

When the input signal SIN has been lost for a given period of time due to dropout or the like, the VCO 1 6 is caused into the free-run state. If the VCO output of that instant is higher than the frequency f1, it is detected by the frequency detector 20 and the resulting output signal SULF is fed to a voltage controlled current source 24 to cause that the potential at a junction A increases.

If the VCO output oscillation frequency is lower than the frequency f2 it is detected by the other frequency detector 22 and the output signal SLLF of the detector 22 is fed to a voltage controlled current source 25 to cause lowering the potential at the junction A. The voltage controlled current source 24 or 26 is a type of voltage-to-current converter which produces a current output responsive to a supplied input voltage. Each of the frequency detectors 20 and 22 is supplied with clock pulses (sampling frequency) CK, from a master clock generator 28. The frequency of the clock pulses may be 44.1 kHz, for example.

Therefore, the frequency detectors 20 and 22 individually count output pulses of the VCO 16 in response to every clock pulse CK1, thereby detecting a VCO output oscillation frequency.

The control over the potential at the junction A performed in the above-described manner allows the output oscillation frequency of the VCO 16 to remain within the frequency range of f1-f2 even if the input signal is lost for a moment. On the restoration of the input signal, the VCO 1 6 resumes developing an output signal the frequency of which corresponds to the input voltage.

Referring to Figures 2 and 3, a practical example of the coactive frequency detectors 20 and 22 will be described in detail. The output osc of the VCO 1 6 (the center frequency of which is 5.733 MHz) is fed to clock terminals of presettable 8-bit counters 30 and 32 as well as to clock terminals of D-type flip-flops 34 and 36.

The clock pulses CK, from the master clock generator 28 (having a repetition frequency of 44.1 kHz and a duty factor of 63 63+67 are applied to a D terminal of the flip-flop 34. The output 5osc of the VCO 1 6, which is applied to the clock terminal of the flip-flop 34 as described, strobes the clock pulses CK1 so that a signal a appears at a 0 output terminal of the flip-flop 34 with a waveform which is substantially identical with that of the clock signal Cm" as shown in Figure 3. Appearing at a Q output terminal of the flip-flop 36, which is connected in series with the flip-flop 34, is a signal b prepared by inverting a signal which is delayed by one period of the signal Ssoc relative to the signal a.Therefore, an output signal c of a NAND gate 38 becomes low level only when both the signals a and b are high level, that is, during a buildup of the signal a, while remaining high level for the other period, as shown in Figure 3.

The signal c is applied to load terminals LD of the counters 30 and 32 to cause them into a loading mode operation for its low level period. In the loading mode, the counters 30 and 32 respectively preset data at their data input terminals A-H (binary "10111111" and " 11000011 " or decimal " 191 " and " 195") in response to clock pulses Sosc which arrive thereat for that while. As soon as such input data are loaded, the signal c at the load terminals LD becomes high level to turn the operating mode of the counters 30 and 32 into a counting mode.At this instant, because the signal a fed to enable terminals EN of the counters 30 and 32 via AND gates 40 and 42 has already been made high level, the counters 30 and 32, individually start counting pulses So5c from one next to the one used for loading purpose. The operation of the counters 30 and 32 continue until their content reaches the maximum value (decimal "255") or until the signal a becomes low level.

When the counters 30 and 32 have individually reached the maximum count while the signal a is high level, high level signals develop at their carry output terminals CA to make the enable terminals EN low level via the AND gates 40 and 42 respectively. This deactivates the counters 30 and 32 while maintaining the maximum value in the counters 30 and 32 and, therefore, maintaining the carry output terminals CA high level.

The carry output terminal CA of each of the counters 30 and 32 is made high level or low level depending respectively upon whether or not the associated counter has reached the maximum "255", that is, whether or not at least 255191 +1 =65 pulses or 266-1 95+1=61 pulses have arrived at the counter ("+1" indicating the pulse used for loading). Such a state of the counter 30 or 32 is respectively latched by a D-type flip-flop 48 or 50 responsive to a signal g, which will be described.

The clock pulses CK, from the master clock generator 28 is also routed to a D terminal of a Dtype flip-flop 52. Strobed by clock pulses CK2 having a constant frequency of 6.1 74 MHz, the clock pulses CK, appear as a signal data Q output terminal of the flip-flop 52 which has a waveform substantially identical with that of the clock pulses CK,, as shown in Figure 3. The inverted version e of the signal d develops at a Q output terminal of the flip-flop 52. Appearing at a Q output terminal of a D-type flip-flop 54 is a signal fwhich is delayed by one period of 6.174 MHz relative to the signal d. As a result, an AND gate 56 produces at its output terminal a signal g which turns into low level when both the signals e and fare high level, that is, at the trailing edge of the signal d. The signal g is fed to flip-flops 48 and 59 as a latch signal.

If 65 or more pulses So5c from the VCO 1 6 are counted while the signal a is high level, that is, during a period of 63 1 x 63+67 44.1 kHz (because the duty factor is 63 63+67 the carry output terminal CA of the counter 30 will have become high level. This status of the CA terminal is latched by the flip-flop 48 and then output as a signal Su,Ffrom a 0 output terminal thereof. The upper frequency limit f1 is produced as follows: 65 63 1 + f, 63+67 44.1 kHz therefore, f,=5.915 MHz Concerning the counter 32, its CA terminal output remains low level unless 61 pulses Sosc are counted while the signal a is high level. This is latched by the flip-flop 50.As a result, a high level signal SL.F develops at a 0 output of the flip-flop 50. The lower frequency limit f2 is produced as follows: 61 63 1 = x f2 63+67 44.1 kHz therefore, f2=5.551 MHz While the counters 30 and 32 have been shown and described as comprising presettable 8-bit counters, use may be made of a series connection of a pair of ordinary general-purpose 4-bit counters.

In summary, it will be seen that the present invention provides a PLL circuit which confines a VCO output oscillation frequency to between predetermined upper and lower frequency limits despite absence of an input signal due to dropout or the like. This will bring the VCO output oscillation frequency back to the predetermined value within a short period of time as soon as the input signal is restored. The operation is free from the influence of fluctuation in the VCO output oscillation frequency which might result from temperature variation. All these advantages, as well as others, are attainable by detecting an increase of the VCO output oscillation frequency beyond the upper limit or a decrease thereof beyond the lower limit each in the free-run condition of the VCO, and controlling the VCO input voltage level with the detection output to hold the VCO output oscillation frequency within the range between the upper and lower limits in the free-run condition.

Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims

1. A phase locked loop circuit for processing a reproduced digital signal, comprising: a phase comparator detector responsive to the reproduced digital signal for producing a difference signal; a low-pass filter for converting the difference signal into a DC voltage signal; a voltage controlled oscillator for generating an output signal having an oscillation frequency which corresponds to the DC voltage signal, said output signal being fed to the phase comparator detector and compared with the reproduced digital signal in phase; and control means for controlling a level of the DC voltage signal fed to the voltage controlled oscillator such that, while the voltage controlled oscillator is in a free-run condition, the oscillation frequency of the output signal thereof being held between a predetermined upper frequency limit and a predetermined lower frequency limit.

2. A phase locked loop circuit as cliamed in claim 1, in which the control means comprises a first frequency detector for generating an upper frequency limit detection signal on detection of an increase of the output oscillation frequency of the voltage controlled oscillator beyond the upper frequency limit while the voltage controlled oscillator is in the free-run condition, and a second frequency detector for generating a lower frequency limit detection signal on detection of a decrease in the output oscillation frequency of the voltage controlled oscillator beyond the lower frequency limit while the voltage controlled oscillator is in the free-run condition.

3. A phase locked loop circuit as claimed in claim 2, in which the control means further comprises a first voltage controlled current source and a second voltage controlled current source for increasing and decreasing a level of the DC voltage signal output from the low-pass filter in response to the upper and lower frequency limit detection signals, respectively.

4. A phase locked loop circuit as claimed in claim 1, in which the upper frequency limit is 5.915 MHz and the lower frequency limit is 5.551 MHz.

5. A phase locked loop circuit as claimed in claim 1, in which the output oscillation frequency of the voltage controlled oscillator is several times a frequency of the DC voltage signal output from the low-pass filter.

6. A circuit for receiving and processing an input signal, the circuit including: an oscillator; means for automatically controlling the output frequency of said oscillator in a manner dependent upon the input signal; and means for inhibiting deviation of said output frequency from predetermined conditions.

7. A phase locked loop circuit substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

8. A phase locked loop circuit substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.