GB2104669A

GB2104669A - Apparatus for testing electronic devices

Info

Publication number: GB2104669A
Application number: GB08221619A
Authority: GB
Inventors: John Paul King; Sadrudin Gulamhusein Nanji; Derek John Painter
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1981-08-06
Filing date: 1982-07-27
Publication date: 1983-03-09
Also published as: AU8690682A; FR2511216A1; FR2511216B1; ZA825430B

Abstract

Apparatus for testing electronic device (1) includes an interconnection means (3, 4) for interconnecting the device (1) to be tested to power and common supply means and means (2) for generating test logic signals for application to the device (1) and for receiving and evaluating result logic signals from the device (1); the interconnection means comprising at least in part a multilayer printed circuit board (3) of which one layer contains a connection for power or common voltage supply comprising a region of conductive material of substantial extent. <IMAGE>

Description

SPECIFICATION Improvements in or relating to apparatus for testing electronic devices Background of the invention Field of the invention This invention relates to apparatus for testing electronic devices such as integrated circuits.

The prior art In a known system for testing integrated-circuit devices the device is subjected to the same sort of conditions as it experiences in use. Power is supplied to the device and then a predetermined sequence of test logic signals is applied to the various input leads of the device. The resultant logic signals produced by the device on its output leads are examined to determine if the device is functioning correctly. The power supply for the device, and the equipment which produces the test logic signals for the device and evaluates the resultant output logic signals from it, are connected to the device through a pair of printedcircuit boards.

The first of these boards, which will be referred to herein as the "load board", imposes on the output leads of the device loads representative of those they would experience in use. Since the loads experienced vary from one type of circuit technology (MOS, ECL, TTL etc.) to another, devices using different types of circuit technology will usually require different load boards.

However, at any rate for simpler devices, it is possible for a family of devices of the same type to use a common load board.

Even within a family of devices of a given circuit type, the functions assigned to the various leads of the devices may vary from one device to another. So the load board is in turn connected to the second of the two printed circuit boards referred to above, which will be termed herein a "device-under-test" board. The device-under-test board contains links, usually hand-wired between predetermined positions on the board and the appropriate leads of a socket which will take the device concerned. There are therefore usually a number of different device-under-test boards for use with a given load board.

It is found that this interconnection system in its known form does not allow devices, especially high-speed devices, to be tested as accurately as may be desired.

Summaries of the invention This invention provides a system for testing electronic devices by applying to a device to be tested power and voltage, such as will subject the device to operational conditions similar to those likely to be expected in use, the system comprising circuit interconnection means for interconnecting with the device power and common voltage supply means, means for generating the test signals for the device under test and means for receiving and evaluating the output signals from the device under test, which interconnection means comprises at least in part a multilayer printed circuit board including at least one layer which provides a connection for a power or common voltage supply and which includes a region of conductive material of substantial extent.

We have found that such a system is capable of performing more accurately than the known system described above, in which both the load board and the device-under-test board are double-sided at most and make their connections for the power and common voltages entirely by tracks of limited width. We attribute this improvement to the smaller resistance of the conductive path provided by the conductive region of substantial extent, which, we believe reduced the variations in the power/common voltages applied to the device that occur when the device switches state.

The invention also provides a printed-circuit board for use as part at least of the interconnection means in a system for testing electronic devices, which system comprises power and common supply means, means for generating test logic signals for application to the device and for receiving and evaluating result logic signals from the device, which board is a multilayer printed circuit board one layer of which contains a connection for a power or common voltage comprising a region of conductive material of substantial extent.

The board may be for use either as a load board or as a device-under-test board. Preferably both such boards are multilayer boards as specified.

Preferably the multilayer board contains a layer of conductive material of substantial extent for connection to ground and interposed between, on the one side, the layer containing the said region of substantial extent, forming a power or common connection and, on the other side, printed-circuit tracks and/or positions for discrete wiring links which tracks or links are for providing connections for the logic signals.

If the board is for use as a load board preferably there is a further layer of conductive material of substantial extent for connection to ground on the side of the layer containing the said region of substantial extent forming a power or common connection remote from the firstmentioned such layer. The board may then also contain, between two such layers, at least one layer containing control tracks for switching means for load components.

Brief description of the drawings An example of a system in accordance with the invention will now be described in greater detail by way of illustration with reference to the accompanying drawings, in which Figure 1 is an outline view of the system; Figures 2a and 2b are circuit diagrams of the conductive paths for power and logic signals respectively; Figure 3 is a cross-sectional diagram of the structure of the load board; Figures 4a, b, c and dare diagrams of the patterns of various conductive layers of the load board; Figure 5 is a cross-sectional diagram of the structure of the device-under-test board; and Figures 6a to c are diagrams of the patterns of various conductive layers of the device-under-test board.

Description of the preferred embodiments Referring to Figure 1, the system is used to test an electronic device 1 such as an integrated circuit.

Fixed equipment 2 contains the power supply for the device, and also equipment, commonly known as the "pin electronics", which generates test logic signals for application to the device . The pin electronics also receives the output signals produced by the device 1 under test and carries out the required evaluations to determine if the device is functioning correctly. Normally it will not only detect a gross fault in the device which would prevent its functioning at all but also classify the device according to the closeness of its adherence to specification.

The fixed equipment 2 is connected to the device 1 under test via an interconnection system the principal components of which are a load board 3 and a device-under-test (DUT) board 4.

The load board 3 has a central circular aperture and, concentric with the aperture, a ring of connectors 5 for the pin electronics. Other connections between the fixed equipment 2 and the load board 3 are made by edge connectors 6 mounted on the load board 3. The load board 3 carries components such as relays 7, resistors 8, and capacitors 9 used to construct the required loads for the output pins of the device 1.

The load board 3 is electrically connected to the DUT board 4 by an inner ring 10 and an outer ring 11 each of plastics material and carrying elastomeric conductive studs 1 0a and 1 a respectively. These studs provide the connection between aligned printed-circuit pads on the load board 3 and DUT board 4. The studs are held under compression by bolts (not shown) which hold the two boards 3 and 4 together.

The DUT board carries a socket 12 in which, in use, the device 1 to be tested is mounted.

Electrical connections from the printed circuitry of the DUT board 4 to the socket 12 are made by hand-wired links 13.

The conductive path by which any one of the various power voltages is supplied to the device is as shown in Figure 2a. The tester-common voltage follows a similar path. (By tester-common is meant the voltage which is treated by the device as OV, even though it may not be OV with respect to ground). The voltage concerned enters by pins 14 of one of the edge connector 6.

The pins are soldered in plated-through holes 3A and are connected to a track 15 in an inner layer of the board. The conductive path then passes to the surface by a plated-through hole 16, along a wire link 1 7 (present for a reason to be explained subsequently) back to the inner layer by a plated through hole 18 and then via a broad region 19 of conductive material to the central area of the board, where it rises by plated-through holes 20 to a surface pad 21.

The pad 21 is connected by conductive studs 1 Oa of inner ring 10 to a matching pad 22 on the surface of the DUT board 4. From there the conductive path for the voltage concerned travels via plated-through holes 23 to a broad region 24 of conductive material in an inner layer of the DUT board 4. This region is connected to the surface by plated-through holes 25, one of which is connected by one of the wire links 13 to a platedthrough hole 26 connected by a track 27 to a plated-through hole containing a lead 28 of the socket 12. This lead is the one that needs to be supplied by the voltage concerned.

Ground is supplied to the load board 3 by pins 29 of the edge-connectors 6. The pins 29 are soldered in plated-through holes connected to three inner conductive layers, 30, 31 and 32 of the load board 3. These layers are connected via the ring 10 to an inner layer 33 of the DUT board in a similar manner to the power/common voltages. For simplicity the connections between the layers 30-32 and 33 are not shown. In the DUT board 4 the layer 33 is connected to a surface region 34, which is thus held at ground potential, to p;ated-through holes 35. The power supply to the device may be decoupled by a capacitor 36 soldered between the region 34 and a plated-through hole 37 connected to the track 27.

To allow the fixed equipment 2 to regulate the power/common supplies there is a sense line for each voltage. For the voltage whose path is shown in Figure 2a the sense line enters by a pin 38 of the edge connector 36 and is connected to the pins 14 carrying the voltage concerned by a surface track 39 on the underside. In this manner the voltage at the point of supply is sensed.

Alternatively the track 39 may be severed and replaced by a wire link to the appropriate pin of the socket 12 device to allow remote sensing of the voltage at the point of supply to the device.

The conductive paths for the various logic signals are as shown in Figure 2b. A logic signal is supplied on a lead 40 of one of the pin electronics connectors 5 and then taken by a surface track 41 to a path 42 connected by a conductive stud 11 a of the outer connector ring 11 to a matching pad 43 on the under-side of the DUT board 4. The path then travels up a plated-through hole 44 and along a surface track 45 to a plated-through hole 46 connected on the underside by one of the wire links 13 to a hole 47 connected to the appropriate pin 48 of the device 1 by a track 49.

An output signal, from, say, a pin 50 follows a similar path to a lead 51 of one of the pin electronics connectors 5. In addition the lead 51 is connected by a track 52 to a wire link 53 made to a track 54 connected to one of the relays 7.

This relay is in series with a load consisting of one of the resistors 8 connected to a surface bus ring 55 held at one of the power/common voltages by a connection down plated-through holes 56 to the appropriate conductive region 19. One of the capacitors 9 is connected between the load and a surface bus ring 60 held at ground potential by a connection down plated-through-holes 61 to the inner layers 30 to 32.

The load is shown as a resistor, but may be more complicated and may be connected to bus rings at more than one potential. The relay 7 is controlled by the pin electronics and its state may be switched during the test sequence. Thus two different load conditions may be simulated for the device pin concerned. The relay 7 also allows the testing of more complicated devices, such as microprocessors, which use some pins at different times for both input, which does not require a load, and output, which does.

The control lines for the various relays 7 are not shown in Figure 2b. Each runs from a pin of one of the edge connectors 6 along one of two inner layers to the site of the relay 7 concerned, where it is connected by a plated-through hole to a pin of the relay. The return path is along a bus ring held at a common potential.

The conductive path for each of the various power and tester-common voltages is brought to the surface at either end of the link 17. Surface access is provided to enable the power to be connected instead by wire links to one of the relays 7 controlled by the pin electronics. This allows the individual power supplies to be applied independently in testing the device.

The structure of the load board is as shown in exploded view in Figure 3. The board is assembled from four insulating sheets 62 carrying a layer of conductive material formed in the required pattern on each side. The sheets are interleaved by sheets 63 of "pre-preg" (glass fibre impregnated with partially cured epoxy resin) which, under heat and pressure, bond the stack together and insulate facing conductive layers from one another.

The eight conductive layers are: a pair of outer layers, namely an upper layer (i.e. that facing the DUT board 4) 64 and an under layer 65; the ground layers 30, 31 and 32; a pair of layers 66 and 67 which between them contain the relay control lines; and a layer 68 which contains the regions 19 of the various power and common voltage supplies.

The patterns of the conductive material in various of the conductive layers is as shown diagrammatically in Figures 4a to 4d. In this particular example there are, as an illustration of a possible number, four voltage supplies: three for power voltages together with one for testercommon.

The upper layer 64 is generally as shown in Figure 4a. Many of the elements have already been described. There are in this case four pads 21 to take the power and common voltages to the DUT board 4, and in addition a pad 69, not shown in Figure 2a, to provide the ground connection to the DUT board. Similarly there are four rings 55 at the different potentials for load building. A further unconnected ring 70 is present and may be used as a bus-bar by the user for any purpose chosen by him.

There are a large number of pads 42 for logic signals (for example 60) arranged in a circle. The corresponding holes for the connector pins 40/51 are also shown as falling in a circle, but may instead be arranged in radial pairs, for example if required by the construction of the pin electronics connectors 5.

Positions for relays are defined by platedthrough holes provided to accept the relay pins.

The number of positions is advantageously equal to the number of logic pads 42.

The ground layers are not shown in plan, since they consist of conductive material occupying substantially the whole area of the board except for clearances around plated-through holes to which they are not connected.

Each of the layers 66 and 67 containing the control lines 66A for the relays 7 is as shown in Figure 4b.

The power layer 68 is as shown in Figure 4c. It has four substantially complete quadrants of conductive material each forming one of the regions 19.

As shown in Figure 4d, the under layer 65 carries the pin electronics connectors 5, the severable power sense tracks 39 and a ring 71 connected to ground.

The structure of the DUT board 4 is as shown in exploded view in Figure 5. The board is assembled from three insulating sheets 72, 73 and 74.

The upper sheet 72 (that facing the position of the device) carries a single conductive layer 75 on its upper surface. The sheet 73 carries the ground layer 33 on its upper surface and a power layer 76 and the under sheet 74 carries a single conductive layer 77 on its outer surface.

The patterns of the conductive material are shown diagrammatically in Figures 6a to 6c.

The under layer 77 is generally as shown in Figure 6a. Besides elements already mentioned it contains a ground pad 78 which matches the ground pad on the load board 3 and introduces ground into the DUT board 4. It is connected by plated-through holes 79 to the internal ground layer 33. There are also two more surface ground pads 80 connected to the internal ground layer 33 by the holes 35.

The ground layer 33 again is not shown in plan since it consists of conductive material occupying substantially the whole surface area of the board except for clearances around plated-through holes to which it is not connected.

The power layer 76, as shown generally in Figure 6b consists of four quadrants forming the regions 24 for the different voltages. The boundaries in one direction are castellated so as to allow the holes 25 by which they are taken to the surface to be arranged in a straight line.

The upper layer is generally as shown in Figure 6c. It will be seen that there are in fact two pads 34 used for decoupling purposes.

It is to be understood that, although not all are shown in Figures 4a to dand 6a to c, platedthrough holes are present as required to form connections between conductive layers and to receive component leads. The power layers 68 and 76, like the ground layers 30-33 contain clearances in the conductive material around plated-through holes which are not intended to make contact with that layer One such clearance is shown in Figure 4c denoted by the reference numeral 81. For simplicity the drawings omit more than a representative sample of the elements which extend round the board. The load board 3 is normally supplied carrying the connectors 5 for the pin electronics, but the other discrete components are normally added by the user, who will prepare the board for the device or forming of devices with which it is to be used.

The main task is to construct the required loads by inserting relays 7 and resistors 8 or other components connected between the relay and the desired power/common rings 55. Normally a relay will be placed in position approximately in line with the pin connector 5 to which it is connected, but the exact position may be chosen for convenience since the connection to the relay is made by inserting a wire link 53. Decoupling capacitors 9 are also inserted. In addition, links 17 must be inserted for routing the power, or alternatively links to a relay 7 introduced if the power is to be switchable during testing. And the surface tracks 39 must be severed to be replaced by wire links if remote sensing is required.

For each load board one or more DUT boards are prepared, depending on whether the load board is for one device or a family of devices. The DUT board is given the appropriate links 13 and device socket 12.

We find that the interconnection system described has an improved performance compared to the prior system described in the introduction to this specification.

In particular, it has been found that it enables the test equipment connected with the system to operate under its optimum conditions. In practice, it has been found that using the prior interconnection system the output signals for the device under test are degraded as compared with the signal output from the same device when tested by utilising the interconnection system of the invention. In particular, the interconnection system of the present invention reduces input signal degradation which is caused by cross-talk or other signal interference between input or output signals and power inputs to the device under test.

In the prior interconnection system it was realised that such cross talk was degrading the test conditions, so that attempts were made to at least reduce the cross talk. The approach to the reduction of cross-talk involved adding decoupling capacitors at various points in the interconnection system. However, it was found that such an approach did not afford a satisfactory solution since the siting and magnitude of the decoupling capaeitors required was related to the nature of the device under test. In other words, the provision of decoupling capacitors provides a relatively poor compromise solution in situations where there is a need to test different types of device.

In order to alleviate the difficulty it has been proposed to modify the software used with the test equipment. As will be readily appreciated such software modification involves variations in the modifications to suit particular devices under test. With a view to removing or at least substantially reducing the difficulties found with the known arrangements the interconnection system essentially proposes the elimination or at least substantial elimination of the cause of cross talk which has been found to a great extent to arise from current fluctuations which are produced in the power supplies connections to the device under test, when the device is caused to undergo a test procedure which involves the operation of the device under as many as possible of the conditions it is likely to meet when in actual use.It is thought that part of the problem arises in the known interconnection system from the use of relatively small cross section conductors for the power and common voltage supply connections which results in a relatively high resistance.

In addition, there is a general close proximity between the signal connections and the supply connections which facilitates the transfer of interference or cross talk between supply lines and signal lines. In relation to the present invention it is believed that amongst the possible reasons for the significant improvement achieved by the present invention lies the reduction of the resistance in the power and voltage supply lines by the provision of power planes which enable the use of relatively large area connections, regions, such as the regions 19 or 24 in the power layers 68 and 76 of the track and DOT board, which leads to a reduction in the extent to which a change of operative state of the device being tested produces a current fluctuation in the power and voltage supply connections.

Furthermore, the provision of the large pads 21, 69, 22 and 80 (i.e. of large extent) in the connection between the load board and the DUT board, together with the use of multiple plated through holes from such pads to inner power layers is also believed to assist in ensuring that the inner power layers also assist in ensuring a low resistance for the power/supply paths of the system, and thus to minimise any interconnection resistances.

As a further means of reducing cross talk it is proposed to provide screening planes to either side of the power planes. In the figures these ground planes 30,31 and 32 in the load board ensure that the power supplies are fully screened, thereby aiding the suppression of cross talk, and other noise conditions.

In the DUT board the ground layer 33 and the pads 80 have also been found to have a screening effect.

By dedicating inner layers to the relay control lines the outer layers are freed from the need to carry these lines, as is found in the prior system described in the introduction. This simplifies the structure of the outer layers and allows ground rings which surround the load constructing area to be included. These ground rings ensure that a connection to ground can always be made close to the point at which power supplies must be decoupled. As a result the decoupling capacitors can be given short leads, which reduces the ill effects of ringing in the leads. Similarly the ground pads 34 allow the power supply to the device to be decoupled with capacitors with short leads.

Various modifications may be made. Although the full benefit of the invention will not then be obtained, either the load or the DUT board may be used with a double sided board as the other part of the interconnection system, and/or one or more of the ground layers may be omitted.

The interconnection system described uses two boards, the load board and the DUT board. It is possible, for complicated devices which require their own specific load board, to use a single board combining the functions of the two.

Claims

1. A system for testing electronic devices by applying to a device to be tested power and voltage, such as will subject the device to operational conditions similar to those likely to be expected in use, the system comprising circuit interconnection means for interconnecting with the device power and common voltage supply means, means for generating the test signals for the device under test, and means for receiving and evaluating the output signals from the device under test, which interconnection means comprises at least in part a multilayer printed circuit board including at least one layer which provides a connection for a power or common voltage supply and which includes a region of conductive material of substantial extent.

2. A system as claimed in Claim 1, in which the printed circuit board includes a first layer for forming a power or supply plane, which provides the region of conductive material of substantial extent.

3. A system as claimed in Claim 1, in which the printed circuit board includes a first layer of conductive material for providing said region of substantial extent, having on one side thereof a second layer of conductive material of substantial extent for connection to ground and at the other side thereof printed circuit tracks-and/or positions for discrete wiring links, which tracks or links are for providing connections for the input and/or output signals.

4. A system as claimed in Claim 3, and including a further conductive layer of substantial extent interposed between said first layer of the printed circuit tracks or links, said further conductive layer being for connection to ground.

5. A system as claimed in Claim 1, 2, 3 or 4, and in which the interconnection means include first and second multilayer printed circuit boards which are operationally electrically connectable with each other with each of said first and second printed circuit boards having a layer which provides a connection for a power or common voltage supply having a region of conductive material of a substantial extent, and in which the first printed circuit board is adapted for connection with the power and voltage supply means, the signal generating means, and the signal receiving and evaluating means, and the second printed circuit board is adapted for receiving and mounting the device to be tested.

6. A system as claimed in Claim 5, and in which the first printed circuit board is utilised for mounting electrical components for providing the requisite loads for the output terminals of the device, and wherein the first printed circuit board additionally includes at least one additional layer of conductive material of substantial extent for providing conductive paths for control signals or the like for electrical components associated with the first printed circuit board.

7. A system as claimed in Claim 6, wherein for each of said first and second printed circuit boards each of said conductive layers associated with power and voltage systems is electrically screened by conductive layers serving as ground layers for the system, and wherein said ground layers occupy substantially the whole surface area of the board except for any clearance that may be required around interlayer connection.

8. A system as claimed in Claim 5, 6 or 7, and in which the first printed circuit board has a central aperture which is bounded on the side of the board that is to be remote from the second printed circuit board with a series of connection means adapted for connection to said generating and receiving and evaluating means, and which is bounded on the side thereof that faces the second printed circuit board by circuit connection means adapted to connect with complementary connection means provided upon the second printed circuit board said circuit connection means on each of said printed circuit boards being of relatively large extent so as to minimise any interconnection resistances.

9. A system for testing electronic devices by applying to a device to be tested power and voltage such as will subject the device to operational conditions similar to those likely to be expected in use, constructed and arranged to operate substantially as hereinbefore described with reference to the accompanying drawings.