GB2104264A

GB2104264A - Code recognition circuit

Info

Publication number: GB2104264A
Application number: GB08123064A
Authority: GB
Inventors: Colin Jeffrey
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1981-07-27
Filing date: 1981-07-27
Publication date: 1983-03-02
Also published as: DE3226844A1; CH660270A5; AU554975B2; AU8623682A; GB2104264B

Abstract

An incoming N bit digital data word is loaded into a recirculating shift register (10 and 11) which is clocked at a high clock rate that is a multiple of the incoming data word bit rate. The recirculated word and a predefined word are compared serially at the high clock rate in a compare element (12), the differences being counted (13). The circuit is particularly suitable for large scale integration, since it employs less logic elements than conventional parallel compare methods, and suitable for applications requiring high comparison speeds, such as in digital radio pager receivers. The application of the circuit to a pager decoder custom integrated circuit is discussed. <IMAGE>

Description

SPECIFICATION Code recognition circuit This invention relates to a code recognition circuit, that is a circuit for comparing one digital data word with a similar digital data word and determining whether there is a match be detecting any differences (errors) between the two words, and is particularly but not exclusively related to digital radio pager receivers.

According to one aspect of the present invention there is provided a method of comparing one incoming N bit digital data word with a similar N bit digital data word whereby to detect any differences therebetween, comprising loading the one N bit digital data word into a recirculating N bit shift register, the register being clocked at a first clock rate comprising a multiple of the incoming data word bit rate, and serially comparing at the first clock rate the word loaded in the shift register with the similar word and counting the number of differences between the two words.

According to another aspect of the present invention there is provided a code recognition circuit wherein an incoming N bit digital data word is compared with a predefined N bit digital word and any differences therebetween detected, comprising a recirculating N bit shift register into which the incoming word is to be loaded, which register is clocked at a first clock rate comprising a multiple of the incoming data word bit rate, a compare element, means to feed the predefined word to the compare element at the first clock rate together with the recirculated word whereby to compare the respective bits thereof serially at the first clock rate, and a counter to count the number of differences between the incoming and predefined data words.

According to a further aspect of the present invention there is provided a decoder circuit for a digital radio pager receiver including a code recognition circuit whereby an incoming N bit digital data word for synchronisation word detection and address word detection proposes, and a bit synchronisation circuit to which the incoming N bit digital data word is also applied, wherein the code recognition circuit includes a recirculating N bit shift register comprising an (No1 ) bit shift register together with a single bit shift, and a two bit data store via which the incoming data word is loaded into the shift register, which code recognition circuit is such that a word loaded into the shift register and circulated therein can be compared a plurality of times in consecutive bit periods with the predefined word, once in each half bit period, and wherein word advance and loading of a new data bit into the shift register is suppressed during the half bit periods of the consecutive periods other than the first half bit period, the bit synchronisation circuit being inoperative during the said first half bit period.

An embodiment of the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 illustrates a conventional "parallel" compare method; Figure2 illustrates a conventional "serial" compare method; Figure 3a illustrates code word format; Figure 3b shows a 32 bit synchronisation codeword; Figure 3c shows a 32 bit idle codeword, Figure 4 illustrates the compare method according to the present invention.

In the conventional "parallel" compare method (Figure 1), one digital data word is stored in one register 1, another similar digital data word with which the one data word is to be compared is stored in another register 2. For a data word with N bits each register 1 and 2 will comprise N data latches.

The thus paired bits are compared simultaneously using N compare elements 3, which may comprise exclusive OR gates, and the number of errors between the two words counted by an error counter 4. This method enables comparison to be performed quickly, but has the disadvantage of requiring a large number of logic elements, which means that it may not be suitable for large scale integration along with other functions in a single integrated circuit chip.

In a conventional "serial" compare method (Figure 2) two digital data words are entered and compared bit by bit. Thus only one latch 5, 6 is required for each N bit data word, together with a single compare element 7 and an error counter 8. N clocks are required to clock the data words through.

Whilst the serial method requires less logic elements than the parallel method, it requires a longer time to complete the compare operation.

The compare method of the present invention is a combination of the parallel and serial approaches which enables fast comparison of incoming data with predefined words to be achieved without requiring a large number of logic elements. The compare circuitry of the present invention was specifically designed for use as a Code Recognition Circuit in a digital radio pager receiver, but its application is not so limited. A digital radio pager receiver is required to receive and process reliably broadcast digital signals which may be noisy or jittery at the point of reception.

The following description is based on the application of the compare method and circuitry of the present invention to the digital decoder of such a pager which employs a code in accordance with the Final Report of the British Post Office Code Standardisation Advisory Group (POCSAG). The code is based on a (31, 21, 2) BCH Code and the full specification for the Standard Code Format is to be found in the report. A transmission consists of a preamble followed by batches of complete codewords, the format of a codeword is shown in Figure 3a. Each batch comprises a synchronisation codeword (Figure 3b) followed by 8 frames each containing two codewords (address and message). The pager population is divided into 8 groups, each pager being allocated to one of the 8 frames and thus will only examine address codewords in that frame.Therefore each pager's address codeword must only be transmitted in the frame that is allocated to those codewords. Message codewords for any pager receiver may be transmitted in any frame, but will follow directly the associated address codeword. A message may consist of any number of codewords transmitted consecutively and may embrace one or more batches, but the synchronisation codeword must not be displaced by message codewords. Message termination is indicated by the next address codeword or an idle codeword (Figure 3c). In the absence of an address codeword or message codeword an idle codeword is transmitted.

Each codeword is a 32 bit digital codeword (Figure 3a). Each codeword has 21 information bits which correspond to the coefficients of a polynomial having terms from x30 down to x10. The polynomial is divided, modulo - 2, by the generating polynomial x10 + xS + xS + x6 + x5 + x3 + 1. The check bits correspond to the coefficients of the terms from x9 to x0 in the remainder polynomial found at the completion of this division. The complete block, consisting of the information bits followed by the check bits, corresponds to the coefficients of a polynomial which is integrally divisable in modulo-2 fashion by the generating polynomial. To the 31 bits of the block is added one additional bit to provide an even bit parity check of the whole codeword.

Each transmission starts with the preamble to permit the pagers to attain bit synchronisation and prepare them to acquire word synchronisation. The preamble is a pattern of reversals 101010.... repeated for a period of at least 576 bits, that is the duration of a a batch plus a codeword. The circuit of the present invention is employed as a code recognition circuit in the pager for comparing the transmitted synchronisation codeword with a predefined synchronisation codeword, and for comparing the transmitted address codewords with a predefined address codeword. It does not attempt any direct comparison by use of the error correction capability contained in the code. Since the code recognition circuit is required to form part of the pager decoder in a custom integrated circuit, various constraints are placed on its design.

A pager may be switched on at any time, or emerge from an area where radio reception is marred (such as in a tunnel or under a bridge), thus it is desirable that the pager can attain bit and word synchronisation, determining between true data and random noise, in a minimum time. A particular bit synchronisation and data/preamble detector is disclosed in our co-pending application No. (I.A.W.

Vance - B.A. Bidwell - C. Jeffrey- D.F.A. Leevers M.J.A. Woodley 11-7-3-1-1), and the comparison (code recognition) circuit of the present invention is particularly, but not exclusively, suitable for use therewith in a digital radio pager decoder. The data is transmitted as 32 bit words, an even parity bit having been added to the BCH code as mentioned above, at a data rate of 512 bits per second.

Referring now to Figure 4, the compare method of the present invention will be described. Figure 4, however, includes more elements than the basic method requires. Incoming data is read into a recirculating N bit shift register, a 32 bit shift register in the case of a pager as described above, instead of an N bit latch in the parallel method of Figure 1. The recirculating N bit shift register of Figure 4 is comprised by a (N-1 ) bit shift register 10 and a single bit shift 11 for reasons which will be described hereinafter for the pager application. The shift register, which has small elements facilitating integration, is clocked at a multiple of the incoming bit rate, so that in one bit period N bits of data may be cycled more than once.In the pager application a 31 bit shift register together with a single bit shift are employed as the shift register, which is clocked at 32 kHz so that each word is cycled once in the first half bit period, advancing one location to allow a new data bit to be entered (loaded) at the beginning of the next bit period. Normally during the second half bit period the register is not clocked. This means that the contents of the data store (shift register) are not corrupted by tiny variations caused by bit synchronisation occurring in parallel, as described hereinafter, in the pager decoder.

Thus the word in the register (10, 11) is updated every data bit and a current data word can be compared serially against a predefined word by comparing the contents of the register with a predefined word, as for example provided by code generator block 14 which is also clocked at the 32 kHz clock rate, by means of a compare element 12 and an error counter 13.

The principle can be extended to compare M predefined words, if the clock rate is set at M times the incoming data rate, although this is not always practicable.

For the pager application the basic circuit comprising an N bit recirculating shift register, a predefined word source, a compare element and an error counter was retimed to the form shown in Figure 4to allow comparison of four predefined (address) codewords, as described hereinafter, in order to enable one of four different times.

Since the data is in 32 bit words it is normally only necessary to make a comparison after the 32nd bit has been received. Hence the number of comparisons can be increased by continuing to cycle this same word again during the second half bit period, and a further twice during the following bit period, but suppressing the word advance and the loading of the new data bit during this time period. In order to allow the next 32 bit word to be tested it is necessary to recover the first bit which was not loaded into the shift register at the correct time. This is achieved by use of a 2 bit data buffer, which acts as a temporary two bit store 15, so that 2 bits can be simultaneously loaded into the shift register with recovery of the "lost bit". Hence by this method four comparisons can be achieved without increasing the clock rate.

It is a feature of this circuit that, as a result of the properties of the (31, 21, 2) BCH codes, it is not necessary to store the 11 least significant bits in the pager decoder employing the circuit, since the 10 parity check bits plus an even parity bit, are generated according to predefined polynomial by a code generator 14. Further, in this application since the remaining 21 bits of the 4 predefined words differ only in their two least significant bits, and for an address codeword the most significant bit is always the same (logic 0), it is only necessary to store a single 18 bit word to generate all 4 predefined address words. The code generation block 14 may be replaced by other means producing a predefined word with which another word is to be compared.

The specific block 14 described illustrates, however, that the number of logic elements needed to create the predefined (address) codewords is minimised using BCH codes. Thus employing the present invention together with such code generation means that number of logic elements is further reduced in comparison with employing parallel compare methods.

The present invention employs serial comparison, which is generally slow, for the actual comparison.

However, the comparison is performed at a high clock speed and one 32 bit recirculating shift register is used instead of two 32 bit latches (Figure 1 parallel method), a shift register being less complex than a latch. Thus the present invention provides fast operation with a reduced number of logic elements, making the comparison circuit particularly suitable for large scale integration.

The function of the code recognition circuit of Figure 4 in the overall pager decoder will be apparent from the following description of the operation of the pager decoder. The digital pager decoder is intended to be formed as a custom integrated circuit which is employed with another custom integrated circuit, the radio chip, in the overall pager, described further hereinafter.

The radio chip is a linear analogue circuit which interfaces with the digital pager decoder chip. The radio chip also processes incoming data off air into a digital signal (DATA) which is supplied to the digital decoder. The radio chip circuit may be as described in our British Patent Specification 1 517 121 (I.A.W.

Vance 3), or our co-pending Application No.41679/ 78 (Serial No. 2032737) (I.A.W. Vance 5) and No.

7930578 (Serial No. 2 057 820) (I.A.W. Vance 8), for example.

Data is only cycled in the shift register (data store) during the first 1/2 bit period, and normally data is not cycled during the second 1/2 bit period. During this second 1/2 bit period bit synchronisation is achieved and it is essential that the data in the store is not scrambled, since this would invalidate code recognition. In order to achieve this, the algorithm for bit synchronisation requires that information in the data store is not clocked or shifted during bit synchronisation. Stated another way, there is a dead period of the data store when the data is locked in but not shifting and thus not affected by bit synchronisation.

Thus data is loaded into the store at the required bit rate and recirculated to advance it bit-by-bit, but then its clock is stopped so that the data is not affected by bit synchronisation. The bit synchronisation circuit thus effectively drives the clock to the data store, so that the data store and bit synchonisation circuit are closely inter-related. This is of course only relevant with this type of recirculating data store. If the data is not being shifted in such a recirculating store at a high bit rate then changes in bit synchronisation will not affect the data.

Within the decoder it is not necessary to bit synchronise over the full batch period, and in fact bit synchronisation is stopped at the time of address word comparison, in order to ensure recirculation in the data store and comparison of four words in 2 bit periods.

The basic compare method of the present invention, which is a combination of the parallel and serial methods of the prior art, requires the digital data to be fed into a recirculating shift register which is clocked at high speed, and once a complete data word is circulating therein it can be shifted straight out, when required, at the high clock rate and compared serially at the high clock rate with a prefixed word.

Claims

1. A method of comparing one incoming N bit digital data word with a similar N bit digital data word whereby to detect any differences therebetween, comprising loading the one N bit digital data word into a recirculating N bit shift register, the register being clocked at a first clock rate comprising a multiple of the incoming data word bit rate, and serially comparing at the first clock rate the word loaded in the shift register with the similar word and counting the number of differences between the two words.

2. A method as claimed in claim 1 wherein a word loaded into the shift register and circulated therein is compared a plurality of times in consecutive bit periods with the similar word, once in each half bit period, and wherein word advance and loading of a new data bit into the shift register is suppressed during the half bit periods of the consecutive bit periods other than the first half bit period.

3. A method as claimed in claim 2 wherein the N bit shift register is comprised by an (N - 1) bit shift register together with a single bit shift, and wherein incoming data is loaded into the shift register via a two bit data buffer whereby to permit simultaneously loading of two bits are permit recovery of the first loaded bit of the one word.

4. A code recognition circuit wherein an incoming N bit digital data word is compared with a predefined N bit digital word and any differences therebetween detected, comprising a recirculating N bit shift register into which the incoming word is to be loaded, which register is clocked at a first clock rate comprising a multiple of the incoming data word bit rate, a compare element, means to feed the predefined word to the compare element at the first clock rate together with the recirculated word where by to compare the respective bits thereof serially at the first clock rate, and a counter to count the number of differences between the incoming and predefined data words.

5. A code recognition circuit as claimed in claim 4, wherein the shift register comprises an (N- 1) bit shift register together with a single bit shift, and comprising a two bit data store via which the incoming word is to be loaded into the shift register.

6. A decoder circuit for a digital radio pager receiver including a code recognition circuitwhere- by an incoming N bit digital data word is compared with a predetermined N bit digital data word for synchronisation word detection and address word detection purposes, and a bit synchronisation circuit to which the incoming N bit digital data word is also applied, wherein the code recognition circuit includes a recirculating N bit shift register comprising an (N-1) bit shift register together with a single bit shift, and a two bit data store via which the incoming data word is loaded into the shift register, which code recognition circuit is such that a word loaded into the shift register and circulated therein can be compared a plurality of times in consecutive bit periods with the predefined word, once in each half bit period, and wherein word advance and loading of a new data bit into the shift register is suppressed during the half bit periods of the consecutive periods, other than the first half bit period, the bit synchronisation circuit being inoperative during the said first half bit period.

7. A decoded circuit as claimed in claim 6, wherein the shift register is clocked at a first clock rate comprising a multiple of the incoming data word bit rate, wherein the code recognition circuit further includes a compare element, and wherein means are provided to feed the predefined word to the compare element at the first clock rate together with the recirculated data word whereby to compare the respective bits thereof serially at the first clock rate.

8. A method of comparing one incoming N bit digital data word with a similar N bit digital data word substantially as herein described with referpence to Figure 4 of the accompanying drawings.

9. A code recognition circuit substantially as herein described with reference to and as illustrated in Figure 4 of the accompanying drawings.

10. Adecodercircuitfora digital radio pager receiver substantially as herein described with reference to and as illustrated in Figure 4 of the accompanying drawings.

11. A digital radio pager receiver including a decoder circuit as claimed in any one of claims 6,7 and 10.

12. A digital radio pager receiver including a code recognition circuit as claimed in any one of claims 4,5 and 9.