GB2099616A - Improvements relating to microprocessor units - Google Patents

Abstract

A microprocessor (1) is encapsulated with a security device. Two field programmable logic arrays (3, 4) are programmed in inversely matching manner an arrange respectively in input and output buses (2, 5) to the microprocessor. These may be for data and/or for addresses. When programming a system memory, data is written in via one of the FPLAs. This effectively scrambles the data into apparently meaningless form in the memory. However, when read out again, it is passed via the other FPLA, which unscrambles it, to the microprocessor. Similarly, data can be placed in 'wrong' addresses in the memory, but when re-addressed via this unit the correct data is extracted. <IMAGE>

Description

SPECIFICATION Improvements relating to microprocessor units This invention relates to microprocessor units and is concerned with providing some security against copying or stealing of programs.

Generally, there are two forms of security required, one being to block multiple copying of a program for use elsewhere, and the other being the prevention of up-dating of a system solely by replacing old software with new. Such software is generally embodied in memories which are small and cheap, and a complicated machine can sometimes be effectively refurbished just by changing to new memories.

The aim of this invention is to provide a defence against these abuses and to ensure that only the original manufacturer will have the ability to make a useful copy or to update.

According to the present invention there is provided a microprocessor unit in which the microprocessor is encapsulated with a security device, this device comprising inversely matched scrambling units through which input and output signals are respectively passed.

Conveniently, these scrambling units are field programmable logic arrays (FPLAs).

In use the microprocessor unit is connected to a memory. This memory will first be programmed through one of the FPLAs which will transpose at least some bits of data into different positions. Thus the memory is stocked with apparently meaningless information. Once it is programmed, the encapsulation is carried out, concealing the FPLAs and much of the microprocessor, but of course leaving the essential terminal pins exposed.

The unit can then be plugged into a processor socket of the system hardware and, despite the apparently meaningless program in the memory, will still function satisfactorily. This is by virtue of the second FPLA through which the information from the memory is directed back to the microprocessor when suitably addressed. The second FPLA transposes the bits back to their original positions.

As well as scrambling and unscrambling the data bits, additional security can be provided by varying the coding pattern according to different addresses.

For a better understanding of the invention one embodiment will now be described, by way of example, with reference to the accompanying drawing in which the single Figure is a diagram of a microprocessor unit.

The microprocessor 1 has a two-way data bus 2 for communication with FPLAs 3 and 4. It is also connected to them by an address bus 5 and read and write lines 6 and 7. The FPLAs are connected by a continuation 8 of the bidirectional data bus to a system memory (not shown) and the address bus has a branch 9 forming the system address bus. In fact, this branch has many more lines than those leading to the address inputs of the FPLAs, as will be explained below. The microprocessor and FPLAs, with their interconnections are encapsulated in a block, of epoxy resin for example, indicated by broken line 10.

Pins for connection to the memory and other units are left exposed. This encapsulation effectively prevents dissection of the unit and thus discovery of the FPLA programs.

Assume that each word to be stored is a byte of 8 bits. In this case, an encoding pattern may have 8 terms enabling each bit to be displaced to another position, for example in accordance with the following:

Thus, whatever appears as the LSB at the input is shifted to the MSB position at the output, the next bit to the LSB is shifted to the third highest position, and so Qn. An eight output FPLA, with of.

course at least eight inputs, can readily accomplish this, and a similar FPLA can reverse the procedure and produce the original byte.

However, there is a slight danger in always using the same code. Repitition can give clues aiding decipherment. Therefore it is desirable to change the coding pattern at intervals, to add further confusion.

A commonly available eight-output FPLA has 16 inputs and 48 terms. As the single encoding pattern of the present example requires 8 terms, the FPLA can accommodate six different patterns, and these can be identified by using three of the remaining eight inputs. Thus the first pattern above may be used by addressing these inputs 001, a second pattern by address 010, a third pattern by 011 and so on.

When programming the memory through FPLA 3, the code pattern is altered in a known sequence so that different locations hold differently encoded information. For example location 1 may use pattern 1, location 2 pattern 2, and so on in cyclic fashion. But the information is still recoverable if the reversing FPLA 4 is correspondingly programmed. When the microprocessor addresses location 2, or 8, for instance, FPLA 4 will be instructed by that address to unscramble in the pattern 2 mode.

At the same time as FPLA 4 is addressed with the pattern number, so is the main memory addressed through branch 9. The location identification will require more bits than the three that are used for determining the coding pattern, but those three can also be used as part of the adresses to the main memory.

It will be understood that it is not essential to scramble an entire word. For example an encoding pattern may simply transpose four out of eight bits, leaving the other four untouched.

As well as, or instead of, scrambling data, it is possible to treat the addresses in this way. Thus instead of the branch 9 going direct to the memory it may connect via a FPLA of suitable capacity.

When programming the memory, it is addressed via this encoding FPLA and instead of location 1, the first data byte or word is entered in another location, and so on.

In use, the microprocessor will issue the correct address to this FPLA, which will transform it into the apparently wrong address and feed this to the memory However, the "right" information is at this "wrong" address, albeit possibly in coded form itself. This information is read out to a reversing FPLA which decodes it as necessary and delivers the correct information to the microprocessor.

Claims (8)

1. A microprocessor unit in which the microprocessor is encapsulated with a security device, this device carrying inversely matched scrambling devices through which input and output signals are passed.

2. A unit as claimed in claim 1, wherein the scrambling devices are field programmable logic arrays.

3. A unit as claimed in claim 1 or 2, wherein one scrambling device has an encoding pattern arranged to transpose bits within words of data to be programmed into a memory, and another scrambling device has a decoding pattern arranged to transpose bits within words of data from the memory in the reverse manner.

4. A unit as claimed in claim 3, wherein the encoding and decoding patterns vary according to address information.

5. A unit as claimed in claim 4, in combination with a memory programmed through one of the scrambling devices, wherein the memory is arranged to be addressed using, at least in part, the address information which determines the encoding and decoding patterns.

6. A unit as claimed in any preceding claim, in combination with a non-volatile read only memory, with the modification that the scrambling device through which output signals are passed is functional only during programming of the memory, and is removed before encapsulation.

7. A unit as claimed in any one of claims 1 to 6, wherein the scrambling devices are arranged to transpose addresses in a memory.

8. A microprocessor unit substantially as hereinbefore described with reference to the accompanying drawing.