GB2082358A - Security systems - Google Patents

Abstract

A detector system comprises a loop containing two or more detectors electrically connected in series each operable to alter an electrical parameter of the loop by a unique amount. A microprocessor control system repeatedly measures the electrical parameter by measuring the effect the latter has on the period of a monostable (15) and compares the measured value with signals stored in a memory. If a detector has been actuated, the system produces an alarm signal. Periodic measurements when no detector is actuated derive correction factors for circuit variations. <IMAGE>

Description

SPECIFICATION Detector systems The invention relates to detector systems.

According to the invention, there is provided a detector system comprising at least one loop containing two or more electrically connected detectors, each detector of the or each loop being operable to alter an electrical parameter of the associated loop by an amount which differs from the alteration produced by the or each other detector of the loop, a memory for storing signals representative of the alteration in or the value of the electrical parameter on operation of each detector, and a control system for repeatedly measuring said electrical parameter of the loop, for comparing the measured value of the parameter with the stored signals and, if a detector has been actuated, for producing an alarm signal.

A previously proposed system comprises a plurality of detectors electrically connected to a control system. The detectors are mormally in closed circuit and when any one of the detectors is operated and becomes open-circuited, the control system senses the opencircuit and produces an alarm signal. It is a disadvantage of such systems that the location of the detector which has been operated cannot be determined other than by visual inspection of all the detectors or by an expensive and complicated system in which each detector is individuaily monitored and is connected separately to the control system.

According to a preferred feature of the present invention, the control system may also produce an output identifying the actuated detector.

The control system preferably includes a microprocessor, a ROM connected to the microprocessor for storing programmes of operations to be conducted by the control system, a RAM also connected to the microprocessor for storing intermediate values and a peripheral interface adaptor for delivering control system outputs and for receiving signals corresponding to the measured value of the parameter.

The following is a more detailed description of one embodiment of the invention, by way of example, reference being made to the accompanying drawings, in which: Figure 1 is a schematic block diagram of a control system of a security system, and Figure 2 is a schematic circuit diagram of a detector loop and a monostable circuit of the security system of Fig. 1.

Referring first to Fig. 2, the security system comprises one or more loops formed by a plurality of electrical detectors 10 connected in series. Each detector 10 comprises an electrical resistance 11 in parallel with a contact 1 2 which is normally closed but which is opened to place the associated resistance 11 into the loop on operation of the detector 10, for example, by unauthorised entry into a zone protected by the detector. The or each loop may be interconnected by a single wire, and thus be a "single pole" wired or may have "double pole" wiring in which each detector has two input connections and two output connections and two wires interconnect the detectors to form a double loop. One loop contains the contacts and the other loop may be permanently short-circuited.This provides a safety feature in that breakage of the short circuit or connection of the short circuit loop to the detector loop can be detected and regarded as evidence of the loop having been tampered with. Alternatively, the other loop may contain detectors so that each detector has two contacts ganged together.

The or each loop is connected to a source of voltage (not shown) and to a capacitive/resistive control 14 of a monostable circuit 1 5.

The monostable circuit 1 5 has a pulse duration, when set, which depends on the value of the resistance in the control 14 and the associated loop and has an absolute value of the range of the pulse duration which is dependent on the capacitive value of the control 14 which, in the present case, is fixed in a manner described below. The trigger input 1 6 of the monostable circuit 1 5 is connected to a bit location 1 7a of a register 18 and the output 1 9 of the monostable circuit 1 5 is connected to a sign bit location 1 7b of the register 18.

The register 18 forms part of a peripheral interface adaptor (PIA) 20 which is included in a control system shown in Fig. 1. The control system also includes a microprocessor 21, a read-only memory (ROM) 22, a random access memory (RAM) 23, a synchronous communications interface adaptor (ACIA) 24.

These components are interconnected by a data bus and an address bus. The PIA 20 has an input connected to a key-operated switch (not shown) having three positions, 'on' and 'off, to the or each loop, as described above with reference to Fig. 2, and to a device (not shown) for choosing, where there is more than one loop, which loop or loops are to be rendered inoperative. The PIA also has an output connected to an alarm (not shown) for location outside the zone protected by the security system, to a buzzer (not shown) for location within said zone, to an illuminated indicator (not shown) and to further equipment to be described in more detail below.

In operation, the security system can be designed to operate in one of two modes; a first mode in which the system identifies each and every detector operated and the sequence in which they are operated and a second mode in which the system identifies only the first detector operated and also indicates when more than one detector has been operated.

The system is arranged as follows to operate in the first mode.

The resistance 11 of the detectors 10 in each loop are chosen so that each has a different resistance and so that any combination of resistances has a different resistance to any single resistance or other combination of resistances. The differences between these resistances must be sufficient to allow for the maximum resistance usable with the monostable circuit 15, resistor accuracy and the range of resistances commonly available. These considerations will limit the number of detectors which can be used in one loop. One such loop might, for example, contain five detectors satisfying these requirements.

Alternatively, where the detectors are double pole wired with each detector have ganged contacts, the resistances may be arranged so that the combination of the resistance in the first loop and the resistance in the second loop is unique for each detector. Thus if x different resistances are used x2 different detectors can be identified (e.g. the first detector may have resistance R, in loop 1 and R, in loop 2 the second detector resistance R, in loop 1 and R2 in loop 2 and so on).

In the second mode, the resistances of the detectors are all different from one another with the combined resistance of any two resistances being greater than any single resistance and above a predetermined level. Once again, the number of detectors 10 which can be included in a loop depends on the maximum resistance usable with the monostable circuit 15, resistor accuracy and the range of resistances commonly available. One such loop might, for example, have 1 2 or 24 detectors.

When using either mode, the value of the loop resistance is measured in the same way, as follows. Referring to Fig. 2, ROM 22 contains a monostable circuit monitoring routine which comprises the following steps. First an index register (not shown) of the microprocessor 21 is cleared and its contents if they are required in the future, are stored in RAM 23.

This index register is set to zero. The register 18 of PIA has the bit location 1 7a incremented and decremented and this provides a trigger pulse to the input 1 6 of the monostable circuit 1 5 which is thus set and feeds an output signal to place a 1 in the sign bit location 1 7b of the register 1 8.

The routine then comprises incrementing the index register and then comparing the contents of the index register with a maximum count. If this is exceeded then there is a fault and the control system will react in accordance with a predetermined fault response.

The next instruction is to test the value of the sign bit location 176 of the register 18. If it contains a 1, that is to say of the monostable circuit 1 5 is set, the routine is repeated from the point where the index register is incremented. This continues until the monostable circuit 1 5 returns to the unset state when the bit in the sign bit location 1 7b is a 0. The routine then finishes and the index register contains a count which is proportional to the set time of the monostable circuit 1 5 ahd is thus proportional to the resistance of the loop.

It will be appreciated that the sequencing of - this routine requires to be controlled and for this purpose a clock (not shown) provides in the microprocessor 21 is used. Each instruction of the routine takes a predetermined number of clock cycles and thus one sequence of the routine takes a predetermined time. It follows therefore that the time taken to accumulate the count in the index register, is an integer number of clock cycles. The possible maximum and minimum values of this time will determine the required range of times for which the monostable circuit should be able to remain set and this will thus determine the characteristics of the control of the monostable circuit.

The correspondence between a particular count in the index register and particular values of the capacitance and the resistance in the loop and the monostable circuit control will depend on the stability of these values with time. Both capacitors and resistors are temperature sensitive, capacitors more so that resistors, and in addition the resistance of the contacts in the detectors 10 may vary with time. In order to allow for such variation, ROM 22 carries a value of the count in the index register when no detector 10 is operated and under nominal ambient conditions.

ROM 22 also contains a programme in which the microprocessor periodically performs the monitoring routine when no detector is operated and thus obtains a count in the index register which includes any errors induced by variations in the components of the loop and the control. This count is compared with the nominal count to produce a continuously updated correction factor which is applied to an index register count obtained when a detector 10 has been operated. Of course, where double pole double contact detectors are used, both loops are interrogated to detect an alarm.

When operating in either mode, the control system, on detection of the operation of any detector 1 0. enters an alarm routine contained in ROM 22. The first operation in this alarm routine is to ascertain whether the alarm condition persists for longer than a predetermined time, for example 200 milliseconds. If it does, a the next operation is for a signal to be sent via PIA 20 to the alarm to activate the alarm. The next instruction is to ascertain whether the system has a 'Dial 999' option and, if it has, a routine for this option is entered in a manner described in detail below. If it has not, the routine jumps to ascertain whether the system has a 'Dial Number' option and, if it has, a routine for this option is entered in a manner described in detail below. If it has not, this routine stops.

When using the first mode, ROM 22 contains counts representative of the counts produced by operation of any detector 10 or combination of detectors 10. When the monostable circuit monitoring routine is completed, the count in the index register, with any necessary correction applied, is compared with the counts in ROM 22 to identify the detector or combination of detectors which have been activated. The identity of the activated detector or detectors 10 is then stored in RAM 23 and can be released on demand either through a socket or on a display which may display either the identities of all detectors activated and the sequence of their operation if required or only the first.

When using the second mode, ROM 22 contains counts representative of the counts produced by operation of any one of the detectors. In addition, microprocessor 21 will recognise when the count exceeds the count of any one detector. When a monostable circuit monitoring routine is completed, the count in the index register, with any necessary correction applied, is compared with the counts in ROM 22 to identify the detector operated. If more than one detector is operated, this is recoginised by the microprocessor 21. RAM 23 stores the identity of the or the first detector operated and this is either displayed or released on demand together with the formation that more than one detector 10 has been operated.

This information is useful to the police in the case of a genuine alarm since identifying the detector or detectors activated will show them where there has been unauthorised access. In the case of a false alarm, the information will allow a service engineer to identify the faulty detector or detectors or zone or procedure.

ROM 22 may also contain various other routines such as 'Dial 999', 'Dial Number' and 'Initiate Direct Line Communication' as well as a '24 hour latch' and 'Entry/Exit Route' routines. Briefly, these routines are effected as follows.

The 'Dial 999' routine is entered when operation of a detector is effected with the key-operated switch 'on'. The routine comprises closing a telephone line loop via PIA 20 and sending a signal via PIA 20 to open and close the telephone line impulse contacts in a manner to send three correctly spaced trains of nine pulses along the telephone lines.

When the connection is established, a prerecorded tape is turned on for a predetermined time to pass a message down the telephone lines. When the message has been completed, the tape is turned off and the telephone is disconnected. The message alerts the police to the fact that a detector has been operated.

It may also be required to convey a message to a central station when a detector is operated. This message may be in digital form and the Dial Number' routine effects the transfer of this message as follows. A RAM 23 memory location is set with a number which corresponds to the number of attempts which are to be made to contact the central station. The telephone loop is closed and the number of the central station is then dialled, using a dialling sub-routine, via the ACIA 24 and modem 25, which is in the originate mode. A waiting loop is entered to wait for a response from a modem at the central station, which is in the answering mode. If this takes too long to arrive, the telephone loop is opened, the memory location in RAM 23 is decremented and, if less than a maximum set number of attempts have been made, the telephone loop closed and the number redialled.If the maximum set number of attempts have been made the routine is halted.

When contact is established with the modem at the central station the digital message is transmitted and a waiting loop is entered to wait for an acknowledgement signal from the central station. If this does not arrive in a predetermined time, the telephone loop is broken and the routine recommenced. If an acknowledgement is received the telephone loop is opened and the routine finished.

It will be appreciated that outside communications can be initiated to signal not only operation of a detector but also a personal attack, low votage in the system, opening and closing routines, fire and false alarm conditions, for example.

The '24 Hour Latch' routine is used to provide a continuous watch for any tampering with the security system. Where the loops are double pole wired, this, for example, may take the form of a break in the second loop. These and the operation of any other tampering detectors are detected by the control system.

The routine proceeds as follows. A memory location in RAM 22 is designated as a 24 hour latch and contains either an entry corresponding to 'no tampering' or an entry corresponding to the detection of tampering. This location retains the tampering entry until reset, even if the tampered circuit is rectified.

The first step in the routine is for the microprocessor 21 to test the 24 hour latch.

If it contains a tampering entry, the buzzer is turned on via PIA 20, regardless of whether there is actual tampering. If there is no tampering entry in the latch, the routine then tests the circuits. If no tampering is detected, this routine ends. if, however, tampering is indicated, the tampering entry is entered into the latch and the buzzer is turned on via PIA 20. The next instruction tests the position of the key-operated switch and, if it is set to the 'off' of 'test' positions, the full alarm is not sounded and the routine finishes. If, however, the switch is set to 'on' the system enters the alarm routine described above.

The 'Entry/Exit' routine is designed to allow a person to leave or enter the zone protected by the system without the alarm being sounded. The entry/exit route is past designated detectors and this route must be negotiated in a predetermined time to prevent the alarm being sounded. The sequence of detectors and the time are stored in the system and the alarm is not sounded if the correct entry/exit procedure is adopted.

The control system may also include a programme for allowing a graded response where a particular zone is protected by two or more detectors of the same or different types. In this case, when a first detector is operated, the control system gives an alert signal but a full alarm is not given unless one or more further detectors protecting the zone is or are operated within a set time. This reduces the incidence of false alarms due to the malfunction of one detector.

The system has been described above with only one loop of detectors. It will be appreciated that two or more loops may be provided to protect two or more zones. The system may, in this case, have the facility for switching into and out of the system various combinations of loops to vary the zones protected by the system. A single monostable circuit may be provided with the loops being connected to the circuit in succession. Alternatively, each loop may have its own monostable circuit and the control system be connected in succession to the inputs and outputs of the monostable circuits.

It will be appreciated that the conversion of the resistance in a loop on operation of a detector 10 into a signal usable by the control system need not be by use of a monostable circuit. For example, the resistance could be converted to an analogue voltage or current which is in turn converted by an analogue-todigital converter into a digital number proportional to the resistance.

In the embodiments described above with reference to the drawings, absolute resistance values are measured in each loop. It will be appreciated that this is not essential and the system could work by measuring the alteration in resistance caused by the opening or closing of a control. It has been found that if such a technique is used a large number of contacts (e.g. 50) are possible in a loop containing 1% resistances and more in double pole wired loops.

Each detector 10 may be arranged to have a resistance even when closed so that the associated loop has a datum resistance. If an attempt is made to bridge a detector 10 and so short it out of the loop, the datum resistance will be altered and this will be detected by the control system and the alarm sounded.

The alarm will also be sounded in such an arrangement if a break-in is attempted by measuring the voltage in the loop and then injecting a corresponding voltage into the loop because this will alter the resistance of the loop.

False alarms are frequently caused by a lowering of insulation resistance between loops having differing potentials or to grounds, by increased loop resistance due to cable faults or by the existence of excessive contact resistance or contact potential due to oxidation or corrosion of joints along a loop.

To overcome this problem, ROM 22 may contain a programme which continuously monitors the progressive build-up of an incipient false alarm. This can be done even when the building is occupied by including in the programme a command to ignore resistance changes produced by operation of the contacts.

ROM 22 can also be programmed to operated the alarm when a contact is operated outside predetermined times. The times are determined by reference to the clock in the microprocessor. This option is useful where a safe or vault is opened only at a certain specified times.

The control system may include a pushbutton array to allow alphanumeric commands to be entered into the system to enable optional features to be selected or switched out and for the setting up or the switchingsff of the system.

While the above description with reference to the drawings is referred to a security system, it will be appreciated that the system can be used to monitor detectors for detecting any conditional change such as fire detectors or industrial process detectors. The system allows the identification and processing of detector operation.

Claims (23)

1. A detector system comprising at least one loop containing two or more electrically connected detectors, each detector of the or each loop being operable to alter an electrical parameter of the associated loop by an amount or to a value which differs from the alteration or value produced by the or each other detector of the loop, a memory for storing signals representative of the alteration in or the value of the electrical parameter on operation of each detector, and a control system for repeatedly measuring said electrical parameter of the loop, for comparing the measured value of the parameter with the stored signals and, if a detector has been actuated, for producing an alarm signal.

2. System according to claim 1 wherein the control system produces an output identifying the actuated detector.

3. A system according to claim 2 wherein the output is in the form of a visual display.

4. A system according to any one of claims 1 to 3, wherein the detectors of the or each loop are so arranged that the operation of each or any combination of detectors produces an alteration in or a value of said electrical parameter of the loop which is different from the alteration or value produced by another detector or combination thereof, the memory storing signals representative of the alterations or values produced by operation of each or any combination of detectors, and, when more than one detector is operated, the control system providing an output identifying each of the detectors operated and the alarm signal.

5. A system according to any one of claims 1 to 3 wherein the detectors of the or each loop are so arranged that the operation of each detector or of any two or more detectors produces an alteration in or a value of said electric parameter which is different from the alteration or value produced by any other or any two or more detectors, said memory storing signals representative of the alterations produced by operation of each or any two or more of the detectors and when any one or more detectors are operated, the control system providing an output indicating such operation and the alarm signal.

6. A system according to any one of claims 1 to 5 wherein each detector comprises an electric resistance which is short or open circuited when the detector is inoperative and which is introduced into or removed from the loop on operation of the associated detector to alter the electrical resistance of the loop.

7. A system according to any one of claims 1 to 6 wherein the or each loop is connected to a monostable circuit of the control system whose pulse duration, when set, varies in dependence on the value of the resistance in the loop, the control system periodically triggering the monostable circuit and producing a signal which is representative of the time period for which the monostable circuit is set and which is thus representative of the resistance of the loop.

8. A system according to claim 7 wherein the control system includes a constant frequency clock and wherein after the monostable circuit has been triggered, the control system enters a routine, under the control of the clock, in which the monostable circuit is periodically examined, and each time the monostable circuit is set, a first register is incremented, said incrementation being halted when examination of the monostable circuit reveals that said circuit is unset to leave, in the first register, a count representative of the resistance of the loop.

9. A system according to claim 8 wherein a second register is provided which has a bit location which is incremented and decremented to trigger the monostable circuit and also has a sign bit location whose bit entry changes when the monostable circuit is set, the control system testing periodically the contents of the sign bit location and incrementing the first register each time an entry in the sign bit location is detected which corresponds to the monostable circuit being set.

10. A system according to any one of claims 7 to 9 wherein the monostable circuit includes a coupling formed by capacitive and resistive elements to provide a minimum duration pulse when all the detectors are short circuited, the memory holding a signal corresponding to said minimum pulse duration under nominal ambient conditions of the system and the control system, when no detector is operated, periodically comparing the measured value of the duration of the minimum pulse with the nominal value of said duration, storihg an error signal representative of the difference between said durations and using said error signal to apply a correction to the duration of the measured monostable circuit pulse when a detector is operated to compensate for drift in the nominal condition of the system.

11. A system according to any one of claims 7 to 10 wherein two or more loops are provided and are connected in parallel to the control system.

1 2. A system according to claim 11 wherein a single monostable circuit is provided which is switched between the loops by the control system.

1 3. A system according to claim 11 wherein a monostable circuit is provided for each loop and the control system switches between the inputs and outputs of the monostable circuits.

14. A system according to any one of claims 11 to 1 3 wherein selection means are provided for rendering operative any one or any combination of said loops or said detectors.

1 5. A system according to any one of claims 1 to 14 wherein the control system includes a microprocessor read only memory (ROM) connected to the microprocessor for storing programmes of operations to be conducted by the control system, a random access memory (RAM) also connected to the microprocessor for storing intermediate values and a peripheral interface adaptor for delivering control system outputs and for receiving signals corresponding to the measured value of the parameter.

16. A system according to claim 15 when dependent on claim 8 or any claim 9 dependent thereto, wherein the first register is an index register of the microprocessor, the second register being a register of the peripheral interface adaptor and the clock being the clock of the microprocessor.

1 7. A system according to claim 1 5 or claim 1 6 wherein the or each loop and/or the control system may be testable to determine whether they have been tampered with and in this case ROM may contain a programme for periodically testing the or each loop and/or the control system and for producing an alarm signal when tampering is detected.

18. A system according to any one of claims 1 5 to 1 7 wherein there is provided a telephone interface system with the ROM containing a programme for connecting a source of information to at least one designated telephone receiver on operation of a detector and for then activating said source of information to pass said information to said least one designated receiver.

1 9. A system according to any one of claims 1 5 to 1 8 wherein the ROM contains a programme for allowing a predetermined sequence of detectors to be activated in a predetermined time interval without producing an alarm signal both when the system is rendered operative and before the system is rendered inoperative to allow, respectively, exit and entry of an operative past said detectors.

20. A system according to any one of claims 1 5 to 1 9 wherein at least one loop contains more than one detector protecting the same zone and wherein the ROM contains a programme for producing an alert signal when a first of said more than one detectors is operated and for producing the alarm signal only when a predetermined number of the remainder of said more than one detectors are operated.

21. A system according to claim 19 wherein said ROM programme produces a warning signal different from said alarm signal during said predetermined time interval.

22. A system according to any one of claims 1 to 21 wherein the system is a security system for detecting unauthorised movement into and out of a zone or area.

23. A security system substantially as hereinbefore described with reference to the accompanying drawings.