GB2080024A - Semiconductor Device and Method for Fabricating the Same - Google Patents
Semiconductor Device and Method for Fabricating the Same Download PDFInfo
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- GB2080024A GB2080024A GB8119691A GB8119691A GB2080024A GB 2080024 A GB2080024 A GB 2080024A GB 8119691 A GB8119691 A GB 8119691A GB 8119691 A GB8119691 A GB 8119691A GB 2080024 A GB2080024 A GB 2080024A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 230000002093 peripheral effect Effects 0.000 claims abstract description 61
- 239000012535 impurity Substances 0.000 claims abstract description 38
- 238000009413 insulation Methods 0.000 claims abstract 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 70
- 230000003647 oxidation Effects 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 12
- 239000004020 conductor Substances 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 83
- 229910052681 coesite Inorganic materials 0.000 description 40
- 229910052906 cristobalite Inorganic materials 0.000 description 40
- 229910052682 stishovite Inorganic materials 0.000 description 40
- 229910052905 tridymite Inorganic materials 0.000 description 40
- 229920002120 photoresistant polymer Polymers 0.000 description 35
- 239000000377 silicon dioxide Substances 0.000 description 28
- 235000012239 silicon dioxide Nutrition 0.000 description 28
- 238000005468 ion implantation Methods 0.000 description 22
- 108091006146 Channels Proteins 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 21
- 229910015900 BF3 Inorganic materials 0.000 description 15
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 14
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- 150000002500 ions Chemical class 0.000 description 7
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- 239000002784 hot electron Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
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- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- -1 BF2 ion Chemical class 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Abstract
An EPROM semiconductor device consists of a memory portion (I) and a peripheral circuit portion (II), each having formed on one main surface of a semiconductor substrate (15) a field portion consisting of a thick first insulation film (14a, 14b), an active region encompassed by the field portion and a gate layer (CG, FG; G) formed in the active region over a second insulation film (16a, 16b) thinner than the thick first insulation film (14a, 14b). A semiconductor layer (18, 19) having the same conduction type as that of the semiconductor substrate (15) but a higher impurity concentration is formed on the semiconductor substrate below the thick first insulation film (14a, 14b) of each field portion of each of the memory portion and the peripheral circuit portion, and the semiconductor layer (18) extends at least from the field portion (14a) of the memory portion (I) to a part of the active region of the memory portion. <IMAGE>
Description
SPECIFICATION
Semiconductor Device and Method for
Fabricating the Same
This invention relates broadly to a
semiconductor integrated circuit device. More
particularly, the present invention relates to an electrically programmable read only memory
device (hereinafter referred to as "EPROM device") and also to a method of fabricating the same.
The EPROM devices in general comprise a
memory array portion consisting of a plurality of
MIS (Metal Insulator Semiconductor) type
memory transistors, and a peripheral circuit
portion consisting of a plurality of MIS type
transistors formed around the peripheries of the
memory array portions (hereinafter referred to as
the "peripheral transistors"). The MIS type
memory transistors of the memory array portion
each consist of floating gate electrodes formed on
the main surface of a semiconductor substrate
and control gate electrodes formed on the gate
electrodes. The peripheral circuit portions consist
of input/output circuits, decoder circuits, and the
like.
The transistors and peripheral transistors in
these EPROM devices are commonly fabricated in
accordance with the following method. First, a
thick oxide film (hereinafter referred to as a "field SiO2") is selectively formed on the surface of the
semiconductor substrate. A gate electrode
consisting of polycrystalline silicon (poly-Si) or
the like is then formed over the surface of a part
of the semiconductor substrate encompassed by
the abovementioned field SiO2 (hereinafter
referred to as an "active region") on a layer of thin gate Six2. Using the abovementioned gate electrode and field SiO2 as the mask, a source region and a drain region are subsequently formed on the surface of the abovementioned active region.
As a method of writing electric information in
the abovementioned EPROM, there is heretofore
known a method which first brings the MIS type
memory transistors into the pinch-off state and then writing the carrier (hot electrons) inside the semiconductor substrate to the floating gate
electrode on the active region, as disclosed by
IEEE Journal of Solid-State Circuits, Vol. SC-7,
No. 5, October 1972 and Japanese Patent Laid
Open No. 102475/1976, for example.
However, the inventors of the present
invention have discovered that, in the
abovementioned information writing method, the writing speed can be improved by forming a high
impurity concentration region having the same
conduction type as the substrate at the periphery of the semiconductor substrate in the channel direction below the gate SiO2 of the memory transistor.
The reason why the writing speed can be
improved may be assumed that when a sourcedrain current flows, the efficiency of occurrence of the hot electrons is improved due to the high impurity concentration region and thus promotes the writing speed. More particularly, the high concentration impurity region restricts extension of the depletion layer thereby to strengthen the electric field at the pinch-off point so that the efficiency of occurrence of hot electrons and the writing speed are promoted.
As a method of forming the high impurity concentration region in the channel portion, the inventors of the present invention have devised a method which introduces the impurity into the active region using a suitable mask after the gate oxide film is formed. However, subsequent studies have revealed that this method is not free from the following drawbacks.
(1) If mask alignment is not made correctly, the position of the high impurity concentration region deviates so that the writing efficiency varies.
(2) The integration density can not be improved in view of the mask error.
On the other hand, it is desired to keep the impurity concentration on the substrate surface near the channel portion as low as possible in order to prevent a decrease in junction capacity and to improve the reverse voltage capacity of the peripheral transistors. Especially when p-type region is formed as a channel stopper in the above-mentioned high impurity concentration region, problems occur such as an increase in the junction capacity and a lowering of the reverse voltage capacity of the peripheral transistor.
The present invention provides a development in such semiconductor devices and methods of making them, as defined in the appended claims.
In the accompanying drawings:
Figure 1 is a plan view showing one cell of a memory MIS transistor in accordance with an embodiment of the present invention; Figure 1 A is a section view taken along line A-A' of Figure 1;
Figure 1 B is a section view taken along line B-B' of Figure 1; Figure 2 is a plan view diagrammatically showing the EPROM device in accordance with the embodiment of the present invention; Figure 3 is a section view taken along line A-A' of Figure 2; Figure 4 shows a modified embodiment of Figure 3; Figure 5 is a plan view showing the EPROM device in accordance with the present invention;Figures 6(a) through 6(e), 7(a) through 7(e), 8(a) through 8(e) and 9(a) through 9(e) are sectional views showing by steps the fabrication method of the present invention applied to the EPROM device; and Figures 1 O(a) through 1 O(p) are sectional views, each showing by steps the method of the present invention when applied to various MIS transistors of the
EPROM device.
Example 1
Figures 1A and 1 B show an example of an MIS type memory transistor in an EPROM device in accordance with the present invention. In the drawings, reference numeral 1 represents a semiconductor substrate (impurity concentration 1015 atoms/cm3) consisting of P-Si single crystal.
On one main surface of this substrate is formed a thick field SiO2 (silicon oxide) film 2. A thin gate
SiO2 film 3 is formed on the surface of a Psubstrate surface of a portion encompassed by the field SiO2 film, using the portion as the active region. A floating gate (FG) electrode 4 consisting of a conductive poly-crystalline silicon (hereinafter referred to as "poly-Si") layer is formed as the first layer on this gate SiO2 film. A control gate (CG) electrode 6 consisting of a conductive poly-Si layer as the second layer is formed over the floating gate on an inter-layer insulating film 5.As shown in Figure 1 B, sourcedrain consisting of an n+ diffusion layer 7 are formed on the substrate surface between each gate electrode, and an aluminum electrode (wiring) 8 coming into ohmic contact with this n+ diffusion layer 7 is so formed over the diffusion layer 7, on an interlayer insulating film 9, as to orthogonally cross the extending direction of the gate above the gate electrode. In the abovementioned MIS type memory transistor, a high concentration p+ layer 10 having the same conduction type as that of the substrate is embedded immediately below the field SiO2 film 2 and a part 1 Oa extends along the peripheral portion of the gate SiO2 film 3 which is to serve as the channel portion.
In the abovementioned MIS type memory transistor, since the p+ layer extends in the channel peripheral portion immediately below the field SiO2film, the efficiency of occurrence of the hot electrons becomes improved and the writing speed is greatly increased when a source-drain current flows.
Figure 2 diagrammatically illustrates an
EPROM device as a whole to which the present invention is applied. In one semiconductor chip 11, reference I represents a memory mat (array)
portion on which a plurality of MIS type memory transistors 12 are disposed. Reference II
represents a peripheral circuit portion which
consists of a plurality of MIS transistors 13 of
varying types. The active region of each MIS
transistor is encompassed by a field portion
consisting of a thick SiO2 film, and various wirings
are disposed in such a manner as to bridge over
the field portion. A p type impurity is introduced
into the semiconductor surface immediately
below the SiO2 film of the field portion in a
concentration higher than that of the substrate
which is to generally serve as the channel
stopper.As shown in the drawing, in accordance
with the present invention, the p+ layer is
disposed at least on the semiconductor substrate
surface immediately below the field 5102 film of
the memory portion, and a part of the p+ layer
extends to the channel peripheral portion. As the
memory portion and the peripheral circuit portion
are associated with each other in this manner, the
following embodiment can be accomplished.
Example 2
In Figure 3, reference numeral I represent a
memory mat portion and II represents each MIS
type transistor of a peripheral circuit portion. Each
MIS type transistor has a gate electrode FG,G that is composed of poly-Si and is formed on gate SiO2 films 1 6a, 1 6b over the surface of a psemiconductor substrate 15 in the active region encompassed by thick field SiO2 films 1 4a, 1 4b.
Especially, the transistor of the memory mat portion has two-layered electrodes FG, CG and an inter-layer insulating film 17. A p+ layer 18 having a high impurity concentration (surface concentration N:1 013 atoms/cm2) is formed on the surface of the p semiconductor substrate immediately below the field SiO2 film on the memory side I, and extends to the channel peripheral portion of the active region. On the side of the peripheral circuit II, a p+ layer 19 is formed on the surface of the semiconductor substrate immediately below the field SiO2 film, but its end portion does not extend to the active region.
In accordance with this embodiment of the present invention, the writing efficiency of the
EPROM is improved because the p+ layer 18 immediately below the field 5102 film exists on the memory side. On the other hand, on the side of the peripheral circuit, the p+ layer 19 immediately below the field portion serves as the channel stopper, but since the active region and the p- substrate surface near the active region are kept at a low concentration, the capacitance can be kept small while the withstand voltage can be made great. Thus, an improvement in the density of integration can be attained by reducing the channel width.
Example 3
In Figure 4, the construction of each MIS transistor, including both the memory mat portion represented by reference numeral I and the peripheral circuit portion represented by reference numeral II, is the same as that of Example 2 (Figure 3). On the memory side I, a p+ layer 18 having a high impurity concentration is formed on the surface of a p semiconductor substrate immediately below the field SiO2 film in the same way as in Example 2, and it extends to the channel peripheral portion.On the peripheral circuit portion II, on the other hand, a p layer 20, which has a concentration higher than that of the substrate but is lower than that of the p+ layer of the field portion on the memory side (i.e., surface concentration N:10t3 atoms/cm2), is formed, but the edge portion of this p layer does not extend up to the active region.
In accordance with this embodiment of the present invention, the writing efficiency of the
EPROM is improved because the p+ layer of the field portion extends to the channel peripheral portion on the memory side, and on the side of the peripheral portion circuit portion, on the other hand, the p layer of the field portion serves as the channel stopper, but since the active region and the semiconductor substrate surface near the active region are kept at a low concentration, the capacitance is small while the withstand voltage can be increased. Thus, density of integration can be increased by reducing the channel width.
Figure 5 shows the layout of the EPROM device as a whole, wherein reference I represents an MIS type memory mat portion and reference numeral il represents a peripheral circuit portion and the device consists of a write circuit 21, an X decoder 22, a Y decoder 23, an address 24, a sense amplifier 25, and so forth. In this drawing, the portion encompassed by dot-and-chain line (represented by hatching) includes the p+ layer 18 in the memory mat portion and the portion immediately below the field portion near the memory mat portion as shown in I of Figures 3 and 4, while the remaining peripheral circuit portion includes a p+ layer 19 or a p layer 20 that is formed immediately below the field portion so as not to extend into the active region, as shown in II of Figures 3 and 4.
Next, the method of fabricating the EPROM in accordance with the present invention will be described in detail with reference to the following.
Examples.
Example 4
Figures 6(a) through 6(e) show an example of the fabrication method of the EPROM device in accordance with the present invention and depict the principal portions of the process employing the Si3N4 (silicon nitride) double work (double bombardment of B+) system. In the drawing, reference numeral I corresponds to the memory mat side and II to the peripheral circuit portion side.
(a) Thermal oxidation of a p-Si substrate 26 is effected to form a thin S102 film 27 on the entire main surface of the substrate. Next, an Si3N4 film 28 is deposited. A part of the Si3N4 film is selectively removed by etching on the I side using a photoresist mask 29 with the II side being left as it is. Thereafter, B+ a high concentration (N:1 x 1 0'4/cm2) of (boron) ions are implanted in the surface of the p Si substrate in through the S102 film. In this example, B+ is not implanted to the II side.
(b) A p+ layer 30 is formed on the surface of the substrate by extending and diffusing the boron, implanted into the Si substrate by an annealing treatment at about 1,1 000C in a N2 (nitrogen) atmosphere. In this instance, a part 30a of the p+ layer is extended in the transverse direction up to a portion below the 5i3N4 film that is to become the channel periphery.
(c) A photoresist treatment is then carried out to cover the entire surface with the photoresist film 31 on the I side. A part of the Si3N4 film on the II side is removed by etching by use of a photoresist film 31 a partially disposed, and ion implantation of B+ ion in Figure 2 is effected while leaving the photoresist film as it is. The B+ quantity to be implanted in this case is in a lower concentration than in the case of the B+ implantation in Figure 1.
(d) After removal of the photoresist, selective oxidation is carried out using the Si3N4 film as the mask in order to form a thick oxide film (field 5102 film) which is to function as the field portion. At the time of oxidation, the p+ layer 30 on the I side further extends into the active region to attain d=approx. 0.5,u. On the II side, on the other hand, the implanted B is extended and diffused to form a p layer 33, but since this p layer 33 has a low concentration, it hardly extends to the active region.
(e) Subsequently, the Si3N4 film is removed by etching, and the thin 5102 film of the active region is removed. After gate oxidation is effected, a thin gate S102 film 34 is formed, thereby forming a gate electrode 35 of the first layer by depositing poly-Si of the first layer and by pattern-etching.
In accordance with the method of the present.
invention described in this Example 4, Si N is patterned twice separately, and the resist mask used thereby is as used as the mask for the B+ ion implantation (p+ ion-implantation peripheral circuit, field ~ ion implantation). Accordingly, it becomes possible to introduce boron in a well controlled manner by setting the implantation energy to 30 to 70 KeV. Thus, in accordance with the present invention, since self-alignment between the field 5102 film and the p+ layer can be accomplished, there is no need to take into account the tolerance for mask alignment for the pe layer. Accordingly, the p+ region can be formed in a miniature size and with extremely high accuracy, and the production yield can be markedly improved.
Example 5
Figures 7(a) through 7(e) show another embodiment of the method of fabricating the
EPROM device in accordance with the present invention and illustrate the principal processes when BF2 (boron fluoride) is used for the impurity ion implantation for the p+ layer and the portion immediately below the field 5102 film.
(a) Thermal oxidation of a p-Si substrate 26 is effected to form a thin 5102 film 27 over the entire main surface of the substrate. Next, an Si N film 28 is deposited, and a part of each the memory mat side (I) and the peripheral circuit side (II) are removed by etching with a photoresist mask 29.
(b) The photoresist used as the 5i3N4 etching mask is removed and a new photoresist mask 31 is formed. The I side is etched while leaving the photoresist on only the II side. In this state, BF+2 (boron fluoride) ion is implanted in a high concentration in order to introduce BF2 into the substrate surface below the 5102 film in the portion of the I side that is not covered with the
Si3N4 film.
(c) Thereafter, the photoresist film is removed and the annealing treatment is carried out in the atmosphere of an inert gas so that BF2 on the substrate surface on the I side is extended and diffused to form a p+ layer 30. A part of this p+ layer 30 extends to the substrate surface below the Si3N4 film.
(d) NF2 ion is implanted in a low concentration over the entire surface to introduce BF2 into the substrate surface on the II side and into the substrate surface on the I side on which the p+ layer 30 is formed.
(e) Field oxidation is effected to form a thick 5102 film 32 on the substrate surface not covered with the 513N4 film. Due to the heat -treatment for the oxidation, BF2 introduced into the substrate surface is diffused into the substrate. Accordingly, the high concentration p+ layer 30 extends deep below the field SiO2 film on the I side into the active region, while on the II side the low concentration p layer 33 is formed but hardly extends into the active region.
The method of the present invention described in this Example 5 uses BF2 for the impurity ion implantation to form the p+ layer 30 and the p layer 33. Comparing their masses, BF2 is at least four times heavier than B: the mass of B is 11 and of BF2 is 49. For this reason, the ion permeability of BF2 is lower than that of B. In the case of B, SiO2~Si3N4 as well as a sufficiently thick (6000 ) photoresist film are necessary in order to prevent ion permeation, but ion permeation can be prevented by SiO2~Si3N4 alone in the case of
BF2. When B is used, the ion can permeate through the channel portion unless the ion implantation energy is below 20 KeV, the result being an increase in Vth.In ion implantation apparatuses available at present, however, it is not possible to implant the ion at an energy of below 20 KeV in a well controlled manner. On the other hand, when BF2 is used, the iniplantation energy can be raised up to about 60 KeV and so is much more controllable. According to the method of the present invention, therefore, self-alignment between the field 5102 film and the p+ layer can be accomplished and, at the same time, a memory cell of a miniature size can be produced with high accuracy and a high production yield.
Moreover, there is no need to take deviation of the mask alignment into account because the work is effected only once.
Example 6
Figures 8(a) through 8(e) show another embodiment of the method of fabricating the
EPROM device in accordance with the present invention and illustrate the principal process steps using a system with a single impurity ion implantation.
(a) Thermal oxidation of a p-Si substrate 26 is effected to form a thin 5102 film 27 over the entire surface of the substrate, and an SIN film 28 is then deposited. A part of the Si3N4 film each on the memory side (I) and the peripheral circuit side (II) is selectively removed by etching with a photoresist mask 29.
(b) The entire surface of the peripheral circuit side (II) is covered with a new photoresist film 31, and the exposed 5102 film 27 on the memory side (I) is removed by etching.
(c) After the photoresist film 31 is removed, oxidation is effected to form an 5102 film 36 about 500 A thick on the substrate surface of the memory side (I). At the same time, another oxidation is applied to the original SiO2 film on the peripheral circuit side (II), to increase the thickness of the SiO2 film 37 to 1,000 A.
(d) B or BF2 ion implantation is hereby effected.
By suitably selecting the implantation energy in this instance, B is introduced in a concentration of about 7x 1013 atoms/cm2 below the field 5102 film of the memory portion and about 4x 1012 atoms/cm2 below the field SiO2 film of the peripheral circuit portion. Thus, impurity diffusion having different concentrations between the memory portion and the peripheral circuit portion can be carried out by a single ion implantation step.
(e) Thereafter, N2 annealing is effected or selective diffusion using the S13N4 film as the mask is effected, thereby forming a field 5102 film 32. A p+ layer 30 and a p layer 33 having concentrations different from each other are formed at the same time in the memory portion and the portion below the field 5102 film of the peripheral circuit portion. In this case, the p+ layer 30 below the field 5102 film in the memory portion extends laterally up to and below the channel peripheral portion.
In accordance with the method of the present invention described in this Example 6, the p+ layer and the p layer can be formed by a single ion implantation treatment, and self-alignment between the field 5102 film and the p+ layer can be accomplished. At the same time, the impurity concentration control can be easily made by changing the thickness of the 5102 film. Hence, a memory cell having a miniature size can be produced with extremely high accuracy and at a high production yield.
Example 7
Figures 9(a) through 9(e) show another embodiment of the method of fabricating the
EPROM device in accordance with the present invention, and illustrate the principal process steps in accordance with a system which carries out surface oxidation twice and impurity ion implantation once.
(a) A thin 5102 film 27 is formed on the entire surface of a p~Si substrate 26 and the 5102 film on the memory side (I) is removed by etching after the peripheral circuit side (II) is covered with a photoresist film 38.
(b) The photoresistfilm is removed and surface oxidation is effected so that a 500 A-thick 5102 film 36 is formed on the surface of the memory (I) while the thickness of the 5102 film on the peripheral circuit side (II) is increased to 1000 A.
(c)ASi3N4 film is deposited on the entire surface, and using a new photoresist film 29 as the mask, a part of the 513N4 film is selectively
removed on the sides of (I) and (II). Thereafter, without removing the photoresist mask, B+ ion implantation is effected to introduce B into the Si surface below the 5102 film. In this ion
implantation, the quantity of B introduced varies between (I) and (II) due to the difference in thickness of the 5102 films 36 and 37.
(d) After the photoresist film is removed, annealing is effected in the N2 atmosphere so as to extend B introduced into the Si substrate surface. in this case, on the (I) side, into which a greater quantity of B was introduced, B is diffused in the transverse direction so that a part of the p+ layer 30 extends to the channel peripheral portion.
(e) Field oxidation is effected to form a thick
SiO2 film 32 on the portion not covered with the S13N4 film.
In accordance with the method of the present invention described in this embodiment, it is possible to use a photoresist mask for the ion implantation in order to form the p+ layer on the memory side, and to simultaneously implant the p type impurity while varying its quantities between the memory side and the peripheral circuit side.
Thus, the number of production steps can be reduced.
Example 8
Next, the method of fabricating the EPROM device including its peripheral circuit will be described with reference to a definite embodiment thereof by use of sectional views of
Figures 1 0(a) through 10(p), showing by steps the fabrication procedure.
(a) A 1,000 thick SZO2 film 41 is formed on the surface of a p type Si single crystal substrate 40 by thermally oxidizing the surface. Further, an approx. 1 500 A thick S13N4 (silicon nitride) film 42 is formed on the surface of this S102 film 41.
(b) In order to form a p+ type channel stopper inside the substrate surface which is to serve as an insulating isolation portion, the abovementioned Si3N4 film 42 is selectively removed by etching using resist film 43 as the mask. Of the regions still covered with the Si3N4 film in Figure 10(b), I is used for producing an MIS type memory transistor while IIA,IIB and llc are used for producing an enhancement type MIS transistor IIA, a depletion type MIS transistor IIB and a high withstand voltage enhancement type
MIS transistor llc, respectively.
(c) The entire surface of the peripheral circuit side (IIAIIIB.IIC)~S covered with a new photoresist film 44 and the SiO2 film not covered with Si3N4 on the memory side (I) is selectively removed by etching to expose the Si substrate 40.
(d) After the abovementioned photoresist film 44 is removed, oxidation treatment is carried out to form an about 500 thick S102 film 45 on the substrate surface on the memory side (I) while oxidation acts upon the surface of the field S102 film of the portion not covered with the Si3N4 film on the peripheral circuit side so that a 1,000 A- thick S102 film 46 is formed.
(e) Using the Si3N4 film as the mask, B or BF2 ion is implanted into the Si substrate surface through the S102 film. By selecting suitable ion implantation energy, the relatively high concentration of impurity, i.e., 1013 atoms cm~2, is introduced into the portion below the 5102 film of the memory portion (I) not covered with Si3N4, while an impurity concentration of 4x 1012 atoms cm~2 is introduced into the portion below the S102 film of the peripheral circuit portion (IIA,IIB,IIC) by the same single implantation treatment.When N2 annealing is then effected, the impurity introduced into the portion below the S102 film is extended into Si, thereby forming a p+ layer 47 or a p layer 48. On the memory side (I), however, since the impurity in a high concentration is introduced, there is formed a p+ layer 47a that extends under and up to the Si substrate surface which is covered with
Si3N4 and is to serve as the active region.
(f) Thereafter, the substrate 40 is heated in the oxidizing atmosphere so that the substrate surfaces on which the SI3Nd film is not formed is oxidized and insulating isolation 5102 films (hereinafter referred to as the "field 5102 film") 49a, 49b, 49c,... are formed in a thickness of about 12,000 A. Below these field 5102 films, B introduced by the aforementioned ion implantation exists as p+ (p) type channel stoppers 47, 48.
(g) The Si3N4 film 42 and the thin SiO2 film 41 therebelow are removed completely by etching to expose the Si substrate surface, and the substrate surface thus exposed is thermally oxidized thereby to form about 800 thick gate 5102 films 50a, SOb, ....... In order to control the threshold voltage values of the memory transistor, the peripheral transistors and especially that of the enhancement type transistor to desired values, B is introduced into the substrate surface by the ion implantation method through the gate S102 films.
The ion implantation energy in this case is about 70 KeV. Since the field SiO2 film is formed sufficiently thick as mentioned above, B is not introduced into the substrate surface immediately below this field S102 film.
(h) An n-type determining impurity such as P (phosphorous) is implanted to a part of the substrate surfaces of the depletion MIS transistorforming portion (rib) and the high withstand voltage enhancement transistor-forming portion (II & through the gate SiO2 films 50c and 50d, using a photoresist film 51 as the mask, thereby forming an n type channel region 52 ans an n type region 53, respectively. Suitable ion implantation energy is about 120 KeV. The surface impurity concentration of the n regions 52 and 53 thus formed is about 1012 atoms/cm2.
(i) After the photoresistfilm 51 is removed, a 3,500 thick polycrystalline silicon layer 54 is formed on the substrate 40 by a CVD (Chemical
Vapor Deposition) process in order to form the floating gate electrode of the memory transistor, the gate electrode of the peripheral transistor and other necessary wiring layers. This polycrystalline
Si layer 54 is selectively etched (patterned) using a photoresist film 55 as the mask, thereby forming the floating gate (GF) of the memory transistor, the gate electrodes G1, G2, G3 and the wiring layer L1. A conduction type-determining impurity is not contained in the polycrystalline Si layer, the gate electrodes GF, G1 G2, G3, or the wiring layer L, at this time.If the impurity exists inside the polycrystalline Si layer before patterning of the polycrystalline Si layer 54, contamination is likely to occur at the states of deposition of the photoresist film 55, selective removal of the photoresist film, and patterning of the polycrystalline Si layer 54, resulting in adverse influences upon the memory characteristics of the memory transistor, and the like.
(j) After the photoresist film 55 is removed, P (phosphorus) is introduced into the gate electrodes GF, G1, G2, G3 and the wiring layer L1, each consisting of the polycrystalline Si layer, in order to reduce resistance of the layer and electrodes. Thereafter, the substrate is subjected to the heat treatment in the oxidizing atmosphere.
As a result, the surfaces of the gate electrodes and the wiring layer are oxidized and 1600 A- thick 5102 films 56a, 56b, 56c, etc., respectively are formed on these surfaces. These 5102 films serve as the inter-layer insulating films.
(k) After the abovementioned step (j) is carried out, second polycrystalline Si layers 57a and 57b are formed on the substrate by the CVD process.
The thickness of this polycrystalline Si layer is about 3,500 A. Furthermore, a conduction typedetermining impurity does not exist in the polycrystalline Si layer. Thereafter, the 5102 film, the polycrystalline Si layer and the gate 5102 film are sequentially and selectively etched at the portions not shown in the drawing with a photoresist film 58 as the mask, thereby forming the control gate CG and the floating gate FG of the memory transistor.
(I) After the photoresist film 58 is removed, P is introduced into the polycrystalline Si layer and the control gate electrode CG. Then using a new photoresist film 59 formed as the mask, the polycrystalline Si layers 57a and 57b are selectively patterned in order to form wiring layers
L2, L3 for mutual connection of the peripheral transistors and an offset gate electrode G4 of the high withstand voltage MIS type transistor (ilk).
Furthermore, the exposed 5102 films 56b, 56e and the gate 5102 films 50b, 50c, etc. are completely removed by etching.
#m) After the photoresist film 59 is removed, P
(phosphorus) is deposited to the exposed substrate surface 40 and it is further subjected to extension diffusion, thereby forming n+ source and n+ drain regions (see Figure 1 B) in the portion of the memory portion (I) which is not shown.
On the peripheral circuit side, nf source regions S S S and no drain regions D1, 2
1' 2' 3 drain regions D D and D3 are formed as shown in the drawing. The depth of these n+ regions is 1 y and the surface impurity concentration is 1018 atoms/cm2. Further, the surfaces of the gate electrodes (CG, G1, G2, G3, G4) are exposed at a low temperature of 8000C in an oxidizing atmosphere, wiring layers (L2, L3), the source region and the drain region are oxidized.
The thickness of the 5102 films 60a, 60b formed on the surfaces of these electrodes, wiring layers and regions is about 1,200 .
(n) In order to attach the electrodes, the 5102 film on the source and drain regions is selectively removed by etching using the photoresist film as the mask.
(o) After the photoresist film 61 is removed, a
PSG (phosphosilicate glass) film 62 is formed on the substrate. This PSG film 62 has a thickness of about 8,000 A. Using the photoresist film 63 as the mask, this PSG film 62 is selectively etched to create contact holes H1, H2,... and so forth.
(p) After the photoresist film 63 is removed, Al (aluminum) is vacuum-deposited to the substrate and is patterned to form a wiring layer 64. Though not shown in the drawing, the Al wiring layer the source-drain region of the memory MIS transistor and extends orthogonally to the drawing (see
Figures 1 and 1 B). The gate electrodes G3 and G4 of the high withstand voltage enhancement type
MIS transistor are connected by the abovementioned Al wiring layer. After the abovedescribed steps are carried out, there can be obtained the memory MIS transistor QM as the memory portion (I) and the enhancement type
MIS transistor QE1' the depletion type MIS transistor QD, and the high withstand voltage enhancement type MIS transistor QE2 as the peripheral portion, as shown in the drawing.
As described in the foregoing Example 6, the principal action and effect of the present invention reside in that the p+ layer and p layer below the field 5102 film can be formed by a single ion implantation treatment and self-alignment between the field 5102 film and the p+ layer can be accomplished, as described in the foregoing embodiments.
Claims (12)
1. An MIS semiconductor device including: a semiconductor substrate having one main surface; a thick first insulation film formed on said one main surface of said semiconductor substrate; semiconductor regions encompassed by said thick first insulation film; and a conductor layer formed over said semiconductor regions on a second insulation film thinner than said first thick insulation film; and a high impurity concentration semiconductor layer having the same conduction type as that of said semiconductor substrate formed on said semiconductor substrate below said thick first insulation film, a part of said semiconductor layer extending to the surface of said semiconductor region having said thin second insulation film.
2. A semiconductor device consisting of a memory portion and a peripheral circuit portion, each having formed on one main surface of a semiconductor substrate a field portion consisting of a thick first insulation film, an active semiconductor region encompassed by said field portion, and a conductor gate layer formed over the active region on a second insulation film thinner than said thick first insulation film, and a semiconductor layer having the same conduction type as that of said semiconductor substrate but a higher impurity concentration than that of said semiconductor substrate formed on said semiconductor substrate below said thick first insulation film of each field portion of each of said memory portion and said peripheral circuit portion, said semiconductor layer extending at least from said field portion of said memory portion to a part of said active region of said memory portion.
3. A semiconductor device according to claim 2 wherein said semiconductor layer formed on said semiconductor substrate below said thick first insulation film of said field portion in said memory portion and having the same conduction type as that said substrate has an impurity concentration higher than that of said semiconductor layer formed on said semiconductor substrate below said thick first insulation film of said field portion in said peripheral circuit portion and having the same conduction type as that of said semiconductor substrate.
4. A semiconductor device according to claim 1 or claim 2 wherein said semiconductor substrate consists of silicon single crystal.
5. A semiconductor device according to claim 1 or claim 2 wherein each of said first and second insulation films consists of a silicon oxide film.
6. A semiconductor device according to claim 1 or claim 2 wherein said conductor layer formed over said semiconductor region consists of a polycrystalline silicon layer.
7. A semiconductor device according to claim 1 or claim 2 wherein said semiconductor substrate is of a p-type.
8. A method of fabricating a semiconductor device which has a memory portion at a part of one main surface of a semiconductor substrate and a peripheral circuit portion at another part, the method including the steps of: forming a thin oxide film over the entire surface of one main surface of said semiconductor substrate; forming a film of an oxidation-resistant material on said oxide film on said one main surface at the portion at which said memory portion is to be formed and on said oxide film at the portion at which said peripheral circuit portion is to be formed; selectively removing said oxidation-resistant material film from said oxide film at the portion at which said memory portion is to be formed; introducing an impurity of the same conduction type as that of said substrate into said semiconductor substrate using said first oxidation-resistant material film as the mask and extending and diffusing said impurity; selectively removing said oxidation-resistant material film on said oxide film at the portion at which said peripheral circuit portion is to be formed; introducing an impurity of the same conduction type as that of said semiconductor substrate into said semiconductor substrate using said second oxidation-resistant material film as the mask; and forming a thick field oxide film on said one main surface of said semiconductor substrate at the portions not covered with said first and second oxidation-resistant material films.
9. A method of fabricating a semiconductor device which forms a memory portion at a part of one main surface of a semiconductor substrate and a peripheral circuit portion at another part, the method including the steps of: forming a thin oxide film over the entire surface of said one main surface of said semiconductor substrate; selectively forming first and second oxidationresistant material films on said oxide films in the portion of said one main surface at which said memory portion is to be formed and in the portion at which said peripheral circuit portion is to be formed, respectively; oxidizing said oxide film at the portion at which said peripheral circuit portion is to be formed so that the thickness of said oxide film at the portion at which said peripheral circuit portion is to be formed and which is not covered with said second oxidation-resistant material film is greater than that of said oxide film at the portion at which said memory portion is to be formed; introducing an impurity of the same conduction type as that of said semiconductor substrate into said semiconductor substrate using said first and second oxidation-resistant films as the mask; and forming a thick oxide film on said one main surface of said semiconductor substrate using said first and second oxidation-resistant material films as the mask.
10. A method of fabricating a semiconductor device which forms a memory portion at a part of one main surface of a semiconductor substrate and a peripheral circuit portion at another part, the method including the steps of: forming an oxide film on said one main surface of said semiconductor substrate at the portion at which said memory portion is to be formed and at the portion at which said peripheral circuit portion is to be formed so that the thickness of said oxide film at the portion at which said peripheral circuit portion is to be formed is greater than that of said oxide film at the portion at which said memory portion is to be formed; forming selectively first and second oxidation-resistant material films on said oxide films in the portions at which said memory portion and said peripheral circuit portions are to be formed, respectively; introducing an impurity of the same conduction type as that of said semiconductor substrate into said semiconductor substrate using said first and second oxidation-resistant material films as the mask; and forming a field oxide film on said one main surface of said semiconductor substrate using said first and second oxidation-resistant material films as the mask.
11. A semiconductor device substantially as described herein with reference to the drawings.
12. A method of fabricating a semiconductor device substantially as described herein with reference to the drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8786780A JPS5713772A (en) | 1980-06-30 | 1980-06-30 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2080024A true GB2080024A (en) | 1982-01-27 |
Family
ID=13926819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8119691A Withdrawn GB2080024A (en) | 1980-06-30 | 1981-06-25 | Semiconductor Device and Method for Fabricating the Same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5713772A (en) |
| DE (1) | DE3124283A1 (en) |
| GB (1) | GB2080024A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1984004852A1 (en) * | 1983-05-27 | 1984-12-06 | Ncr Co | Process for fabricating complementary and nonvolatile type devices on a common substrate |
| EP0160965A2 (en) * | 1984-05-07 | 1985-11-13 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device with a stacked-gate-electrode structure |
| EP0193841A2 (en) * | 1985-02-25 | 1986-09-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| FR2583920A1 (en) * | 1985-06-21 | 1986-12-26 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT AND IN PARTICULAR AN EPROM MEMORY COMPRISING TWO SEPARATE ELECTRICALLY ISOLATED COMPONENTS |
| EP0244367A2 (en) * | 1986-04-21 | 1987-11-04 | SGS MICROELETTRONICA S.p.A. | Mos type integrated semiconductor device with nonuniform thickness of gate oxide and process for fabricating it |
| US4780424A (en) * | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
| EP0390219A2 (en) * | 1989-03-31 | 1990-10-03 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5061654A (en) * | 1987-07-01 | 1991-10-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit having oxide regions with different thickness |
| EP0499985A2 (en) * | 1991-02-18 | 1992-08-26 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor memory device |
| US5158902A (en) * | 1989-04-28 | 1992-10-27 | Kabushiki Kaisha Toshiba | Method of manufacturing logic semiconductor device having non-volatile memory |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192067A (en) * | 1981-05-22 | 1982-11-26 | Hitachi Ltd | Erasable and programmable read only memory unit |
| JPS594170A (en) * | 1982-06-30 | 1984-01-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS60223945A (en) * | 1984-04-21 | 1985-11-08 | Shinryo Air Conditioning Co Ltd | Blow-off port structure for clean room |
| IT1236980B (en) * | 1989-12-22 | 1993-05-12 | Sgs Thomson Microelectronics | NON-VOLATILE EPROM MEMORY CELL WITH DIVIDED GATE AND SELF-ALIGNED FIELD INSULATION PROCESS FOR OBTAINING THE ABOVE CELL |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2129181A (en) * | 1934-04-11 | 1938-09-06 | Carrie E Morse | Liquid purification plant |
| JPS5827666B2 (en) * | 1975-03-12 | 1983-06-10 | 株式会社日立製作所 | hand warmer |
| IT1089299B (en) * | 1977-01-26 | 1985-06-18 | Mostek Corp | PROCEDURE FOR MANUFACTURING A SEMICONDUCTIVE DEVICE |
| JPS53124084A (en) * | 1977-04-06 | 1978-10-30 | Hitachi Ltd | Semiconductor memory device containing floating type poly silicon layer and its manufacture |
| JPS54137982A (en) * | 1978-04-19 | 1979-10-26 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPS5530846A (en) * | 1978-08-28 | 1980-03-04 | Hitachi Ltd | Method for manufacturing fixed memory |
| DE3015615A1 (en) * | 1979-04-27 | 1980-11-06 | Maruman Integrated Circuits In | Read only memory has two types of MOS elements - producing different information states with different threshold voltage values |
| JPS56108259A (en) * | 1980-02-01 | 1981-08-27 | Hitachi Ltd | Semiconductor memory device |
-
1980
- 1980-06-30 JP JP8786780A patent/JPS5713772A/en active Pending
-
1981
- 1981-06-19 DE DE19813124283 patent/DE3124283A1/en not_active Withdrawn
- 1981-06-25 GB GB8119691A patent/GB2080024A/en not_active Withdrawn
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4516313A (en) * | 1983-05-27 | 1985-05-14 | Ncr Corporation | Unified CMOS/SNOS semiconductor fabrication process |
| WO1984004852A1 (en) * | 1983-05-27 | 1984-12-06 | Ncr Co | Process for fabricating complementary and nonvolatile type devices on a common substrate |
| EP0160965A2 (en) * | 1984-05-07 | 1985-11-13 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device with a stacked-gate-electrode structure |
| EP0160965A3 (en) * | 1984-05-07 | 1987-09-09 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device with a stacked-gate-electrode structure |
| EP0193841A2 (en) * | 1985-02-25 | 1986-09-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| EP0193841A3 (en) * | 1985-02-25 | 1986-12-17 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US4754320A (en) * | 1985-02-25 | 1988-06-28 | Kabushiki Kaisha Toshiba | EEPROM with sidewall control gate |
| FR2583920A1 (en) * | 1985-06-21 | 1986-12-26 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT AND IN PARTICULAR AN EPROM MEMORY COMPRISING TWO SEPARATE ELECTRICALLY ISOLATED COMPONENTS |
| EP0206929A1 (en) * | 1985-06-21 | 1986-12-30 | Commissariat A L'energie Atomique | Method of producing an integrated circuit and in particular an EPROM memory with two distinct electrically isolated components |
| EP0244367A2 (en) * | 1986-04-21 | 1987-11-04 | SGS MICROELETTRONICA S.p.A. | Mos type integrated semiconductor device with nonuniform thickness of gate oxide and process for fabricating it |
| EP0244367A3 (en) * | 1986-04-21 | 1989-06-14 | SGS MICROELETTRONICA S.p.A. | Mos type integrated semiconductor device with nonuniform thickness of gate oxide and process for fabricating it |
| US5061654A (en) * | 1987-07-01 | 1991-10-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit having oxide regions with different thickness |
| US4780424A (en) * | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
| EP0390219A2 (en) * | 1989-03-31 | 1990-10-03 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| EP0390219A3 (en) * | 1989-03-31 | 1992-02-05 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5169792A (en) * | 1989-03-31 | 1992-12-08 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US5158902A (en) * | 1989-04-28 | 1992-10-27 | Kabushiki Kaisha Toshiba | Method of manufacturing logic semiconductor device having non-volatile memory |
| EP0499985A2 (en) * | 1991-02-18 | 1992-08-26 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor memory device |
| EP0499985A3 (en) * | 1991-02-18 | 1992-09-16 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor memory device |
| US5219775A (en) * | 1991-02-18 | 1993-06-15 | Kabushiki Kaisha Toshiba | Manufacturing method for a floating gate semiconductor memory device by forming cell slits |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5713772A (en) | 1982-01-23 |
| DE3124283A1 (en) | 1982-06-16 |
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Legal Events
| Date | Code | Title | Description |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |