GB2077974A

GB2077974A - A matrix type liquid crystal display device

Info

Publication number: GB2077974A
Application number: GB8124241A
Authority: GB
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 1978-10-25
Filing date: 1979-10-24
Publication date: 1981-12-23
Also published as: GB2077974B; GB2034953B; DE2943206C2; DE2943206A1; GB2034953A

Abstract

A matrix type liquid crystal display includes an array of MOS-FET's on one substrate for controlling individual picture elements, a plurality of source lines crossing a plurality of gate lines for controlling the MOS-FET's, and a plurality of common electrodes on the opposite substrate, each under the elements along one gate line. The gate lines are scanned sequentially (c), the elements for display in each being selected by synchronised signals (a), (b) on the source lines. In use, the MOS-FET drains apply voltages (d), (e) to the selected picture elements in alternate frames, and in the intermediate frames voltages (f) of the same polarity are applied to the common electrodes to cause reversal of the effective voltage (g) across the selected picture elements and zero across unselected elements. Halftones are possibly by control amplitude of drain (i) and common voltage, giving element voltages (j). <IMAGE>

Description

1 GB 2 077 974 A 1

SPECIFICATION

A matrix type liquid crystal display device The present invention relates to a liquid crystal display, and more particularly to a matrix type display device 5 comprising a liquid crystal display panel.

Hughes Aircraft Company has introduced a new concept of a matrix type liquid crystal display panel wherein a MOS-FET and a parasitic capacitpr were implemented on a SOS (Silicon on Sapphire) or a conventional silicon substrate for each of the picture elements.

Although the details of such a panel are fully apparent from "A Liquid Crystal TV Display using a Silicon--- On-Sapphire Switching Array" by L.T. Lipton, M.A. Meyer and D. O. Massetti, paper presented at the 1975 Society for Information Display Symposium, New York and "A fully integrated MOS Liquid Crystal Video-Rate Matrix Display." presented at International SID Symposium, Boston, Mass., April 1977, its structure and operating principle will be briefly discussed here to give a better understanding of the present invention.

Figure 1 shows a circuit including a MOS-FET3and a parasitic capacitor (Cs) 5foreach ofthepicture elements of the panel and Figure 2 shows the enabling voltage waveforms associated with the circuit of Figure 1. In the given example there are only four picture elements and these are aligned in an X-Y matrix to provide a visual matrix display.

If a source voltage of V, and a gate voltage of V, are applied to the source electrode 1 and the gate 20 electrode 2 of Figure 1, then the MOS-FET 3 is placed into the conductive (ON) state so that the parasitic capacitor (Cs) 5 in parallel with the capacitance (CLC) 4 of the liquid crystal material is charged via the ON resistance RON of the MOS-FET from the source electrode 1. Therefore, the potential (V drain 1) at the drain electrode 6 varies pursuant to the following formula (l):

V drain 1 = V, (1 - e t)...... (1) wherein -cl = RON (CLC + CS) 30 Then, if the gate voltage at the gate electrode 2 charges to a zero potential, the MOS-FET 3 is turned to the cut-bff (OFF) state. This results in the capacitors CLc and Cs starting to discharge the cumulative charge thereon through the OFF resistance FOFF of the MOS-FET 3 and the resistance RLc of the liquid crystal 35 material. Since the resistances ROFF, RLc and RON are correlated as follows, ROFF >> RON, RLC > ROFF the process of discharging goes on quite slowly such that the potential (V drain 2) at the drain electrodeis held considerably high for a relatively long period of time as defined by the following formula:

V drain 2 = Vie _t _2 wherein'U2 = (ROFF/RLC) (CLC + CS) ..... (2) The result of these processes is apparent from the voltage waveform chart of Figure 2. The effective voltage at the drain electrode, namely, the effective voltage developing across the liquid crystal picture element is remarkably high and assures a high contrast display even when the voltage applied to the source electrode 1 has a small duty factor and a low effective value.

A cell structure for operation pursuant to the above described principle is illustrated in Figure 3.

Nevertheless, two basic problems have been experienced in enabling the above described display panel with enabling voltages such as indicated in Figure 2.

(D As long as the voltage-current characteristics % - ID) of the MOS-FET are asymmetrical with respect to - polarity, as shown in Figure 4, it is difficult to enable the liquid crystal panel with an alternating current voltage including no dc component. This substantially shortens the operating life of the liquid crystal panel. 60 0 When using waveforms of enabling voltages as indicated in Figure 5 to enable all the picture elements - other than one selected by a specific source electrode Si and a specific gate electrode Gi, the MOS-FETfor the selected or disabled one remains in the cut-off (OFF) state but the capacitors CLC + Cs are progressively charged via the OFF resistance ROFF. It is therefore possible that a voltage more than a given threshold voltage level Vth of the liquid crystal material may be applied thereto. The resulting voltage is in the form VLci65 2 GB 2 077 974 A 2 as indicated in Figure 5 and on-off switching is effected between the source voltage Vsj and the gate voltage VGi so that, while the MOS-FET is in the OFF state, the drain voltage VDy bears an increased effective value equal to or higher than that in the ON state. This causes an objectionable visual display and a variation in contrast depending on the number of liquid crystal elements enabled at any given moment.

Accordingly, Hughes Aircraft Company devoted research activities to developing liquid crystal materials capable of being enabled with a de voltage without shortening the operating life thereof in order to overcome the problem (D. However, the materials were not comparable to those driven by an alternating current voltage. The problem @still remained unsolved and an attempt to ease the problem @wasmade by increasing the ratio ROFF/RON of the MOS-FET.

According to the present invention, there is provided a matrix type display device comprising:

a matrix LCID display panel having a plurality of picture elements each of which is controlled bythe difference between the voltage at a common electrode on a first substrate of the panel and the voltage provided by a respective one of a plurality of MOS-FET's forming an array of lines and columns disposed on a second substrate of the panel, the panel having a plurality of source lines each connected to the source electrodes of a column of MOS-FET's and a plurality of gate lines each connected to the gate electrodes of a 15 line of MOS-FET's for controlling the MOS-FET's; and drive means including means for sequentially scanning the gate lines and means arranged to cause the MOS-FET's of selected picture elements associated with a gate line to provide a signal of predetermined polarity when that gate line is scanned, and, when the gate line is next scanned, to apply a reverse voltage across those selected picture elements by applying a signal of the same polarity to the common electrode of 20 those picture elements.

Using such a device, it is possible to apply symmetrical voltages, having no d.c. component, to the panel and thus avoid the above-mentioned problem (1).

Co-pending patent application No. 7936867 proposes a solution forthe above-mentioned problem and as will be made clear later the principles involved in that solution can also be incorporated in a device of 25 the present invention. Arrangements embodying the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a prior art matrix type liquid crystal display using MOS-FET's; 30 Figures 2(a) to (c) are timing diagrams for illustration of the operation of the circuit of Figure 1, Figures 2(a) 30 and 2(b) showing the waveforms of source and gate voltages applied to a MOS-FET, and Figure 2(c) illustrating the resulting waveform of the voltage across a selected picture element; Figure 3 is a cross-sectional view of a matrix type liquid crystal display panel incorporating MOS-FET's; Figure 4 is a voltage-current graph of a conventional n-channel MOS-FET; 35 Figure 5 is a timing diagram of a specific operating state of the circuit of Figure 1; Figure 6 is a timing diagram illustrating how a display device according to the invention of patent application No. 7936867 is driven; Figure 7 is a timing diagram illustrating how a display device according to the present invention is driven; Figure 8 is a cross-sectional view of a liquid crystal display panel which can be used in a device according to the present invention; Figure 9 is an equivalent circuit diagram of the liquid crystal display panel of Figure 8; Figure 10 is a timing diagram illustrating how another display device according to the present invention is driven; Figure 11 shows an arrangement used in driving the panel of Figures 8 and 9; and Figure 12 shows a circuit diagram and a timing diagram of an exemplary circuit for producing the source 45 voltage used to drive the panel.

Figure 6 illustrates the driving method used for a display device according to the invention of patent application No. 7936867, which is intended to solve the problem Q mentioned above. The method is being described here because the principles involved can be used, as will be clear later, in a device of the present invention.

Figure 6(a) shows the waveform of the source voltage Vsiwhich is applied to the (i)th source electrode and which has positive and negative polarity components. The arrangement is such that the positive and negative components of the source voltage Vsj are applied when it is desired to write-into a selected picture element, and the source voltage is held at zero potential when it is not desired to write-into the element.

Figure 6(a) illustrates the waveform of the voltage at the source electrode when alternate picture elements 55 on the Mth source electrode are written-into, the intermediate elements being disabled. It will be noted that the positive and negative components of the source voltage are reversed in phase between the odd and even frames to enable the panel in an alternating current fashion.

Figures 6(b) - 6(d) illustrate the waveforms of the gate voltages VGi, VGi+l and VGi+2 at the (j)th gate electrode through the (j + 2)th gate electrode which are to be scanned in sequence. For picture elements 60 which are written-in, a pulse of the gate voltage is applied at the same time as the positive component of the source voltage during odd frames and at the same time as the negative component during even frames. The, pulse width of the gate pulse is the same as that of the component of the source voltage with which it is concurrently applied, i.e. the same as the positive component during odd frames and the negative component during even frames.

3 GB 2 077 974 A 3 The result is that during successive frames each written-in picture element has a successively alternating voltage applied thereacross.

In the example as shown in Figure 6, the Q, j)th and Q, j+2)th picture elements are written-in whereas the Q, j+l)th picture element is not written-in.

Because the source voltage is bipolar, i.e. it includes both positive and negative components, the voltage 5 across picture elements which are not written-in does not progressively increase during the scanning frame.

In fact the pulse width ratio of the positive and negative polarity components of the source voltage is selected so that, when a MOS-FET associated with the electrode is OFF, charging and discharging currents flowing through the transistor in the positive and negative directions bring the effective voltage across the associated display element to zero, thus compensating for variations in the characteristics of the MOS-FET with the polarity of the applied voltage. Thus even if only one picture element is not written-into as indicated in Figure 5, this picture element would never be supplied with a voltage due to cross-talk. The display panel thus has a higher contrast which does not vary with the number of picture elements which are written- in.

The findings of the inventors' experiments demonstrated that the following pulse width ratios were suitable:

pulse width of positive pulse pulse width of negative pulse 0.2 to 0.05 One effective way to avoid the above-mentioned problem G) using a device according to the present invention will now be described with reference to the timing diagram of Figure 7. As will be clear later, both problems CD and @ can be solved by using the principles involved here in conjunction with those forming the basis of the method of Figure 6.

Referring to Figure 7, when it is desired to write-into a selected one of the picture elements, a unidirectional source voltage pulse Vs as shown in Figure 7(a) is supplied to the source electrode of its associated MOS-FET. The source voltage pulse is negative in the case where the MOS-FET's are of p-channel type and positive in the case where they are of n-channel type. The gate voltage pulse VG shown in Figure 7(c) is applied to turn on the MOS-FET in each odd and even frame, the source voltage pulses Vs only being applied during the odd frames. Thus, the drain voltage VD (ON) of the MOS- FET's will have the waveform of 30 Figure 7(d). The waveform of Figure 7(d) illustrates only the negative voltage side and, of course, includes a d.c. component. A common voltage Vc shown in Figure 7(f) is applied to the common electrode at the other side of the selected display element during the even frames. As a result, a differential voltage between the voltages of Figures 7(d) and 7(f), namely, the voltage waveform of Figure 7(g) is applied across the liquid crystal material to perform the write operation. It can be seen from Figure 7(g) that the voltage value and 35 waveform of the common voltage Vc may be properly selected in line with the drain voltage VD for supply of an alternating voltage including no d.c. component to the liquid crystal panel.

When a selected picture element of the liquid crystal material is not desired to be written-in, the source electrode of its associated MOS-FET is supplied with the source voltage Vs (OFF) as shown in Figure 7(b) together with the gate voltage pulse VG of Figure 7(c) in such away that the MOS-FET selecting that picture 40 element applies a voltage thereto only during the even frames. Therefore, the drain voltage VD (OFF) of the FET has the waveform shown in Figure 7(e), this voltage being applied to one electrode of the picture element of the liquid crystal material. The common voltage Vc shown in Figure 7(f) is applied to the common electrode during the even frames with the resulting similarity in voltage polarity and waveform. Therefore, there is no potential difference between the two opposing electrodes of the panel, and the voltage across non-selected picture elements is thus as indicated in Figure 7(h).

In order to be able to apply the common voltage Vc to the various picture elements of the liquid crystal panel in conformity with the scanning of the respective gate electrodes, the preferably transparent common electrode is made in a stripe-like form with the discrete stripes extending in parallel with the gate electrodes.

Across-sectional view of the resulting liquid crystal display panel is illustrated in Figure 8 and an equivalent 50 circuit diagram thereof is illustrated in Figure 9.

If it is desired to provide a half-tone display, the amplitude of the source voltage Vs and the common voltage should be varied in accordance with the desired intensity. Suitable examples of the drain voltage and the applied voltage across the liquid crystal material are illustrated in Figures 7(i) and 7(j).

Using the technique illustrated in Figure 7, the voltage on the common electrode in even frames differs 55 from that during odd frames and the voltage applied by the MOS-FET's to the picture elements matches that applied to the common electrode when the picture element is not writtenin and is 180'out of phase when the picture element is written-in. Thus symmetrical voltages having no d. c. component are applied to the panel, which thus enjoys a relatively long life. Furthermore, the MOS- FET's only have to pass current in a single, preferred direction and this provides highly efficient driving of the panel.

- As can be seen from Figure 6(e), the voltage waveform applied across the liquid crystal material in the - arrangement solving the problem @ is asymmetric with respect to the positive and negative polarities and contains a substantial d.c. component. Furthermore, the driving of a display device using the method described in connection with Figure 7, although overcoming the problem (J), would not overcome the problem (2).

4 GB 2 077 974 A 4 Another embodiment of the present invention is an effective measure to overcome both problems 0 and 0, and will be described with reference to the timing diagram of Figure 10. The construction of the liquid crystal display panel is the same as in Figure 8 and its equivalent circuit is as shown in Figure 9.

Figure 1 0(a) shows the waveform of the source voltage on the (i)th column when the successive picture elements associated with that column are enabled such that each written- in element is followed by two 5 non-written elements.

During odd frames, negative and positive components of the source voltage are applied during the period from tj up to t2 and zero voltage during the periods from t2 to t3 and from t3 to t4. During even frames, the source voltage is at zero from t'l to t'2 and negative and positive pulses are applied from t'2 to t3 and from t'3 to t'4 The pulse width ratio of the negative and positive pulses is established as described in connection with Figure 6.

Figure 1 0(b) depicts the waveform of the gate voltage on the (j)th line, Figure 10(c) on the (j + 1)th line and Figure 1 0(d) on the Y+2) line. As is indicated in Figures 10(b) to 10(d), gate voltage pulses are sequentially applied to the gate electrodes for sequentially scanning the gate electrodes.

Figures 10(e) through 1 0(g) depict the waveforms of the voltages applied to the common electrodes corresponding to the (j)th through (i + 2)th lines.

From the foregoing, it is clear that during the odd frames the source voltage on the U)th column and the gate voltage on the (j)th line are supplied to turn on the MOS-FET at the intersection (i, j) while the negative component of the source voltage is present so that the liquid crystal material at the specific picture element 20 Q, j) is supplied with this negative component and hence the voltage VLcjj. This results in writing-in the specific picture element (i, j).

Since during the next succeeding line scan the source voltage on the (i)th column is zero, the MOS-FET at the intersection Vj+1) causes the voltage VLcjj+j across the (i, j+ 1) picture element also to be zero.

The same procedure will be repeated for the second succeeding Y+2) line without performing the write operation. The above procedures continue up to the last line, with those elements which have been selected having a voltage applied thereacross, to complete one scanning frame.

During the next succeeding frame, that is, the even frame, the operations of the respective MOS-FET's are reversed. Thus, the source voltage is zero when the MOS-FET Q, j) is scanned, and the negative component of the source voltage is present when the MOS-FETs U, j+1) and (i, j+2) are scanned.

For those picture elements which have been selected for display, the voltage applied thereto by means of the associated common electrode during even frames is opposite to that applied by the MOS-FET during odd frames (see Figure 1 0(h)). The non-selected picture elements are supplied with the negative component of the source voltage Vsj and the common voltages Vcj+j and Vcj+2 at the same time. Since these voltages are identical in polarity, waveform and magnitude, no resultant voltage is therefore applied as best seen from 35 Figures 10(1) and 1 0(j).

In Figure 11, there is illustrated an example of a circuit adapted to apply the common voltages of Figures 10(e) through 1 0(g) to the stripe-shaped common electrodes 31. Figure 12 shows a practical circuit and associated timing diagram for producing the source voltage Vsf of Figure 1 0(a) which is to be supplied to the source electrode of the MOS-FET.

Although the use of a common electrode in stripe-like form renders the manufacture of the liquid crystal panel and the enabling circuit somewhat complicated, it is possible to use MOS-FET's even with a poor ROFF/RON ratio and nevertheless obtain an ideal enabling operation as long as there is no difference in operating performance from one MOS-FET to another. The findings of the inventor's experiments indicated that a 128 line matrix display provided as high a contrast as in a conventional static mode through the use of 45 elements with ROFF/RON 300.

As is obvious to those skilled in the art, the present invention is equally applicable to n-channel MOS-FET's by merely changing the polarity of the enabling voltages, as well as to MOS-FET's deposited on an SOS (Silicon On Sapphire) substrate.

i Z

Claims

1. A matrix type display device comprising:

a matrix LCD display panel having a plurality of picture elements each of which is controlled by the difference between the voltage at a common electrode on a first substrate of the panel and the voltage 55 provided by a respective one of a plurality of MOS-FET's forming an array of lines and columns disposed on a second substrate of the panel, the panel having a plurality of source lines each connected to the source electrodes of a column of MOS-FET's and a plurality of gate lines each connected to the gate electrodes of a line of MOS-FET's for controlling the MOS-FET's; and drive means including means for sequentially scanning the gate lines and means arranged to cause the 60 MOS-FET's of selected picture elements associated with a gate line to provide a signal of predetermined polarity when that gate line is scanned, and, when the gate line is next scanned, to apply a reverse voltage across those selected picture elements by applying a signal of the same polarity to the common electrode of those picture elements.

2. A device as claimed in claim 1r including a plurality of common electrodes each associated with the 65 GB 2 077 974 A picture elements controlled by a respective line of MOS-FET's.

3. A device as claimed in claim 2, wherein the drive means is arranged such that, for alternate scans of a gate line, the source line associated with each selected picture elements of that gate line is supplied with a positive and a negative pulse and the source line associated with each non-selected picture element of that gate line is supplied with zero voltage, and for the intervening scans of the gate line the source line associated with each selected picture element is supplied with zero voltage and the source line associated with each non-selected picture element is supplied with a positive and a negative pulse.

4. A matrix type display device substantially as herein described with reference to Figures 7 to 9 of the accompanying drawings.

Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited, Croydon, Surrey, 1981. Published by The Patent Office, 25 Southampton Buildings, London, WC2A l AY, from which copies may be obtained.