GB2073969A - Circuit interrupter apparatus - Google Patents
Circuit interrupter apparatus Download PDFInfo
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- GB2073969A GB2073969A GB8111092A GB8111092A GB2073969A GB 2073969 A GB2073969 A GB 2073969A GB 8111092 A GB8111092 A GB 8111092A GB 8111092 A GB8111092 A GB 8111092A GB 2073969 A GB2073969 A GB 2073969A
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- 230000006870 function Effects 0.000 claims description 44
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000000737 periodic effect Effects 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 230000007246 mechanism Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000000717 retained effect Effects 0.000 description 7
- 101100534682 Arabidopsis thaliana SUMO4 gene Proteins 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- QBSJMKIUCUGGNG-UHFFFAOYSA-N isoprocarb Chemical compound CNC(=O)OC1=CC=CC=C1C(C)C QBSJMKIUCUGGNG-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 101100365194 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SEC7 gene Proteins 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/10—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current additionally responsive to some other abnormal electrical conditions
- H02H3/105—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current additionally responsive to some other abnormal electrical conditions responsive to excess current and fault current to earth
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
- H02H3/0935—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means the timing being determined by numerical means
Abstract
In an overcurrent or earth-leakage protective system, the current sensor output is digitised and then analysed in a digital processor 154. <IMAGE>
Description
SPECIFICATION
Circuit interrupter apparatus
The invention relates to circuit interrupter apparatus having means for electronically analyzing the electrical conditions on a circuit being protected, and means for automatically interrupting the current flow whenever electrical conditions exceed predetermined limits.
Circuit breakers are widely used in industrial and commercial applications for protecting electrical conductors and apparatus connected thereto from damage due to excessive current flow. Circuit breakers were initially designed to interrupt when the current flowing through them exceeded a certain level.
Gradually, however, more elaborate time-current interrupting characteristics were required such that a circuit breaker would rapidly open upon very high overload conditions but would delay interruption upon detection of lower overload currents, the delay time being roughly inversely proportional to the degree of overload. Additionally, circuit breakers were called upon to interrupt upon the detection of ground fault currents. As the complexity of electrical distribution systems increased, the control portions of circuit breakers on a system were interconnected to provide selectivity and coordination of interruption sequences.
This allowed the system designer to specify the order in which the various circuit breakers would interrupt under specified fault conditions.
During the late 1960's, solid-state electronic control circuits were developed for use in high power, low voltage circuit breakers. These control circuits performed functions such as instantaneous and delayed tripping which were traditionally achieved by magnetic and thermal means. The improved accuracy and flexibility of the solid state electronic controis resulted in their wide-spread acceptance, even though the electronic control circuits were often more expensive than their mechanical counter-parts.
The earliest electronic control circuit designs utilized discrete components such as transistors, resistors, and capacitors. More recent designs have included integrated circuits which have provided improved product performance at reduced cost.
As the cost of energy continues its rapid rise, there is increasing interest in more effectively controlling the usage of electrical energy through the design of more sophisticated electrical distribution systems.
Therefore, there is required a circuit breaker providing a more complex analysis of electrical conditions on the circuit being protected and even greater capability for coordination with other breakers. As always, it is extremely desirable to provide this capability at the same or lower cost.
Accordingly, the present invention provides circuit interrupter apparatus, comprising contacts for connection to an associated circuit to be protected; interrupter means operable to open said contacts; sensing and powering means for sensing current flow through the contacts and providing a digital signal related to the current sensed, and for providing operating power for said apparatus; and digital processor means connected to and empowered by said sensing and powering means for receiving said digital signal, and connected to said interrupter means for effecting contact opening operation thereof when said digital signal attains a predetermined value.
More specifically, the circuit interrupter apparatus includes means for converting analog signals to digital values, a digital arithmetic and logic processor, and memory array means for storing a plurality of values corresponding to the desired time current tripping characteristics of the apparatus. The processor periodically generates signals to cause the analog-to-digital conversion means to supply a digital representation of the value of current flow through the contacts. The processor then compares the current flow value representation to the digital representations of the time-current tripping characteristic stored in the memory, and generates a signal to energize the interrupter means and effect contact opening operation thereof when the sensed current flow exceeds the time-current tripping characteristic of the apparatus.
The electronic means also analyzes electrical parameters on the associated circuit. Numeric display mewans visible from the exterior of the apparatus are provided for displaying a numerical representation of the electrical parameters. The numeric display means is part of a front panel display system including also a plurality of electrically powered visual display indicators. Means are provided to prevent nuisance tripping upon system power-up, to determine peak current values for each cycle of AC current, and to ensure the most conservative settings if unreliable values of time-current tripping characteristic parameters are entered. Cause of trip and display of trip current is also provided, as is an accurate determination of long delay and ground fault trip operation.
A preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 is a perspective view of a circuit breaker embodying the invention;
Figure 2 is a functional block diagram of the circuit breaker shown in Figure 1;
Figure 3 is an electrical schematic diagram of a distribution system employing the circuit breaker of
Figures 1 and 2;
Figure 4 is a graph of a typical time-current tripping characteristic, plotted on a log-log scale;
Figure 5 is a block diagram of the trip unit of the circuit breaker shown in Figures 1 and 2;
Figures 6A and 6B are partial schematic circuit diagrams of the trip unit of Figure 5;
Figure 7 is a general flow chart of the program stored in the memory of the microcomputer;;
Figure 8 is a flow chart of the analog-to-digital routine stored in the memory of the microcomputer which is a component of the trip unit;
Figure 9 is a flow chart of the short delay trip and instantaneous trip functions of the program of Figure 7;
Figure 10 is a flow chart of the long delay trip function of the program of Figure 7;
Figure ills a flow chart of the ground trip function of the program of Figure 7, Figure 12 is a flow chart of the self-checking routine of the program of Figure 7; and
Figure i3is a flow chart of the rOutine to read external programmable read-only-memory of the program of Figure 8.
General Physical and Electrical Description: reference may now be had to the drawings, in which like reference characters refer to corresponding components. A perspective view and a functional block diagram of a molded case circuit breaker 10 embodying the inv-e-ntion are provided in Figures 1 and 2, respectively. Although the circuit interrupter 10 is a three-pole circuit breaker for use On a three-phase electrical circuit, the invention is, of course, not so limited and could be used On a single-phase circuit or another type of multiphase circuit.
A powersource, such as a transformer or switchboard bus, is connected to input terminals 12, and an electrical load is connected to output terminals 14. Internal conductors 1.6 connected to the terminals 12 and 14 are also connected to interrupting contacts IS which serve to selectively open and close an electrical circuit through the circuit breaker. Thecontàcts 18 are operated by mechanism 20 which responds to manually or automatically initiated commands to open or close the contacts 18.
Current transformers 24 surround each of the internal phase conductors 16 to sense the level of current flow through the conductors 16. The output from the current transformers 24 is supplied to a trip unit 26, along with the output from a current transformer 28 which senses the level of ground fault current flowing in the circuit.The trip unit 26 constantly monitors the level of phase and ground fault currents flowing in the circuit to which the breaker loins connected, and initiates a command signal to a trip coil 22 which actuates the mechanism 20 to open the contacts 18 whenever electrical conditions On the Circuit being protected exceed predetermined limits stored in the trip unit 26. During normal conditiOns, the mechanism 20 can be commanded to open and close the contacts 18 through manually-initiated commands applied through the manual controls 312.
Referring to Figure 1, it can be seen that the circuit breaker 10 includes a molded insulating housing 34.
The terminal 12 and 14 (Figure 2) are on the rear of the housing 34 and are thus not shown in Figure 1.
handle 316is mounted on the the nglht-hand side of the housing 34 to allow an operator to manually charge a spring (not shown} in the Mechanism 20. The manual controls 32 are positioned in the center of the housing 34. Windows 38 and 40 indicate the state of charge of the spring, and the position of the contacts 18, respectively, A push-button 42 allows an operator to cause an internal electric motor to mechanically charge the spring inthesame manner as the manual charging operation which can be perform ed by the handle 36.
A pushbutton 44 allows an Operator to cause the spring to operate the mechanism 20 to close the contacts Ia Similarly, a pushbutton 46 allows an operator to cause the spring and mechanism 20 to open the contacts Ia.
The panel ofthe trip unit 26 is positioned on the left side of the housing 34, as indicated in Figure 1. This panel includes a numeric display device 80 to permit an operator to observe the electrical parameters on the circuit being protected, a plurality of light-emitting diotie (LlED} indicators 84, 85, and 88, a rating plug 78 to determin the maximum continuous current of the breaker, and plug-in programmable read-only memory (PROM) chip chip 52 to 82 to define the time-current trip characteristic of the breaker.
Use of a Circuit Breaker in an Eiectrical sewer Distribution System before explain the operation of the trip unit, it will be helpful to describe in greater detail the function of a Circuit breaker in an electrical power distribution circuit. Figure 3 shows a typical electrical distribution system. A plurality' Of electrical loads 48 are supplied through circuit breakers 50, 52 and 54 from either of two sources of electrical energy 56 and 58.The sources 56 and 58 could be transformers connected to separate high voltage electrical feeder lines, diesel-powered generatots, or à combination of the two. Power from the first source 55 is supplied through the first main circuit breaker 50 to a plurality of branch circuit breakers 6-0,52,64, and 65 Similarly', power from the second source 58 may be supplied through the second main circuit breaker 52 to a second plurality of branch circuit breakers 68,70,72, and 74.Alternatively, power from either source 56 or 5S V be supplied through the tie circuit breaker 54 to the branch circuit breakers on the opposite side. Generally, the main and tie circuit breakers 50,52 and 54 are coordinated so that no branch circuit is- simultaneously supplied by both Sources. The capacity of the main and tie circuit breakers 50, 52 and 54 is usually' greater than that of any branch circuit breaker.
If a fault (abnormally large current flow) should occur at, for example, the point 76, it is desirable that this condition be detected by the branch circuit breaker 52 and that this breaker rapidly trip, or open, to isolate the fault from any source of electrical power. The fault at the point 76 may be a large over-current condition caused, for example, by a short circuit between two of the phase conductors of the circuit, or an overload only slightly above the rating of the breaker such as might be caused by an overload motor. Alternatively, it may be å ground fault caused by a breakdown of insulation on one of the conductors, allowing a relatively small amount of current flow to an object at ground potential. In any case, the fault would also be detected by the main or tie breakers 50, 52 or 54 through which the load fed by branch breaker 62 is supplied at the time of the fault.However, it is desirable that only the branch circuit breaker 62 operate to isolate the fault from the source of electrical power. The reason for this is that if the main or tie circuit breaker should trip, electrical power would be lost to a greater portion of the entire system than merely the load attached to the branch circuit on which the fault occurred. It is therefore desirable that the main and tie circuit breakers 50, 52 and 54 should have a longer delay period following detection of a fault before they initiate a tripping operation. The coordination of delay times among the main, tie, and branch circuit breakers for various types of faults and the need for inter-locking between breakers are major reasons for the need to provide sophisticated control in a trip unit.
Time-Current Tripping Characteristics:
In order to achieve the coordination between circuit breakers as described above, the time vs. current tripping characteristics of each circuit breaker must be specified. Circuit breakers have traditionally exhibited characteristics similar to that shown in Figure 4, where both axes are plotted on a logarithmic scale. When current below the maximum continuous current rating of the breaker is flowing, the breaker will, of course, remain closed. As current increases, however, it is desirable that at some point, for example the point 300 of
Figure 4, the breaker should trip if this overload current persists for an extended period of time. Should a current flow equal to the maximum continuous current rating as specified by point 300 persist, it can be seen from Figure 4 that the breaker will trip in approximately 60 seconds.
At slightly higher values of current, the time required for the breaker to trip will be shorter. For example, at 1.6 times maximum continuous current, as specified by point 302, the breaker will trip in about 20 seconds.
The portion of the curve between the points 300 and 304 is known as the long delay, or thermal, characteristic of the breaker, since this characteristic was provided by a bimetal element in traditional breakers. It is desirable that both the current level at which the long delay portion begins and the trip time required for any point on that portion be adjustable. These parameters are known as long delay pickup p and long delay time, respectively, the variation of which is indicated by the arrows 306 and 308.
At very high overcurrent levels, for example 12 times the maximum continuous current and above, it is desirable that the circuit breaker trip as rapidly as possible. This point 312 on the curve is known as the "instantaneous", or magnetic, trip level, since traditional breakers employed an electromagnet in series with the contacts to provide the most rapid response. The instantaneous pick-up level is usually adjustable, as indicated by the arrow 314.
To aid in coordinating breakers within a distribution system, modern circuit breakers have added a short delay trip characteristic 316 between the long delay and instantaneous portions. The present invention allows adjustment of both the short delay pick-up level and the short delay trip time, as indicated by the arrows 318 and 320.
Under certain conditions it is desirable that the trip time over the short delay portion vary inversely with the square of the current. This is known as an 12t characteristic and is indicated in Figure 4 by the broken line 310.
Trip Unit Functions and Modes:
The functions and modes of the trip unit 26 employing the invention will now be described. A rating plug 78 is inserted into the front panel of the trip unit 26 to specify the maximum continuous current to be allowed in the circuit being protected by the circuit breaker. This may be less than the actual capacity of the circuit breaker, which is known as the frame size. For example, the frame size for the circuit breaker may be 1,600 amperes; however, when the breaker is initially installed the conductors of the circuit being protected may be sized so as to continuously supply only 1,200 amperes of electrical current.Therefore, a rating plug can be inserted in the trip unit to ensure that the maximum continuous current allowed by the circuit breaker will be only 1,200 amperes even though the circuit breaker itself is capable of safely carrying 1,600 amperes continuously.
Throughout the remainder of the description of the invention, current levels may be described as multiples of the maximum continuous current specified by the rating plug. This convention will be expressed as, for example, 3 per unit, or 3 p.u., to indicate a current level of three times the maximum continuous current.
The electronic circuitry internal to the trip unit causes the numeric display indicator 80 (Figure 1) to sequentially display the present value of electrical conditions on the circuit being protected, and the various limit settings defining the time-current trip curve of the breaker as currently set. The LED's 84,86 and 88 indicate whether a ground fault, long delay overcurrent, or "instantaneous" overcurrent was the cause of a trip operation.
To the right and below the numeric display indicator 80 and rating plug 78 is the plug-in programmable read-only memory (PROM) module 82, such as a type 3601 manufactured by the Intel Corporation, in which are stored the various limit values and settings which specify the time-current tripping characteristic of this particular circuit breaker. The method of loading the settings into this module, and the manner in which the module is used by the trip unit circuitry will be described in a later section herein.
System Description
The trip unit circuitry includes a digital arithmetic, logic, card control processor 154, such as the type 8048 microcomputer maufactured by the Intel Corporation, and is presented by block diagram in Figure 5. This section will describe each block of Figure 5 and present a description of the operation of the trip unit.
The microcomputer 154 contains an arithmetic logic and control unit 153, 64 x 8-bit bytes of read-write random access memory (RAM) 155, 1K x 8-bit bytes of read-only memory (ROM) 157, an 8-line data bus 172, and two 8-line input-output ports Port 1 and Port 1. Other types of digital arithmetic, logic, and control processors could be used, such as those requiring outboard memory circuits rather than having the on-chip
RAM and ROM circuits of the 8048. However, for a detailed description of the micro-computer, reference should be made to the MCS-48 Micro-computer User's Manual published by the Intel Corporation.
Circuit Description:
Referring to the system block diagram of Figure 5 and the detailed schematic diagram of Figure 6, the display section 79 is first described. It consists of four data latches IC5,1C6, IC7 and IC8 and the four-digit liquid crystal numeric display 80. The data latches may be the type MC 14543. Display data is multiplexed on the data bus 172 of the microcomputer; the four least significant bits represent data and the four most significant bits its position on the display. The liquid crystal display 80 derives its back plane clock from the interval timer 92. This interval timer also fulfills the function of resetting the microcomputer if it does not receive its clock signals from the microcomputer 154. Under normal operation, the microprocessor outputs a pulse on every execution of the main program loop.
It can be seen on the diagram of Figure 5 that the PROM 82 receives its address from the data bus 172 and outputs its contents via Port 1. Since the display section 79 and the address lines of the PROM 82 are both connected to the data bus 172, the address information for the PROM would tend to cause a garbled display.
However, the address information appears on the bus for only a small fraction of a second, to be immediately followed by valid display information. The LCD display therefore does not have time to respond to the PROM address information and the operator observes only the valid display information.
The output subsystem 94 consists of 1/2 of a type A775 comparator IC2, and of quad NOR gate IC10 and quad NAND gate IC11. Through comparator IC2, the microcomputer 154 via Port 2 sets an interlock output signal after a ground fault pickup. Through the NAND gate of lC1 1, the microcomputer sets the corresponding LED indicator 84,86 or 88 after a trip.
The NOR gates IC10 provide the high-level output signal to trip a signal SCR 98 under ground, short delay, long delay, or instantaneous trip. It also forces this trip signal to follow the RESET signal during power-up, thus eliminating false tripping during the 10 ms period of microcomputer instability after power is first applied.
The input subsystem 100 consists of two peak detecting circuits including capacitors 90 and 91, a type
ZN425J D/A converter IC4, the other half of comparator IC2, and the analog switches of IC3. The capacitors 90 and 91 store the peak value of phase and ground current, respectively, for each cycle of the AC line. The peak values are then read every cycle by the microcomputer. The capacitors 90 and 91 are reset (discharged) later in each cycle by the microcomputer through a transistor 96 and IC11 activated by Port 2.
The analog-to-digital conversion of the signal from the input subsystem 100 is accomplished by an iteration technique employing the D/A converter IC4 and comparator IC2. A digital value is supplied to the
D/A converter IC4 by the microcomputer 154. This value is converted to an analog value and supplied to IC2.
lC2 then compares this value to the value supplied from capacitor 90 or 91 through the analog switch IC3 and indicates whether or not the value supplied by IC4 is larger. The result of this comparison is supplied via the T1 test input to the microcomputer 154, which then generates a new value to IC4. This process continues
until the value generated by the microcomputer 154 is very close to that supplied by the analog switch IC3, and the result is retained in the accumulator of the microcomputer 154. The technique is shown in greater detail in the flow chart of Figure 8.
The function of transistors 102 and 104 and their associated components is to direct the phase (or ground) currents from the CT's 24 and 28 to the rating plug resistor 105 during non-tripping operation. However, when a trip condition is sensed and the trip SCR 98 is turned on, transistors 102 and 104 are turned off, thereby directing essentially all of the phase (or ground) current signal into the shunt trip coil for a positive tripping action.
Power for the trip unit circuitry is supplied by rechargeable battery with charging power produced by the current transformers 24. Alternatively, power could be derived directly from the current transformers 24 or independently via connections to the conductors 16.
Description of Operation
The operation of the invention is described in detail in this section. In the first part, a general flow chart of the program and the allocation of memory are presented. Major subroutines called from the main loop will then be detailed in the second part.
Data MemoryAllocation:
The allocation of the internal RAM 155 of the microcomputer 154 is shown in Table 1.
TABLE I
DATA MEMORY MAP (RAM)
63 Long Delay Pick-up (LDP)
62 Long Delay Time (LDT)
61 Short Delay Pick-up (SDP)
60 Short Delay Time (SDT)
59 Instantaneous Trip Setting (ITS)
58 Ground Fault Pick-up (GFP)
57 Ground Fault Time (GFT)
56
55
54 Sum 6 = Tally of GFT
53 Sum 4 = Tally of SDT
52 Sum 45 = Self-checking Sum 4
51 Sum 65 = Self-checking Sum 45
50
49
48
47
46 Sum 3= LowerTallyofLDT 45 Sum 2 = Middle Tally of LDT
44 Sum 1 =UpperTallyofLDT 43
42
41 Trip Flag
40 Cycle Counter
39 Present value of inst. current
38 Present value of GND current
37
36 Trip value
35
34 Display index
33 Low byte of addr. of next display
32 High byte of addr. of next display
As can be seen, the top eight locations are used to load the limit value settings, such as Long Delay Pick-up and Long Delay Time.The values in these locations are refreshed every 4 seconds, after a reading of the external PROM 82. The tallies for ground fault, short delay, and long delay timing functions are also kept in
RAM. The address of the next information to be displayed, the present value of ground and instantaneous current, and the trip value are stored in locations shown. The addressing of those values is done indirectly through Register m (R) or Register 1 (R1) which contains the particular address.
The lower 32 words of data memory are used for standard "housekeeping" functions of the microcomputer, as explained in the previously referenced Intel User's Manual.
Main Loop
Refer to the flow chart of the main loop shown in Figure 7. After the system is powered-up or the reset button on the front panel is pushed, the program counter of the microcomputer 154 is loaded automatically with Ibpl hex. An instrument at this location brings the microcomputer to three initialization routines: clear
RAM, load display with aa.a, and perform discriminatory trip function. In the latter function, the present value of the phase current is compared with 9.0 p.u., i.e. nine times rated current. Thus, if the breaker is experiencing a high overload when the trim unit is first powered-up, the program is able to trip the breaker within 0.5 ms. These initialization routines are executed only during power-up or reset.
At this point the program counter is decremented to FF hex or 255 decimal. This count signals the microcomputer 154 to read the external PROM 82. If the PROM 82 is unreadable (contents = H or FFH) or the checksum is invalid, minimum limit value settings (from ROM 157 internal to the microcomputer) are loaded in corresponding RAM locations. Otherwise, the last sixteen memory locations of the PROM 82 are read. The use of a 2K PROM will thus allow the user to reprogram a new set of limit values into the PROM 16 times, before a new PROM must be employed. (16 x 16 values x 8 bits per value = 2048). After reading values from PROM, the program jumps to entry location BEGIN. From then on, this will be the starting point of the main loop.
The internal ROM 157 of the microcomputer 154 includes a look-up table containing the addresses of the subroutines which prepare the formats to enable the various parameter values to be displayed. Through an index R34 (initialized at Ib and updated by each dispaly routine) the address of the next display routine is read and stored in R33 and R32 of RAM 155.
Next, the four main functions of the program are entered: the instantaneous trip function, the short delay trip function, the long delay trip function and the ground trip function. Those functions will be presented in detail in the next section.
A self-checking subroutine is next executed. In this subroutine, the analog-to-digital converter, short delay pick-up, and ground test functions are checked. If a failure is detected, a failure flag is set and an error code stored in RAM 155.
The capacitors 90 and 91 for storing peak phase and ground current are then discharged and a time delay executed equal to 16.667 ms less the time expended in executing the main loop instructions.
Aflap is next checked to determine if a tripping operation has occurred. If so, the value of phase or ground current which caused the trip is now displayed. Since the trip unit is powered externally, a tripping operation will not inhibit execution of the microcomputer software.
After the first cycle, the main counter is at 254D. This number signals the microcomputer 154 to select another parameter to be displayed by the indicator 80. Realizing that this count is circular, it can be seen that the selection is done immediately after reading the PROM 82 and 255 x 16.667 ms (4.27 sec) thereafter.
The parameter display is a three-digit number in per unit format, the parameter being displayed is identified by a numeric code which appears concurrently with the parameter value in the left-most digit of the numeric display 80, as follows:
1. Present Phase Current
2. Long Delay Pick Up
3. Long Delay Time
4. Short Delay Pick Up
5. Short Delay Time
6. Ground Fault Pick Up
7. Ground Fault Time
8. Instantaneous Trip Level
9. Present Ground Current
When the counter reaches 125 (2.1 sec) and if an error was found in the self-checking routine, an error code will be displayed in the indicator 80 instead of a parameter value: 1 for AID conversion failure or instantaneous trip function failure, 2 for short delay function failure, 3 for ground trip function failure, and 4 to indicate that minimum settings are being used.This will cause the indicator 80 to change from parameter value to error code every two seconds, indicating to the user that an error was found.
Detailed Description of Operation
This section will describe, in detail, the function blocks shown in the general flow diagram. Reference should be made to the flow diagrams presented for each block.
Considering the instantaneous trip function and short delay trip function test, refer to the flow chart of
Figure 9. Upon entering those two routines, the micro-computer 154 switches the D/A converter IC4 analog output to the phase peak detecting circuitry through resistors 108, 110 and 112, having values of 6.8K, 220K, and 220K, respectively. This produces a scale factor of 1 p.u. (with a digital representation of 160). The AID conversion (Figure 8) subroutine is now called which lasts 0.26 ms (104 instructions x 2.5 Fcs average execution time).
The A/D conversion subroutine operates by clearing the accumulator, then setting the most significant bit thereof as a test value. This value is sent to the D/A converter which produces a corresponding analog value.
This analog value is compared to the phase current value provided by the peak detecting capacitor 90. If the trial analog value is smaller than the phase current, then the trial value consisting of one bit is added to the digital successive approximation of the phase current value which is retained in register R3. The test bit in the accumulator is then shifted one place to the right, a corresponding analog test value generated, a comparison made, and the bit is retained or not in register R3 according to the results of the comparison. In a similar manner all eight bits of the accumulator are tested and at the completion of the eighth bit, the retained value in R3 is transferred to the accumulator.
The digital value of present phase current (PPC) is then stored in RAM 155 in order to be displayed and used in the Short Delay routine. If PPC is greater than the instantaneous trip setting (ITS), a tripping operation is executed, which includes the function of saving the current value which caused the trip (to be displayed on indicator 80) and lighting the proper LED 84,86 or 88 to indicate cause-of-trip. Otherwise, the short delay trip function is entered.
In the Short Delay routine, a tally is incremented every cycle if the PPC is larger than the short delay pickup.
The tally is then compared to a value corresponding to the short delay time setting (SDT). If the tally is greater than the SDT vaue, a trip operation is called for. Otherwise, the Long Delay Test routine is entered. If the PPC is smaller than the short delay pickup the short delay tally is reset to zero. At this point the Long
Delay Test (LDTST), as shown in Figure 10, is entered.
Upon entry, the LDTSTfunction switches (through IC3) to the phase peak detecting circuitry. However, this is done through resistors 114 and 116 having values of 3.3K and 220K, respectively (see Figure 6). Thus, the threshold level in the A/D conversion process is doubled. Keeping in mind that 1 p.u. was encoded as 16D in the instantaneous trip and short delay functions, it can be seen that now 1 p.u. is encoded as 32D (a resolution of 3.12%).
For long delay timing a quantity proportional to (i)2 must be calculated. This value is added to an accumulating register and then compared to the Long Delay Time (LDT) setting whenever the Long Delay
Pick-up (LDPU) setting is exceeded. The accumulating register then represents "(i)2t". The use of an example will illustrate the procedure used:
Suppose LDPU = 1 PU = 32 D
LDT = 2 sec
I (PPC) = 6 PU = 32 D x 6 = 192 D
i2 = (192)2 = 36,864 Instead of storing i2, however, the quantity i2/4 is retained since less memory space is required, and sufficient resolution still maintained. Thus:
i2/4 = 36,864/4 = 9216.
If i2/4 is accumulated into a tally of 24 bits every 1/60 of a second, in two seconds the tally will be:
9216 x 60 x 2 = 1,105,920 D which brings the upper eight bits of the tally to the value: 1,105,920/216= 17D Thus, an LDT setting for 2 seconds, encoded as 17 D or 11 H, is reached in exactly 2 seconds as desired.
Therefore, LDT setting = # of seconds x 17/2. It must be realized that with lower PPC the trip unit will take longer time to reach that count, and with larger PPC the trip unit will reach that count faster (time will be inversely related to (i)2).
Referring to the flow chart of Figure 10, it can be seen that when the PPC is less than LDPU the tally is decremented with a fixed value of A4 H = 164 D. This number represents the (LDP min)2/4 or (.8 x 32 D)2/4 = 164D.
The ground fault test function is now performed. In prior art trip units, on non-ground faults in which the phase current is between three and ten times the breaker frame rating, the ground fault pick-up is desensitized so that the fictitious ground fault current (an artifact of the current transformers) will not cause an improper trip. In the present trip unit as can be seen in the flow chart of Figure 11, further corrective action is provided. The ground fault pick-up is desensitized, as in the prior art, when PPC is greater than or equal to 7.0 PU; however, for PPC between 1.0 and 7.0 PU, the fictitious ground current is accounted for by subtracting from the ground current sensed, the PPC divided by 4. This method could, of course, be accomplished by other means, such as analog circuitry.
If the present ground current is greater than the ground current pick-up setting, the ground interlock output is set, to signal other breakers that this breaker is monitoring of a ground fault. Next a tally similar to the short delay tally is incremented. If this tally is now greater than the ground fault tally trip value, a trip operation is performed. Otherwise, the program enters the self-checking routine.
If the present ground current is less than the ground current pick-up setting, but greater than 1/2 the setting, the ground interlock output is set. In addition, for all values of ground current less than the setting, the tally is decremented (not reset as in Short Delay) and the self-checking routine.
Refer to the self-checking routine in Figure 12. This routine, performed every cycle, resets the peak-detecting capacitors 90 and 91 and checks the running tally of ground fault and short delay functions, alerting the user to a malfunction of the main loop. This is done by setting flags which are checked every 2.1 seconds in the main loop, and storing an error code. If the flag is set, the main loop causes an error code number to appear on the numeric display 80. Thus, instead of a four-second display of parameter values, there would be alternate 2.1 second displays of error codes and parameter values.
As stated previously, the READ routine shown in Figure 13 allows the user to reprogram the external PROM chip 16timesvia a PROM programmer. It also loads minimum settingsforthe breaker, if the PROM was not correctly programmed or the PROM is missing.
As an example, the settings may be encoded in PROM 82 as follows:
EXAMPLE
(x 32) LDPU of .8 PU = .8 x 32 = 26 D =1AH
(x8.5) LDT of 2sec = 2 x 8.5 = 17 D =11H
(x16) SDPU of 1.5 PU = 1.5 x 16 = 24 D = 18 H (;:1) SDT of 20 cycles = 20 x 1 = 20 D =14H (x 64) GFP of .2 PU = .2 x 64 = 12.8 D =ODH (xl) GFT of 20 cycles = 20 x 1 = 20 D =14H (x16) ITC of 8.0 PU =8x16 = 128 D = 80 H
In this format the settings are ready to be used by the program. However, in order to be displayed (every 4 seconds) they must be each converted to recognizable decimal characters.
Thus, every display routine calls a routine to convert the integer and fraction portions of the display value from hex format to BDC. The BCD values are then converted to 7-segment format by the latch decoders.
IDENTIFICATION OF REFERENCE NUMERALS USED IN THE DRAWINGS
LEGEND REF. NO. FIGURE
BEGIN F1 7
UPDATE ADDRESS OF N. DISPLAY F2 7
INSTANTANEOUS TRIP FUNCTION F3 7
SHORT-DELAY TRIP FUNCTION F4 7
LONG DELAY TRIP FUNCTION F5 7 GOD TRIP FUNCTION F6 7
A/D CONVERSION F7 7
SELF-CHECKING F8 7
RESET PHASE PEAK DETECTING CAPACITOR F9 7
DELAY = 16.667 - SOFTWARE TIME F10 7 COUNTER=COUNTER-1 F11 7
HAS THE BREAKER TRIPPED F12 7
DISPLAY TRIP VALUE F13 7
IS COUNT = 125 (T=25EC) F14 7
SELF CHECKING OK F15 7
DISPLAY ERROR CODE F16 7
POWER ON RESET OR RESET PUSH BUTTON F17 7
CLEAR TRIP INDICATION DISPLAY 0 000 F18 7
CLEAR RAM F19 7
MECHANISM 20 2
DISCRIMINATORY TRIP FUNCTION F20 7
IDENTIFICATION OF REFERENCE NUMERALS USED IN THE DRAWINGS
LEGEND REF. NO FIGURE
COUNTER = COUNTER-1 F21 7
TRIP COIL 22 2
IS COUNT = 255 OR T = 4 SEC7 F22 7
READ PROM F23 7
IS CHECK SUM VALID F24 7
LOAD MINIMUM SETTINGS F25 7
TRIP UNIT 26 2
IS COUNT = 254 F26 7
DISPLAY NEXT FUNCTION F27 7 8-- > COUNTER; 0-- > ACC; 0 < R2,R3; SET CARRY F28 8
PREVIOUS POSITION IN ACC. F29 8 SHIFTTEST BIT RIGHT F30 8
SAVE ITIN R2 F31 8
MANUAL CONTROL 32 2
ADD TO RETAINED VALUE F32 8
COMPARE IT WITH ANALOG INPUT F33 8
IS IT LARGER F34 8
RESET BIT F35 8
SAVE BIT IN R3 F36 8
IS COUNTER-1 = 0 F37 8
TRY NEXT BIT POSITION F38 8
RETAINED VALUE IN ACC. F39 8
SWITCH TO INSTANTANEOUS PEAK DETECTING
CIRCUITRY F40 9
DO A/D CONVERSION F41 9
STORE PPC F42 9
IS PPC # ITS F43 9
TRIP & STORE VALUE F44 9 IS PPC 3 SDP F45 9
TALLY = TALLY + 1 F46 9
IS TALLY # SDT F47 9
IDENTIFICATION OF REFERENCE NUMERALS USED IN THE DRAWINGS
LEGEND REF. NO.FIGURE
TRIP & STORE VALUE F49 9 SUM4 = TALLY = F49 9 SWITCH TO LD ACCURACTY 1.0 = 32D F50 10
DO A/D CONVERSION F51 10
SAVE PPC F52 10
IS PPC3LDPU F53 10
TALLY = TALLY - A4H F54 10 DO (PPC)2/4 F55 10
SOURCE 1 56 2 SAVE (PPC)2/4 F56 10
SAVE (PPC)2/4 TO TALLY F57 10
SOURCE 2 58 2
STORE NEWTALLY F58 10
IS UPPER BYTE OF TALLY LDT F59 10
TRIP & SAVE VALUE F60 10
SWITCH TO GROUND PEAK DETECTING CIRCUITRY F61 11
DO A/D CONVERSION & STORE F62 11
IS PPC > 7.0 PU F63 11
SKIP GROUND TEST F64 11 IS PPC 1.0 F65 11 GROUND CURRENT = ACTUAL VALUE - PPC/4 F66 11 IS GROUND CURRENT 3 SETTING F67 SETTING F67 11 SET GROUND INTERLOCK OUTPUT F68 11
TALLY = TALLY + 1 F69 11
IS TALLY # GFT F70 11
TRIP & SAVE VALUE F71 11 IS GROUND CURRENT # SETTING/2 F 72 11
SET GROUND INTERLOCK OUTPUT
F 73 11
IDENTIFICATION OF REFERENCE NUMERALS USED IN THE DRAWINGS
LEGEND REF. NO. FIGURE
TALLY = TALLY -1 F74 11
SFCHK F75 12
DISCHARGE PEAK DETECTING CAPACITOR F76 12 IS PPC =0 F77 12
A/D CONVERSION FAILURE F78 12
DISPLAY SECTION 79 5
SET FLAG F79 12
RETURN F80 12
IS PPC ITS F81 12
EXTERNAL PROM 82 5
FAILURE ON ITS FUNCTION F82 12
SET FLAG F83 12
RETURN F84 12
IS PPC 3 SDP F85 12
INCREMENTSUM 4S S86 12
IS SUM 4S = SUM4
F 87 12
FAILURE ON SDP FUNCTION
F 88 12
SET FLAG F89 12
RETURN F90 12
LOAD PGC F91 12
INTERVAL TIMER 92 5 IS PGC 3 GFP F 92 12 ISTALLY=SUM6S-1 F93 12 OUTPUTSUBSYS. 1/21C 2, IC10, IC11 94 5 RETURN F94 12 ISTALLY=SUM6S+1 F95 12
FAILURE ON GFP FUNCTION F96 12
IDENTIFICATION OF REFERENCE NUMERALS USED IN THE DRAWINGS
LEGEND REF. NO. FIGURE
SET FLAG F97 12
DELAY F98 12 IS SUM 4 = F99 12
READ F100 13
SET ADDRESS = H F101 13
READ PROM F102 13
IS CONTENT = 4)4)OR = FFH F103 13
VIRGIN PROM OR NO PROM IN SOCKET LOAD
MINIMUM SETTINGS F104 13 SETERROR FLAG F105 13
RETURN F106 13
ADDRESS = ADDRESS +1H F107 13
READ PROM F108 13 IS CONTENT= OOH OR = FFH F109 13
IS ADDRESS = FH LASTTRY F110 13
ADDRESS = ADDRESS - 1 0H F111 13
READ NEXT 26 LOCATIONS F112 13
IS CHECK SUM VALID F113 13
LOAD SETTINGS IN CORRESPONDING RAM LOCATION F114 13
RETURN F115 13
LOAD MINIMUM SETTINGS F116 13
SET ERROR FLAG F117 13
RETURN F118 13
Claims (43)
1. Circuit interrupter apparatus, comprising contacts for connection to an associated circuit to be protected; interrupter means operable to open said contacts; sensing and powering means for sensing current flow through the contacts and providing a digital signal related to the current sensed, and for providing operating power for said apparatus; and digital processor means connected to and empowered by said sensing and powering means for receiving said digital signal, and connected to said interrupter means for effecting contact opening operation thereof when said digital signal attains a predetermined value.
2. Circuit interrupter apparatus as claimed in claim 1, wherein said digital processor means comprises a microcomputer.
3. Circuit interrupter apparatus as claimed in claim 1 or 2, including a read-write memory means interconnected with said digital processor means for storing a value related to said current, and retrieving means interconnected with said processor means and said read-write memory means for retrieving the stored value from said read-write memory means after said processor means has effected said contact opening operation.
4. Circuit interrupter apparatus as claimed in claim 3, wherein said read-write memory means comprises a semiconductor random access memory connected to said digital processor means.
5. Circuit interrupter apparatus as claimed in claim 4, wherein said digital processor means and said semiconductor random-access memory are contained in a common electrical circuit chip.
6. Circuit interrupter apparatus as claimed in any of the preceding claims, including predetermined value means connected to said digital processor means for providing said predetermined value thereto, said predetermined value means being adjustable.
7. Circuit interrupter apparatus as claimed in claim 6, wherein said predetermined value means comprises a memory means providing said predetermined value in digital form.
8. Circuit interrupter apparatus as claimed in claim 7, wherein said memory means comprises an interchangeable semiconductor memory array removably insertable into an exterior surface of the circuit interrupter apparatus.
9. Circuit interrupter apparatus as claimed in-claim 7 or 8, wherein said memory means comprises a read-only memory.
10. Circuit interrupter apparatus as claimed in claim 9, wherein said read-only memory is a programmable read-only memory.
11, Circuit interrupter apparatus as claimed in claim 9 or 10, wherein said read-only memory is a plug-in type memory.
12. Circuit interrupter apparatus as claimed in claim 7, wherein said memory means is digitally programmable.
13. Circuit interrupter apparatus as claimed in any of the preceding claims, including instruction means connected to said digital processor means for providing the latter with instructions assisting in the operation thereof.
14. Circuit interrupter apparatus as claimed in claim 13, wherein said operation is periodic.
15. Circuit interrupter apparatus as claimed in claim 13 or 14, wherein said instruction means provides said instructions in digital form.
16. Circuit interrupter apparatus as claimed in claim 13, 14 or 15, wherein said instruction means comprises an instruction memory means.
17. Circuit interrupter apparatus as claimed in claim 16, wherein said instruction memory means is digitally programmable.
18. Circuit interrupter apparatus as claimed in claim 1, including storage means for storing a time-current tripping characteristic, electronic means connected to the output of said sensing and powering means, to said storage means, and to said interrupter means for analyzing electrical parameters on said associated circuit and for operating said interrupter means when current flow therethrough exceeds said time-current tripping characteristic; and numeric display means interconnected with said electronic means and visible from the exterior of the apparatus for displaying a numerical representation of said parameters.
19. Circuit interrupter apparatus as claimed in claim 18, including additional power supply means interconnected with said numeric display means for supplying power thereto after operation of said interrupter means.
20. Circuit interrupter apparatus as claimed in claim 18 or 19, including separate additional power supply means interconnected with said electronic means for supplying power thereto after operation of said interrupter means.
21. Circuit interrupter apparatus as claimed in claim 18, 19 or 20, including memory means for storing a value corresponding to the value of current flow through said contacts at which operation of said interrupter means was initiated, said numeric display means being interconnected with said memory means for displaying said stored value.
22. Circuit interrupter apparatus as claimed in claim 21, wherein said memory means comprises a read-write memory.
23. Circuit interrupter apparatus as claimed in any of claims 18 to 22, wherein said storage means comprises means for storing a multifunction time-current trip characteristic, and said processor means comprises means for identifying each function of said multi-function trip characteristic with a numeric label, and means operable upon operation of said interrupter means for supplying to said display means the numeric label of the function of the multifunction time-current trip characteristic which was exceeded by current flow through said contacts to cause operation of the interrupter means, whereby said numeric display means displays cause-of-trip information.
24. Circuit interrupter apparatus as claimed in claim 23, wherein said numeric label comprises a single-digit numerical value.
25. Circuit interrupter apparatus as claimed in any of the claims 18 to 24, wherein said electronic means comprises a microcomputer including means for storing a plurality of instructions which cause said microcomputer to sequentially display a series of numeric values corresponding to the electrical status of said interrupter means and to parameters defining said time-current tripping characteristic.
26. Circuit interrupter apparatus as claimed in any of claims 18 to 25, wherein said numeric display means comprises a liquid crystal display.
27. Circuit interrupter apparatus as claimed in claim 1, including interlock means connected to the sensing and powering means and to said interrupter means for preventing operation of the interrupter means uniess the power from the powering means has attained a predetermined minimum value.
28. Circuit interrupter apparatus as claimed in claim 1, wherein said current is an alternating current, and said sensing and powering means includes a peak detector which senses the peak value of said alternating current, said digital signal being related to said peak value, and reset means for resetting said peak detector, said digital processor means adapted to reset said peak detector once each cycle of said alternating current.
29. Circuit interrupter apparatus as claimed in claim 1, wherein said digital processor means has an output at which both memory data for storage and display data for indication are provided, said apparatus including latchable storage means connected to said output for receiving and storing said memory data, said latchable storage means being latched after said memory data is received and stored so that subsequently provided display data is ignored by said latchable storage means until the latter means is unlatched, and display means connected to said latchable storage means for receiving and displaying said display data.
30. Circuit interrupter apparatus as claimed in claim 1,wherein said sensing and powering means includes sensing means for sensing said current and for providing an analog signal related thereto, said apparatus including analog comparator means having one input thereof connected to receive said analog signal from said sensing means, the output of said analog comparator means providing a digital signal when a feedback analog signal on another input of said comparator means said and analog signal have different values, said digital processor means having an output port on which sequentially increasing digital levels are generated by the processor means, and digital-to-analog means having an input thereof connected to receive said digital levels and having an output thereof connected to said other input terminal of said analog comparator means to provide said feedback analog signal thereto in relation to said digital levels.
31. Circuit interrupter apparatus as claimed in claim 1, wherein the sensing means provides said digital signal with controllable resolution, and the processor means is operable to execute a plurality of operating functions, said processor means providing a feedback signal to said sensing means for controlling the resolution thereof in correspondence with the operating function being executed by the digital processor means.
32. Circuit interrupter apparatus as claimed in claim 30 or 31, wherein the feedback signal is derived from a switchable voltage divider.
33. Circuit interrupter apparatus as claimed in claim 1, wherein the sensing means comprises phase current sensing means, and ground fault current sensing means for sensing ground fault current and for providing a digital representation of said ground fault current, said digital processor means being connected to said phase current and ground fault current sensing means to receive said digital representation, and being connected to said interrupter means to operate same when a test quantity related to said digital representation exceeds a first predetermined value, said processor means setting said test quantity equal to said digital representation when phase current flow through said contacts is below a second predetermined value, setting said test quantity equal to a first corrected value less than said digital representation when said phase current flow attains said second predetermined value, and setting said test quantity equal to a second corrected value less than said first corrected value when said phase current flow attains a third predetermined value.
34. Circuit interrupter apparatus as claimed in claim 1, including display means interconnected with said processor means for displaying concurrently a parameter value and a code value identifying said parameter value, both of said values being supplied by said processor means.
35. Circuit interrupter apparatus as claimed in claim 1, wherein the processor means is adapted to effect contact opening operation of said interrupter means when the sensed current flow exceeds one of several possible trip currents as defined by a time-current trip characteristic, said apparatus including a plurality of light emitting indicators disposed on the exterior surface of said apparatus and connected to the processor means, said processor means energizing one of said light emitting indicators, upon operation of said interrupter means, according to which of said trip currents is exceeded by the sensed current flow.
36. Circuit interrupter apparatus as claimed in claim 1, including numeric display means mounted on an external surface of said apparatus and connected to the processor means, said processor means supplying a numeric error code thereto for display upon detection of improper operation within the processor means, which error code corresponds to the component of said processor means which is operating improperly.
37. Circuit interrupter apparatus as claimed in claim 1, wherein said digital processor means has programmably stored therein a first representationof a time-current tripping chracteristic from which said predetermined value is normally chosen, and has generally permanently stored therein a second representation of a time-current tripping characteristic from which said predetermined value may be chosen in the event said first representation is not utilized, said apparatus including detecting means interconnected with said processor means for detecting when said first representation should not be utilized and for thus causing utilization of said second representation.
38. Circuit interrupter apparatus as claimed in claim 37, wherein the second time-current characteristic is conservative relative to the first time-current characteristic.
39. Circuit interrupter apparatus as claimed in claim 37 or 38, wherein the first time-current characteristic is not utilized because of incorrect programming thereof.
40. Circuit interrupter apparatus as claimed in claim 37 or 38, wherein the first time-current characteristic is not utilized because of an electrical problem associated therewith.
41. Circuit interrupter apparatus as claimed in claim 37, wherein the first time-current characteristic is stored in a detachable memory, and is not utilized because of improper connection thereof in said processor means.
42. Circuit interrupter apparatus as claimed in claim 1, including interchangeable programmable memory means removably connected to the processor means for storing a representation of desired time-current tripping characteristics of said apparauts, said memory means comprising a plurality of memory locations, the number of which locations is an integral multiple of the number of parameters necessary to define the desired time-current tripping characteristics of said apparatus, said processor means selecting the last set of parameters of the multiple sets stored in said memory means for use in limit check operations.
43. A circuit interrupter apparatus comprising interrupter means for conducting current flow through an associated circuit and for interrupting said current flow upon command; sensing and powering means for sensing current flow through said interrupter means and for supplying operating power to said apparatus; converting means for converting analog signals to digital values, said conversion means having its input operatively connected to said sensing and powering means; a digital arithmetic logic and control processor having its input connected to the output of the analog-to-digital converter means and its output connected to said interrupter means; instruction memory means connected to said digital arithmetic logic and control processor for storing sequential commands to the processor; and limit value means connected to said processor for storing a digital representation of the desired time-current trip characteristic of said apparatus, said processor executing commands stored in said instruction memory means to periodically generate signals to cause said conversion means to supply a digital representation of the current flow value through said interrupter means, and comprising said current flow value representation with the digital representation of said time-current trip characteristic stored in said limit value memory means, said processor generating a command signal effecting a circuit interrupting operation of said interrupter means when the current flow therethrough exceeds said time-current trip characteristic.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14063180A | 1980-04-15 | 1980-04-15 | |
US06/140,632 US4377836A (en) | 1980-04-15 | 1980-04-15 | Circuit interrupter with solid state digital trip unit and positive power-up feature |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2073969A true GB2073969A (en) | 1981-10-21 |
GB2073969B GB2073969B (en) | 1984-09-26 |
Family
ID=26838358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8111092A Expired GB2073969B (en) | 1980-04-15 | 1981-04-09 | Circuit interrupter apparatus |
Country Status (9)
Country | Link |
---|---|
AU (1) | AU549018B2 (en) |
BR (1) | BR8102310A (en) |
CH (1) | CH658755A5 (en) |
FR (1) | FR2481534B1 (en) |
GB (1) | GB2073969B (en) |
IE (1) | IE51346B1 (en) |
IT (1) | IT1137369B (en) |
MX (1) | MX154859A (en) |
NZ (1) | NZ196611A (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4423458A (en) | 1982-04-05 | 1983-12-27 | Siemens-Allis, Inc. | Signal processing system for overload relay or the like |
US4423459A (en) | 1982-04-05 | 1983-12-27 | Siemens-Allis, Inc. | Solid state circuit protection system and method |
US4446498A (en) * | 1982-04-05 | 1984-05-01 | Siemens-Allis, Inc. | Electronic control system for overload relay or the like |
US4456871A (en) * | 1982-04-05 | 1984-06-26 | Siemens-Allis, Inc. | Power supply for electronic control system |
FR2578090A1 (en) * | 1985-02-25 | 1986-08-29 | Merlin Gerin | CIRCUIT BREAKER WITH DIGITAL STATIC TRIGGER WITH REVERSE TIME TRIGGERING FUNCTION |
FR2578091A1 (en) * | 1985-02-25 | 1986-08-29 | Merlin Gerin | CIRCUIT BREAKER WITH DIGITAL STATIC TRIGGER PROVIDED WITH A CALIBRATION CIRCUIT |
FR2592532A1 (en) * | 1984-06-29 | 1987-07-03 | Gen Electric | CIRCUIT BREAKER WITH PROTECTION RELAY. |
FR2595170A1 (en) * | 1986-03-03 | 1987-09-04 | Mors | ELECTRONIC PROTECTION METHOD OF ELECTRIC MOTOR AND DEVICE FOR IMPLEMENTING SAID METHOD |
EP0253009A1 (en) * | 1985-03-07 | 1988-01-20 | Mitsubishi Denki Kabushiki Kaisha | Inverse-time relay |
EP0279690A2 (en) * | 1987-02-20 | 1988-08-24 | Westinghouse Electric Corporation | Circuit interrupter apparatus with a style saving rating plug |
GB2226464A (en) * | 1988-11-16 | 1990-06-27 | Ohbayashi Corp | Power control apparatus |
FR2776433A1 (en) * | 1998-03-05 | 1999-09-24 | Gen Electric | METHOD FOR INITIALIZING EARTH DEFECT AND SHORT-TERM PROTECTION HEAT INDEX ACCUMULATORS IN A CIRCUIT BREAKER |
US8355230B2 (en) | 2003-12-08 | 2013-01-15 | Siemens Industry, Inc. | Extended instantaneous protection |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4752853A (en) * | 1987-02-20 | 1988-06-21 | Westinghouse Electric Corp. | Circuit interrupter apparatus with an integral trip curve display |
US4827369A (en) * | 1987-02-20 | 1989-05-02 | Westinghouse Electric Corp. | Circuit interrupter apparatus with a selectable display means |
JP2604015B2 (en) * | 1988-09-09 | 1997-04-23 | 日本碍子株式会社 | Distribution line monitoring system |
JPH0284014A (en) * | 1988-09-20 | 1990-03-26 | Ngk Insulators Ltd | Distribution line monitoring system |
AT399429B (en) * | 1989-06-06 | 1995-05-26 | Gec Alsthom T & D Gmbh | ELECTRONIC DEVICE WITH A PLUG UNIT FOR SWITCHING MONITORING OF SWITCHGEAR |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2609654B2 (en) * | 1976-03-09 | 1978-01-05 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | DIGITAL OVERCURRENT RELEASE |
FR2412079A1 (en) * | 1977-12-13 | 1979-07-13 | Electricite De France | Electrical power distribution network fault detector - has FET switches with low-pass filter providing blocking signals for isolating circuit at multivibrator output |
ES468764A1 (en) * | 1978-04-13 | 1979-10-01 | Arteche Instr Sistemas | A new delayed action electrical protection device, depending on an adjusted magnitude. |
GB2020124B (en) * | 1978-04-27 | 1982-08-25 | Tokyo Shibaura Electric Co | Overcurrent protection |
JPS55127821A (en) * | 1979-03-27 | 1980-10-03 | Tokyo Shibaura Electric Co | Digital protection relay unit |
US4339802A (en) * | 1979-08-10 | 1982-07-13 | Tokyo Shibaura Denki Kabushiki Kaisha | Digital protective relaying devices |
US4319298A (en) * | 1979-08-28 | 1982-03-09 | General Electric Company | Motor protection device |
EP0047749A1 (en) * | 1980-02-23 | 1982-03-24 | George Ellison Limited | Overcurrent protection devices |
-
1981
- 1981-03-24 NZ NZ196611A patent/NZ196611A/en unknown
- 1981-03-25 AU AU68732/81A patent/AU549018B2/en not_active Expired
- 1981-03-31 IE IE731/81A patent/IE51346B1/en not_active IP Right Cessation
- 1981-04-09 GB GB8111092A patent/GB2073969B/en not_active Expired
- 1981-04-14 MX MX186850A patent/MX154859A/en unknown
- 1981-04-14 CH CH2498/81A patent/CH658755A5/en not_active IP Right Cessation
- 1981-04-14 IT IT21171/81A patent/IT1137369B/en active
- 1981-04-14 BR BR8102310A patent/BR8102310A/en not_active IP Right Cessation
- 1981-04-15 FR FR8107623A patent/FR2481534B1/en not_active Expired
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4423459A (en) | 1982-04-05 | 1983-12-27 | Siemens-Allis, Inc. | Solid state circuit protection system and method |
US4446498A (en) * | 1982-04-05 | 1984-05-01 | Siemens-Allis, Inc. | Electronic control system for overload relay or the like |
US4456871A (en) * | 1982-04-05 | 1984-06-26 | Siemens-Allis, Inc. | Power supply for electronic control system |
US4423458A (en) | 1982-04-05 | 1983-12-27 | Siemens-Allis, Inc. | Signal processing system for overload relay or the like |
FR2592532A1 (en) * | 1984-06-29 | 1987-07-03 | Gen Electric | CIRCUIT BREAKER WITH PROTECTION RELAY. |
US4717985A (en) * | 1985-02-25 | 1988-01-05 | Merlin Gerin S.A. | Circuit breaker with digitized solid-state trip unit with inverse time tripping function |
FR2578090A1 (en) * | 1985-02-25 | 1986-08-29 | Merlin Gerin | CIRCUIT BREAKER WITH DIGITAL STATIC TRIGGER WITH REVERSE TIME TRIGGERING FUNCTION |
FR2578091A1 (en) * | 1985-02-25 | 1986-08-29 | Merlin Gerin | CIRCUIT BREAKER WITH DIGITAL STATIC TRIGGER PROVIDED WITH A CALIBRATION CIRCUIT |
EP0193447A1 (en) * | 1985-02-25 | 1986-09-03 | Merlin Gerin | Static numerical circuit interrupter having a calibration circuit |
EP0194176A1 (en) * | 1985-02-25 | 1986-09-10 | Merlin Gerin | Static numerical circuit interrupter with an inverse time-tripping function |
US4682264A (en) * | 1985-02-25 | 1987-07-21 | Merlin Gerin | Circuit breaker with digital solid-state trip unit fitted with a calibration circuit |
US4769735A (en) * | 1985-03-07 | 1988-09-06 | Mitsubishi Denki Kabushiki Kaisha | Inverse-time relay |
EP0253009A1 (en) * | 1985-03-07 | 1988-01-20 | Mitsubishi Denki Kabushiki Kaisha | Inverse-time relay |
EP0237412A1 (en) * | 1986-03-03 | 1987-09-16 | Mors | Process for the electronic protection of an electrical motor and device for carrying it out |
FR2595170A1 (en) * | 1986-03-03 | 1987-09-04 | Mors | ELECTRONIC PROTECTION METHOD OF ELECTRIC MOTOR AND DEVICE FOR IMPLEMENTING SAID METHOD |
EP0279690A2 (en) * | 1987-02-20 | 1988-08-24 | Westinghouse Electric Corporation | Circuit interrupter apparatus with a style saving rating plug |
EP0279690A3 (en) * | 1987-02-20 | 1989-11-08 | Westinghouse Electric Corporation | Circuit interrupter apparatus with a style saving rating plug |
GB2226464A (en) * | 1988-11-16 | 1990-06-27 | Ohbayashi Corp | Power control apparatus |
US5019956A (en) * | 1988-11-16 | 1991-05-28 | Ohbayashi Corporation | Power control apparatus |
GB2226464B (en) * | 1988-11-16 | 1992-12-02 | Ohbayashi Corp | Power control apparatus |
FR2776433A1 (en) * | 1998-03-05 | 1999-09-24 | Gen Electric | METHOD FOR INITIALIZING EARTH DEFECT AND SHORT-TERM PROTECTION HEAT INDEX ACCUMULATORS IN A CIRCUIT BREAKER |
US8355230B2 (en) | 2003-12-08 | 2013-01-15 | Siemens Industry, Inc. | Extended instantaneous protection |
Also Published As
Publication number | Publication date |
---|---|
CH658755A5 (en) | 1986-11-28 |
NZ196611A (en) | 1985-07-31 |
FR2481534A1 (en) | 1981-10-30 |
BR8102310A (en) | 1981-12-08 |
FR2481534B1 (en) | 1986-12-26 |
IE810731L (en) | 1981-10-15 |
AU549018B2 (en) | 1986-01-09 |
IE51346B1 (en) | 1986-12-10 |
IT8121171A0 (en) | 1981-04-14 |
MX154859A (en) | 1987-12-22 |
AU6873281A (en) | 1981-10-22 |
GB2073969B (en) | 1984-09-26 |
IT1137369B (en) | 1986-09-10 |
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Legal Events
Date | Code | Title | Description |
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PE20 | Patent expired after termination of 20 years |
Effective date: 20010408 |