GB2069795A - Solid state digital television cameras - Google Patents

Abstract

A solid state digital television camera has a solid state image sensing device 1, 2 an analog-to-digital converter 3.33 for converting the output of the image sensing device 1, 2 to a digital colour signal, a filter 6, 36 for providing a predetermined filter characteristic to the digital colour signal, and a digital colour modulator 21, 41 for modulating the output of the filter 6, 36 to produce a digital modulated signal. The processing rate between the solid state image sensing device 1, 2 and the filter 6, 36 is the same as the sampling rate of the solid state image sensing device 1, 2, or n DIVIDED m.p .fsc (eg. 4 DIVIDED 3 fsc) where fsc is a colour sub-carrier frequency, p is 3 or 4, and m and n are small integers. The processing rate for the remaining circuitry is pfsc (eg. 4 fsc). In addition, a digital-to-digital converter 20, 40 for converting the processing rate from n DIVIDED m. p.fsc to pfsc is provided between the filter 6, 36 and the digital colour modulator 21, 41. Thus, the digital television camera is operated at a relatively slow sampling drive rate and hence is suitable for integrated circuit construction. <IMAGE>

Description

SPECIFICATION Solid state digital television cameras This invention relates to solid state digital television cameras.

A colour television camera has been proposed in which an image pick-up output signal derived from a solid state image sensing device, this being an analog signal, is subjected to a digital intermediate process and a standard analog colour television signal is finally produced. As compared with conventional colour television cameras in which a colour television signal is analog-processed throughout, such a television camera is particularly advantageous in the signal processing, the circuit construction and reliability. Moreover, digital signal processing in colour television cameras has recently been more favoured in order to permit interfacing with other digital equipment.

When digitally processing the image pick-up output signal to produce a colourtelevision signal, the processing rate in producing a digital modulated colour signal is normally selected to be three or four times the colour sub-carrier frequency fsc. This selection is made not only in consideration of the colour sub-carrier frequency fsc of the standard colour television signal, but also of the band width of a video signal, and of easy processing of the signal when the video signal is considered as a two-dimensional sampling system.

Accordingly, when 3fisc or 4fsc is selected as the frequency of a reference clock signal, all the circuits for the digital processing must operate art a rate of 3fsc or 4fisc, for example, the frequency of a drive pulse signal for driving the solid state image sensing device, the sampling rate of a sampling pulse signal for sampling-holding the output of the solid state image sensing device, and the processing rate for converting the image sensing output from its analog form to its digital form. However, if this reference clock is used for processing in the circuit system, the frequency exceeds 10 MHz.Moreover, if a digital filter is used for limiting the frequency band of a colour signal, to provide a constant cut-off frequency, the number of delay elements used in the digital filter increases in proportion to the processing rate.

Therefore, a digital processing circuit of large scale is necessary, and this is difficult to form as an integrated circuit.

According to the present invention there is provided a solid state digital television camera having a solid state image sensing device from which dot sequential picture signals are picked up, the camera comprising: a solid state image sensing device for picking up a picture and producing electrical video signals; an analog-to-digital converter for converting said picked-up video signals to digital video signals; a digital filter for filtering said digital video signals; a digital colour modulator or encoder modulating a sub-carrier signal in the respective carrier phases with primary colour components individually produced from said digital filter; a digital-to-analog converter for converting the outputs of said digital colour modulatorto analog video signals; and a digital-to-digital converter located between said digital filter and said digital colour modulator for converting the outputs of said digital filter with a sampling drive rate of m. P fsc to the digital video signals with another sampling drive rate of p . fsc where fsc is a colour sub-carrier frequency, p is 3 or 4, and m and n are small integers, in which said analog-to-digital converter and said digital filter are driven at a sampling rate of n P fsc ,while said m digital-to-digital converter, said digital modulator and said digital-to-analog converter are driven at a sampling rate of p .

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure lisa diagram showing the spatial relation of sampling in two solid state image sensing devices; Figure 2 is a block diagram of one embodiment of the invention; Figure 3 is a block diagram of a gamma-correction circuit of the embodiment; Figure 4 is a graph used for explaining the operation of the circuit of Figure 3; Figure 5 is a block diagram of a filter of the embodiment; Figure 6 is a block diagram of a digital filter of the embodiment; Figure 7 is a block diagram of a digital-to-digital converter of the embodiment; Figure 8 is a block diagram of digital modulators of the embodiment; Figures 9A and 9B are vector diagrams used for explaining the operation of the embodiment;; Figures lotto 1 OF are waveform diagrams used for explaining the operation of the modulator of Figure 8.

The embodiment to be described is a colourtelevision camera using charge coupled devices (CCDs) as its image sensing device.

Referring to Figure lithe embodiment uses a two-chip type colour television camera, in which one COD 1 provides a green signal G only from its entire surface and another COD 2 provides a red signal R and a blue signal B alternately in a line sequential manner. In order to prevent aliasing noise from being generated and to improve the resolution in the horizontal direction, the spatial sampling phase between the CCDs 1 and 2 is shifted by T/2 where 7 is the pitch of the picture elements in the horizontal direction.

Referring to Figure 2, the image pick-up output, that is the red and blue signals Rand B, from the COD 2 is first converted to a 1-sample 8-bit digital signal or a word signal by an analog-to-digital (AID) converter 3 and the converted signal is supplied to a signal processing circuit 4. Since the input signal to the AID converter 3, or the output of the COD 2 is already sampled by the COD drive clock signal, the AID converter 3 only needs to quantize the output of the COD 2. The aforesaid signal processing implies the usual gamma-correction, white clip, pedestal clamp and soon.

The digital signal subjected to the above signal processing is supplied to a filter device 6. As shown, the filter device 6 comprises a simultaneous circuit 7 for making line sequential signals in to simultaneous form, a digital filter 8 for providing a desired filter characteristic, and a matrix circuit 9. The matrix cir cuit 9 functions to produce band-limited digital col our signals, that is a red signal CR and a blue signal OB, and also digital luminance signals YR and Ys. The digital filter 8 is a two-dimensional spatial filter, which is used to eliminate aliasing noise caused by the line sequential operation. The digital filter8 also band limits the luminance signal components and the colour signal components, and effects vertical aperture correction.

The signal processing system between the COD 2 and the filter device 6 operates at the sampling rate of the COD 2. In this example, the sampling rate of the COD 2 is 4fscI3(=Fs), so that the A/D converter 3, the signal processing circuit 4 and the filter device 6 all operate at the sampling rate 4fsc/3. A clock pulse signal OKF of this sampling rate is supplied from a clock pulse generator 10. The following digital processing circuits will operate based on a clock pulse signal OKB of 3fisc or 4f,,.

The digital colour signals CR and C8 from the matrix circuit 9 are supplied to a digital-to-digital (DID) converter 20 where the digital colour signal CR and C8 processed at the sampling rate of 4fsc13 are converted into digital colour signals CR and C8 with a sampling rate of 4fisc Thus converted digital colour signals CR and OB are fed to a digital colour mod ulator 21 where they are modulated to, for example, a quadratureg-phase signal.This modulated digital colour signal CR8 (=CR+C8) fed to a digital adder or mixer 23 where it is mixed with the digital luminance signal YR or YB which is delayed by a predetermined time at a digital delay circuit 22. Thus a digital video signal DVS1 is derived from the digital adder 23.

A digital synchronizing signal generator 24 is supplied with a pulse signal from the clock pulse generator 10 to produce a digital burst signal SB and a composite synchronizing signal SYNC, which are then added to the digital video signal DVS1 is then converted into an analog signal by a digital-toanalog (DIA) converter 102 and this analog signal is fed to an adder out mixer 103.

The green signal G derived from the COD 1 is also subjected to a similar digital process in an AID converter 33, a signal processing circuit 34, a filter device 36, a DID converter 40 and a digital colour modulator 41 to obtain a modulated digital signal This signal cm is fed to an adder or mixer 43 where it is ad led to a digital luminance signal YG from a digital delay circuit 42 to provide a digital video signal DVS2. This digital video signal DVS2 is supplied through a fH/2 digital delay line 105 and a DiAcon- verter 104 to the adder 103, where it is added to the digital video signal DVS1 to produce a standard analog television signal TVS.In this case, the filter device 36 is not provided with a simultaneous circuit.

The delay line 105 is provided following the adder 43 in orderto correct the time difference between the digital video signals DVS1 and DVS2 resulting from the offset 7/2 of the picture elements in the CCDs 1 and 2, such that the modulation axis advanced in phase at the digital colour modulator 41 is restored to be coincident with the spatial sampling phase of the green signal G. When the red and blue signals R and B are the same in spatial sampling phase as the green signal G, the delay line 105 is not required.

Some of the above-mentioned circuits will now be described in more detail.

Firstly, a digital camma-correction circuit 50 provided in the signal processing circuit 4 is shown in Figure 3. The gamma-correction circuit 50 comprises a read-only memory (ROM) 51 used as a look-up table, and latch circuit 52 and 53 provided at the input and output of the ROM 51. The ROM 51 stores therein a gamma-correction output code word corresponding to an input code word as shown in Fig urge 4. Accordingly, an 8-bit 1-word input code word, which is the latch output, is supplied to the ROM 51 to address it so that the addressed code word is read out. The latch circuits 52 and 53 are driven by the same clock pulse signal OKF and hence low speed elements may be used therefor. The ROM 51 has an input and output rate of 1:1 so that it can be constructed with a relatively simple logic circuit.

Figure 5 shows the filter device 6, in which the simultaneous circuit (or switcher) 7 includes a pair of cascade-connected delay elements 55 and 56 each having a delay time of 1 H, an adder 57 and an attenuator 58. The digital colour signal R or B from the signal processing circuit 4 and that delayed by 2H by the delay elements 55 and 56 are added together by the adder 57, and then the adder signal is fed to the attenuator 58 where the level of the added signal is attenuated to one half to perform vertical interpolation based on outputs of two horizontal lines with respect to the same colour signal.

This two-dimensional spatial filter acting as the vertical interpolator has the following transfer function H(v): H(v)=[1 + (w' )g where - is a delay element for two scanning lines in the vertical direction. Then, a switching circuit 59 following the attenuator 58 effects a switching operation at every line interval (1 H) to make the linesequential digital colour signals into simultaneous mode signals.

The digital colour signals R and B simultaneously arranged by the switching circuit 59 are respectively supplied to digital filters 8R and 8B to provide desired filter characteristics. The digital filters 8R and 8B are transversal type digital filters having symmetric impulse responses, in order to provide stabilised process and constant group delay characteristics.

Figure 6 shows one example of the digital filter 8R or 8B. This example is a septenary digital filter formed as a low-pass filter, in which six delay operators 61 to 66, each having a delay of 1IFs, are connected in series. An output of, for example, the delay operator 63 and outputs of three adders 67 to 69 are supplied through elements 70 to 73 having impulse response coefficients he to h3to an adder 74 to derive therefrom a digital colour signal R, or B, having a frequency band limited to about 800 KHz.

The delay operators 61 to 66 are supplied with the clock pulse signal CKF from the clock pulses generator 10 and the delay time in the horizontal direction is 1IFs, so that processing at low speed can be effected. The filter with the aforesaid construction also has constant group delay characteristics and hence there is delay error between the R or B channel and the G channel. The other digital filter 8B is constructed in the same manner.

Referring again to Figure 5, the band-limited digital colour signals R, and B, from the digital filters 8R and 8B are supplied to the matrix circuit 9 together with band-unlimited digital colour signals Rw and 8w so that the following digital luminance signals YR and YB are produced therefrom.

= = 0.30 RL + 0.25 RH Y8=0.11 B,+0.25BH where RH and BH are high frequency components of the digital colour signals Rw and Bw.

If the digital colour signals R, and BL passed through the matrix circuit 9 are expressed as CR and 08, these signals CR and CB are supplied to the D/D converter 20 (Figure 2) where they are subjected to the rate conversion process. The D/D conversion is a kind of interpolation so that the processing rate of Fs = 4f5J3 can be converted to that of F8, = 4fsc by newly interpolating two samples between respective samples of the digital colour signal CR or Ce.

Figure 7 shows one example of the D/D converter 20, in which rate conversion is effected by interpolation using linear approximation. Each of delay operators 80 and 81 comprising a D-type flip-flop for example is driven by the clock pulse signal CKB of frequency 4fsc and provide a delay of 1/4f,,. The delay operators 80 and 81 are connected in cascade.

Outputs of respective steps are supplied to an adder 82 in which an original output, an output delayed by 1/4f5cx and an output delayed by 1/2f,, are added together. The added output of the adder 82 is then fed to a level shift circuit 83 where its level is attenuated to one third.

By performing the above signal processing, two samples are newly interpolated between two original samples with a period of 1/4fsc so that conversion of the processing rate is carried out and an interval between two original samples is approximated to a straight line.

After matching of the processing rate, the digital colour signals CR and Cg are subjected to balanced modulation by the digital colour modulator 21 to provide the modulated digital colour signal CRIB. That is, in this example quadrature 2-phase modulation is performed. Therefore, the digital colour signals CR and OB are resolved into a component VRB which Is in-phase with the R-axis and a component URB of the quadrature axis.Figure 8 shows the balanced modulators 21 and 41, in which the digital colour signal Cs is supplied to a circuit 90 to derive therefrom a colour component Basin0 in-phase with the R-axis, where B is the level of a colour signal and 0 an angle between the vector B of the colour signal OB and the quadrature axis URB as shown in Figure 9A. In this example, 8 is about 30 . The circuit 90 also performs suitable level adjustment of the colour component.

Similarly, the digital colour signal OB is fed to another circuit 91 to derive therefrom a colour component BcosB on the quadrature axis URB after being suitably adjusted in level.

On the other hand, the digital colour signal CR is adjusted in level at a circuit 93 and then supplied to a subtractor 94 together with the output of the circuit 90 to derive therefrom a colour component (R-Bsin0) on the R-axis, or the VRB-axis. These in-phase components V08 and quadrature component URB are alternately obtained at every 1/2f,, by a switching circuit or data multiplexer 95 and are thereafter supplied to a multiplier or sign inverter96.The sign inverter 96 is supplied with a carrier fsc from the clock pulse generator 10, and performs multiplication by minus one in the former half of the carrier period and multiplication by plus one in the latter half of the carrier period so that the components V08 and URB are subjected to quadrature 2-phase modulation.

The digital colour modulator 41 provided in the green signal system is also constructed as a balanced modulator. Accordingly, the digital colour signal CG is supplied to circuits 97 and 98 where it is divided into a quadrature component URB and an in-phase component VRB. These components are switched at a frequency 2f5c at a data multiplexer 99 and then multiplied with the carrier, at a multiplier or sign inverter 100 to provide a digital modulated signal CG subjected to quadrature modulation. A further description forthe above will be below given with reference to the digital colour modulator 41 of Figure 8, and Figure 98.

The input signal CG to the digital colour modulator 41 (the signal CG has only an amplitude component and no phase component) is resolved into components on the VRB-axis and the URB-axis similarly to Figure 9A. In this case, the input signal CG provides video information which is advanced by z/2 pitch of a colour element from the signals CR and CB supplied by the Rand B chips as shown in Figure 1, so that it is expressed st' on the vector of Figure 9B.That is the signal (i' is shown a a position which is delayed by 135" from the vector G of the actual green colour.

Accordingly, in orderto produce the green colour signal C G corresponding to the actual green colour vector, which is also actually subjected to quadrature 2-phase mJodulation, a delay time of H/2 is necessary for CR and Ce. Forthis reason, as shown in Figure 2, the delay line 105 of time TH/2, or 1/2 of 3/4fsc, is connected following the adder 43. In this case, the clock pulse signal CKB from the clock pulse generator 10 is supplied to the D/A converter 102, and to a phaseshifter 101 where it is phase-corrected for correcting for the T/2 pitch, and then supplied to the D/A converter 104.

When producing the digital burst signal SB at the synchronizing signal generator 24, since the burst signal is opposite in phase relative to the U-axis, the burst signal is resolved into a component of the R-axis and a component of its orthogonal axis and code words corresponding to respective a;:es are stored in a memory. Thus, if the above code words are selectively missed at every 1/4fact a desired digital burst signal SB can be produced. In the practical case, a ROM is supplied with clock pulse signals Of fsc and 2fisc, a burst flag pulse signal and a horizontal synchronizing pulse signal, the latter signals being a synchronism with the formal signals. Thus, these signals logically produce the digital burst signal SB.

Figures 1 OA to 1 OF are views used for explaining the operation of the digital colour modulator 21. That is, Figure 10A shows the phase of a sub-carrierofan NTSC signal. Figure lOB illustrates the waveform of the signal of frequency 2fisc for switching the data multiplexer95, and Figure 100 shows components ob an output signal of the multiplexer 95. The waveform of a signal of frequency f= for switching the sign inverter 96 is shown in Figure 1 OD, and an output of the sign inverter 96 is depicted in Figure 1 OE. It is noticed from Figure 10E that the output of the digital colour modulator 21 is a signal subjected to quadrature 2-phase modulation.Figure 10F represents the phase of the digital burst signal fed to the adder 25.

As described above, the digital processing circuit system X (Figure 2) from the COD 1 (or 2) to the filter device 6 (or 36) is operated atthe sampling rate Fs = 4/3fisc of the COD 1 or 2, and the other digital processing circuit system Y (Figure 2) following the circuit system X operated at the rate of Fst = 4fsc, so that a digital processing circuit system X with low-speed operation can be used, and hence a relatively cheap digital circuit can be used. Also, matching of the processing rates can be achieved by the DID converter 20 which is relatively simple in circuit construction.

The system is suited to integrated circuitoonstruc- tion.

In the above embodiment, the processing rate of the digital processing circuit system Y is Fs' = 4fsc, but F8 = 3fsc is also usable. Also, in this embodiment, a two-chip type television camera is used, but a singie-chip type or three-chip type can also be used.

Moreover, the semiconductor image sensing devices may be MOS-type sensors.

Claims (8)

1. A solid state digital televison camera having a solid state image sensing device from which dot sequential picture signals are picked up, the camera comprising: a solid state image sensing device for picking up a picture and producing electrical video signals; an analog-to-digital converter for converting said picked-up video signals to digital video signals; a digital filter for filtering said digital video signals; a digital colour modulator or encoder modulating a sub-carrier signal in the respective carrier phases with primary colour components individually produced from said digital filter; a digital-to-analog converter for converting the outputs of said digital colour modulator to analog video signals; and a digital-to-digitai converter located between said digital filter and said digital colour modulator for converting the outputs of said digital filter with a sampling drive rate of n p . fsc to the digital video m signals with another sampling drive rate of p. fsc where sc is a colour sub-carrier frequency, p is 3 or 4, and m and n are small integers, in which said analog-to-digital converter and said digital filter are n driven at a sampling rate of m. P . fsc while said digital-to-digital converter, said digital modulator and said digital-to-analog converter are driven at a sampling rate of p. fsc.

2. Acamera according to claim 1, wherein said digital filter is a two-dimensional spatial filter acting as a vertical interpolator for the line alternating signal.

3. A camera according to claim 1 wherein said primary colour components are rate-converted to 4fisc by said digital-to-digital converter while m and n are 3 and 1, respectively, and p is 4.

4. A camera according to claim 1 wherein said digital modula.or is a quadrature-phase balanced modulator for alternately multiplexing in-phase components and quadrature components every one quarter of the sub-carrier period at the clockfrequency 2fisc and by alternately inverting the sign thereof every one half of the sub-carrier period at the clock frequency fj.

5. A camera according to claim 1 furthercomprising a gamma-correction circuit using a read-only memory operated atthe sample drive rate of n p m

6. A camera according to claim 1 wherein said image sensing device comprises two sensing images, one for picking-up red and blue colour sign als and the other for picking-up a green colour signal.

7. A solid state digital television camera substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.

8. A solid state digital television camera substantially as hereinbefore described with reference to Figures 2,3 and 5 to 8 of the accompanying drawings.