GB2066627A - P.C.M. frame aligner with frame slip characteristic - Google Patents

Abstract

The propagation delays in aligners for digital switching systems are becoming a matter of growing concern as increased switch transmission delay is contemplated in the future digital switching system designs employing more than two stages of time switch. A current design involves a 21 DIVIDED 2 frame delay which will be unacceptable in the new design. This proposal involves updating the one frame aligner of the type disclosed in B.P. 1,498,498 so that the read/write counters of the aligner remain separated regardless of the state of synchronisation of the line served by the aligner. The circuit details ensure that either there is no slip between the frames or there is one complete frame slip which is either a frame repeated or a frame lost. In this present proposal when comparator logic detects that the count of the write counter is catching that of the read counter, the read counter is advanced by x-bits, a shift register is inserted in the data path to the time switch and double read is effected on the buffer store of the aligner for x-bits.

Description

SPECIFICATION Frame aligners for time division multiplex communication systems The present invention relates to frame aligners for use in time division multiplex (t.d.m.) communication systems.

An aligner is employed to retime data from a pulse code modulation (PCM) system to the frame synchronous clock of a time switch. It-must also take into account both the long term and short term variation of the line frequency and the clock stability. In doing this the aligner must meet the so-called slip rate criteria.

A one frame aligner is disclosed in British Specification 1,498,498 and consists of a 256 bit random access memory, (RAM) and an additional delay means in the form of a shift register that can be switch in and out of the data path to the time switch as required.

The 256 bit random access memory (RAM) is written to continuously using the recovered line (input data path) clock to strobe the data from that line. The data is read from the aligner using the local (read) clock. The shift register is included to cater for the long and short term clock variation and is switched in and out as required, depending on the re'ationship between the relative address location of the read and write clocks.

On set up or re-establishment of alignment following synchronisation loss, it is important to have as great a difference between read and write clocks as possible, however, with a basic one frame aligner, even with a delay that can be switched in and out, this is not always possible. However, should a frame slip occur due to the long and short term clock variation, then further slips are guaranteed not to occur unless loss of synchronisation occurs.

In the event of loss of synchronisation, the write and read clocks are not locked to the same frequency such that under certain conditions the clocks will become coincident, which is a situation that must not be allowed to occur. It is necessary, therefore, to separate the clocks by moving the count of the aligner read counter with respect to that of the aligner write counter. This is done without affecting the write counter in the time switch by inserting or removing the shift registers. In doing this however a frame slip may be introduced. This involves either the repetition or loss of a frame.

As digital switching system designs are advancing, more stages of time switches are being employed which involves greater data transmission delays and accordingly the propagation delays incurred in the frame aligner are of greater importance than hitherto.

An aim of this invention is to reduce the transmission delay through the aligner while maintaining a frame slip characteristic such that when slip occurs, one complete frame is either repeated or lost.

According to the present invention, there is provided a frame aligner for use in a time division multiplex communication system of the synchronous network type, the frame aligner comprising a multi-address buffer store having one address for each bit of a time division multiplex frame of a data bit stream on a time division multiplex input data path, addressing means for addressing the buffer store including read counter means and write counter means, comparator means for detecting when the count of the read and write counter means are within predetermined boundary conditions with respect to each other, delay means of x-bits in length which can be switched into or out of a time division multiplex output path, in which when the delay means is switched into the output data path and when the count of the write counter is catching that of the read counter, the read counter is advanced by xbits, and a double read function is performed on the buffer store for x-bits.

The invention will be better understood from the following description of ar. exemplary embodiment which should be read in conjunction with the accompanying drawings in which: Fig. 1 to Fig. 7 illustrates timing diagrams with respect to the relationship between the read and write counters and the information to be written to the time switch; Fig. 8 is a block diagram of the flow chart of the clash detection logic in relation to the present invention; and, Fig. 9 illustrates a block diagram of the random access memory including the double read arrangements.

There are four conditions which occur in the one frame aligner that require examination in order to define its slip characteristics. These conditions depend on a) whether the delay can be inserted or removed, b) whether the read clock is to be advanced or retarded, and c) the relative frequencies of the read and write clocks.

Referring now to the drawing these conditions are considered in turn.

ADVANCE, INSERT, WRITE CATCHING READ Referring to Fig. 1 and Fig. 2, this situation is most easily represented by showing the conditions just before and just after the advance is done.

Looking at the information written to the time switch (Fig. 2), there is a problem in that the information already stored in the shift register SHR repeats the previous x bits from [(256-x) - writing them into the wrong locations (1vex).

The ideal solution to this is that the correct data from 1 vex is read out of the random access memory RAM until the data has worked its way through the shift register SHR. This however requires two reads from the random access memory RAM.

Alternatively data out of the shift register SHR can be inhibited until the data x is available at the output. In this case two consecutive slips are done on bits 1vex. Initially the read clock jumps by x bits and thus bits 1 -x are not available at either the output of the shift register or the random access memory RAM, and to avoid writing in data associated with other channels, writing to the time switch is inhibited for x bits. Thus, bits ( 1 EX)N (where the suffix N refers to the frame number) are not overwritten by the bits (1ex)N+, in the time switch, and are thus used in two consecutive frames, (frame N and N+1), however, the next read of those bits takes the bits (1 < X)N+2.Therefore, a part frame repeat and a part frame loss has occurred in consecutive frames, which is not totally acceptable. Accordingly the two or double read solution is favoured to meet this problem.

ADVANCE, INSERT, READ CATCHING WRITE Referring now to Fig. 3, advancing the read counter leads it to overtake the write counter which gives it an effective retardation of 256-x bits. If the data out of the shift register SHR is inhibited during the time the first x bits would normally be output and the existing information in the time switch is not overwritten, then a total of one frame will be repeated. This frame consists of the x bits that are already in the time switch plus the 256-x bits that are rewritten from the random access memory RAM.

In this case the requirement to perform two reads from the random access memory RAM during the period 1 -x does not exist.

RETARD, REMOVE, WRITE CATCHING READ Referring now to Fig. 4, retarding the read counter causes the write counter to overtake the read counter. This gives an effective advance in the read counter of 256 - x bits, thus these bits will not be output as they are overwritten. In addition, the x bits in the shift register SHR are not written as the output is now taken directly from the random access memory RAM, and this output is the new (256-x) bit. Thus in total one frame is omitted and a one frame slip occurs.

RETARD, REMOVE, READ CATCHING WRITE Referring now to Fig. 5 retarding the read counter causes the output of the random access memory RAM to change to what was the output of the shift register SHR, thus the shift register SHR can be switched out with no effect on the information passed to the time switch.

The four conditions are summarised in table 1.

TABLE 1

ADVANCE INSERT WRITE CATCHING READ No slip * ADVANCE INSERT READ CATCHING WRITE Slip-Frame Repeated RETARD REMOVE WRITE CATCHING READ Slip-Frame lost RETARD REMOVE READ CATCHING WRITE No slip * Special read facility is required in the RAM From the table the slip rate can be determined, in a non synchronous situation as follows: (a) WRITE CATCHING READ Referring to Fig. 6a and 6b, the total slip on the PCM system is determined by summing the effect on the aligner of the two actions, advance insert and retard remove. These two actions as shown in table 1, cause a one frame slip (loss).The total effect on the counters for a frame slip to occur is for the write counter to catch the read counter by x bits (Fig. 6a), and 256 - x bits (Fig. 6b), to give a total of 256 bits (1 frame). Therefore the slip rate, the time between slips, is given by the reciprocal of the difference in clock frequencies multiplied by 256 seconds.

(b) READ CATCHING WRITE Referring to Fig. 7a and Fig. 7b, the slip on the PCM system is determined by summing the effect on the aligner of the two actions, advance insert, and retard move. These actions, as shown in table 1, cause a one frame slip (repeated). The total effect on the counters for a frame slip to occur is for the read counter to catch the write counter again in two stages, totalling one frame. Fig. 7a, 256 - x bits, Fig. 7b, x bits. The slip rate is again given by the reciprocal of the difference in clock frequencies multiplied by 256, seconds.

Referring now to Fig. 8, this shows how the read counter binary 00000000 condition is compared with the count of the write counter in a block < 6; 6 > to < 250 and, > 250. These conditions serve as the boundary conditions which are to be detected at switch-on or following the regaining of synchronisation.Three courses of action are shown: a) 6 > to < 250 no action other than continuation of read/write function to the random access memory RAM; b) < 6 and when the count of the read counter is catching that of the write counter; with the shift register in the data path to the time switch, the read counter is retarded by x bits and the shift register is removed from the path; when the shift register is not in the data path to the time switch to the time switch the read counter is advanced and the shift register is inserted into the path and; c) > 250 and when the count of the write counter is catching that of the read counter; with the shift register in the data pach to the time switch, the read counter is retarded by x bits and the shift register is removed from the data path with the shift register not in the data path, the count of the read counter is advanced by x bits and the shift register is inserted into the data path, whereupon a double read function is performed on the random access memory for x bits.

The value of x is chosen to be 64, which simplifies the implementation and also provides the required long and short term clock variation in the proposed synchronised system.

Referring now to Fig. 9, there is shown in block schematic form the random access memory, data select and control logic arrangement, concerning this invention, for providing the required data, OPDP, at the time switch interface, to meet the required complete frame slip algorithm.

The choice of three data sources is required for output data OPDP to the time switch. These include data directly from the RAM, data from the shift register SHR and the double read data from the RAM. These are shown as the three inputs to MUX3 namely (RA)DATA, (SHR)DATA and (RA+64)DATA.

The choice of data to be output from the aligner to the time switch is under the control of the select signal, DSC. This signal is generated by the clash detection logic as detailed in block diagram flow chart form illustrated in Fig. 8, and shown as the control clock, clash detection CD in Fig. 9.

The random access memory is fabricated from four 64 bit quadrants RAM 1, RAM2, RAM3, RAM4.

Data, IPDP is written cyclicly to the RAM's at the recovered line clock frequency, and data is read from the RAM's at the local clock frequency. Under normal operation the reads and writes are interleaved on a one to one basis but when the clock frequencies are moving with respect to one another, which can be caused by loss of synchronisation, or be due to drift within the synchronous network, two consecutive reads or writes may be required.

The read counter, RC, provides an 8 bit address to select one location within the RAM, however, in order to perform the double read function it is necessary to convert this address to two addresses 64 bits apart, hence RC and RC+64. This is done by splitting the 8-bit RC address into two parts, SRQ, the two most significant bits, and ADD, the six least significant bits.

SRQ goes to the select logic, SL, where two adjacent quadrants of the RAM are selected. These two quadrants contain the data addressed by RC and RC+64. The RAM's are selected by way of paths, CSi , CS2, CS3 and CS4. The select logic also provides the decode signals SEL A and SEL B for the multiplexers MUX1 and MUX2 to select the addressed RAM outputs D01, D02, D03 and D04 for (RA) DATA and (RA+64)DATA.

The (RA) DATA is also clocked into the shift register SHR using a clock devised from the aligner local (read) clock. The data is strobed from the shift register SHR using the aligner local (read) clock. The four random access memory quadrants have the common six bit address, ADD as the read address, to select the output data.

It will be evident to those skilled in the art that the random access memory can be divided into any even plurality of segments, the addressing arrangements being amended accordingly as necessary.

Claims (9)

1. A frame aligner for use in a time division multiplex communication system of the synchronous network type, the frame aligner comprising a multi-address buffer store having one address for each bit of the time division multiplex frame of a data bit-stream on 8 time division multiplex input data path, addressing means for addressing the buffer store including read counter means and write counter means, comparator means for detecting when the count of the read and write counter means are within predetermined boundary conditions with respect to each other, delay means of x-bits in length which can be switched into or out of a time division multiplex output path, in which when the delay means is switched into the output data path and when the count of the write counter is catching that of the read counter, the read counter is advanced by x-bits and a double read function is performed on the buffer store for x-bits.

2. A frame aligner as claimed 110 claim 1, in which the buffer store comprises a random access memory having an even plurality of separate segments of x-bits each, wherein data is written into the memory cyclically at recovered clock frequency and data is read from the memory at local clock frequency.

3. A frame aligner as claimed in claim 2, in which the read counter provides addresses to select locations containing data in the random access memory.

4. A frame aligner as claimed in claim 3, in which the memory has four separate quadrants and each address comprises two parts, a first part comprising a plurality of bits for selecting two separate adjacent quadrants of the random access memory, the plurality of bits being applied to the addressing means, and a second part comprising a further plurality of bits for selecting data located within the said adjacent quadrants the further plurality of bits being applied directly to the adjacent quadrants.

5. A frame aligner as claimed in claim 4, in which the address means provides first and second decode signals for controlling first and second multiplexors respectively enabling either the addressing data of one or other of the selected quadrants to be switched respectively from the random access memory.

6. A frame aligner as claimed in claim 5, in which the comparison means comprises clash detection logic which detects the predetermined boundary conditions of the read and write counters.

7. A frame aligner as claimed in claim 6, in which when the predetermined boundary conditions of the read and write counters are detected a select signal is generated to select the aligner data output.

8. A frame aligner as claimed in claim 7, in which when the predetermined boundary condition showing that the count of the write counter is catching that of the read counter and when the delay means is switched into the output data path, the select signal controls a third multiplexor enabling data from the delay to be switched through the third multiplexor to be output to the output data path.

9. A frame aligner substantially as described herein with reference to, and as shown, in the accompanying drawings.