GB2062963A - Semiconductor chip mountings - Google Patents

Semiconductor chip mountings Download PDF

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Publication number
GB2062963A
GB2062963A GB8035586A GB8035586A GB2062963A GB 2062963 A GB2062963 A GB 2062963A GB 8035586 A GB8035586 A GB 8035586A GB 8035586 A GB8035586 A GB 8035586A GB 2062963 A GB2062963 A GB 2062963A
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United Kingdom
Prior art keywords
semiconductor chip
solder
circuit board
electrode
layer
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Granted
Application number
GB8035586A
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GB2062963B (en
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Hitachi Ltd
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Hitachi Ltd
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Publication of GB2062963B publication Critical patent/GB2062963B/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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Abstract

A semiconductor chip with its electrodes 22 connected to corresponding electrodes 25 on a circuit board 24 by solder columns 23 is supported by solder spacers 33 formed on isolated metallised pads 34 on the circuit board, the spacers not wetting the chip. The arrangement is produced by forming solder bumps on the electrodes of the chip and circuit board and applying to the isolated pads layers of a solder of higher melting point and of a thickness less than the combined heights of the solder bumps. The chip is positioned on the circuit board with the solder bumps in contact and the temperature raised. The solder bumps melt and merge to form the columns 23 and the spacers then melt, surface tension causing the chip to be lifted so that the solder columns 23 are drawn into a cylindrical or hour-glass shape. Since the spacers do not wet the surface of the chip no lateral or rotational forces which might displace the chip are generated. <IMAGE>

Description

SPECIFICATION Semiconductor chip mounted structure and method of making the same The present invention relates to a semiconductor chip mounted structure in which a semiconductor chip including therein semiconductor devices is mounted on and bonded to a circuit board having an insulating substrate.
There has been hitherto used a semiconductor chip mounted structure in which a semiconductor chip and electrodes on a circuit board are soldered through the face down bonding method, without using any lead wire therebetween, to mount the semiconductor chip on the board. A plan view and a sectional view of such a structure are as shown in Figures 1 and 2 of the accompanying drawings, respectively. The sectional view of Figure 2 is taken along line Il-Il in Figure 1. Referring to Figures 1 and 2, a semiconductor chip 1 is provided thereon with electrodes 2, and a circuit board 4 is provided thereon with electrodes 5 at positions substantially corresponding to those of the electrodes 2. The semiconductor chip 1 and the circuit board 4 are so positioned by known positioning means that each of the electrodes 2 is opposed to the corresponding one of the electrodes 5.Then, the chip 1 is connected and bonded to the circuit board 4 at some joining points, which are simultaneously soldered in such a manner as forming solder columns 3 by appropriate heating means such as a heating furnace, a solder ing bath or the like.
The above-mentioned chip mounted structure has an advantage that the time necessary for the bonding operation is not changed, even through the number of joining points were larger. In this structure, however, the semiconductor chip is bonded to the circuit board by means of solder, which is considerably deformable, without other intervening members. Accordingly, each of the joining points suffers from a thermal steess which is caused by generation of heat in the semiconductor chip, changes in the ambient temperature, and others, the strength of the thermal stress depending upon a difference in the thermal expansion coefficient between the semiconductor chip and the circuit board.
Thus, the solder is disadvantageously fatigued and is apt to be separated from the electrodes on the circuit board. For the above reason, the environment in which the structure is employed, and the size of the semiconductor chip are restricted. This advantage stems from the fact that the each of the solder columns 3 has a form of a spherical segment because the semiconductor chip is joined with the circuit board by the use of the natural melting and solidification of the solder forming the columns 3, and that each solder column therefore suffers from a concentrated stress at the interface between the solder column and the corresponding one of the electrodes on the circuit board when applied with an external stress.Further, in many cases, the interface between the solder column and the electrode becomes fragile due to reaction and/or diffusion which may take place between atoms forming the solder column and atoms forming the electrode. There has been known a structure which can solve the abovementioned problem, and in which each of the solder columns 3 has a form of a circular cylinder or a sand-glass to distribute the external stress uniformly along the solder column and to make full use of the deformability of the solder column. (See, for example, U.S. Patent3811186 issued on May21, 1974.) In the above-mentioned structure, as shown in Figures 3a and 3b, there are provided between a semiconductor chip 1 and a circuit board 4 spacers 9 which are made of solder and used only for the mechanical connection between the chip 1 and the board 4, that is, used only to ensure the spacing between the chip 1 and the board 4. Further, electrodes 2 on the semiconductor chip 1 are connected to electrodes 5 on the circuit board 4 by solder columns 3, each of which has a form of a circular cylinder or a sandglass, depending upon the amount of solder for forming the each column 3.
Further, there has been known such a structure as shown in Figures 4a and 4b, in which a dielectric plate 11 for supporting solder spacers 12 is provided on a circuit board 4, and each of solder columns 3 for electrically connecting electrodes 2 on a semiconductor chip 1 to electrodes 5 on the circuit board 4 is controlled by the spacers 12 so as to have a form of a circular cylinder or a sandglass.
The inventors have found out that in these structures as shown in Figures 3a and 4a, when the semiconductor chip 1 and the circuit board 4 are positioned so that each of the electrodes 2 is opposed to the corresponding one of the electrodes 5, small solder mounds 8 on the semiconductor chip 1 make contact with small solder mounds 10 on the circuit board 4 or the dielectric plate 11 with small solder mounds 6 on the semiconductor chip 1 being spaced apart from small solder mounds 7 on the circuit board 4. This is because of the different amounts of solder for the small mounds 6, 7 and 8, 10 such that the connecting or bonding solder columns 3 finally take a form of a circular cylinder or a sandglass. The small mounds 6 are brought in contact with the small mounds 7 after the small mounds 8 and 10 have melted and reflowed so as to form spacers 9 or 12.Accordingly, the form of the bonding solder column 3 is variable depending upon the manner in which the small mounds 8 and 10 melt and solidify as well as upon variations in the height of the mounds 8 and 10. In the worst case, the solder solumn 3 is subjected to torsion, and false connection takes place. That is, in the two structures shown in Figures 3a, 3b, 4a and 4b, it is very difficult to obtain the solder columns 3 having an optimum form. Further, in the structure shown in Figures 4a and 4b, it is required to form the dielectric plate 11 with a high accuracy.
An object of the prevent invention is to provide a semiconductor chip mounted structure, in which the form of a solder column for connecting or bonding a semiconductor chip to a circuit board can be readily controlled free from the drawbacks of the conventional structures.
Another object of the present invention is to provide a semiconductor chip mounted structure, in which a semiconductor chip and a circuit board are soldered at all joining points with higher reliability free from the drawbacks of the conventional structures.
Afurther object of the present invention is to provide a method of making a semiconductor chip mounted structure, in which a semiconductor chip and a circuit board are soldered at all joining points with a high work efficiency free from the drawbacks of the conventional methods.
According to the present invention which attains these and other objects, there are provided a semiconductor chip mounted structure and a method of making such a structure: in which isolated metallized pads are provided on a circuit board along with solder thereon assuming the state of a sheet or paste; and in which by heating the structure the semiconductor chip and the circuit board are first soldered at electrode portions to be connected or bonded and then the solder on the isolated metallized pads melts, so that the molten solder on the isolated pads pushes up the semiconductor chip on the basis of the surface tension of the molten solder without wetting the semiconductor chip, whereby the molten solder at each connecting electrode portion has a form of a circular cylinder or a sandglass, and then both the molten solder on the isolated pads and the molten solder at the connecting electrode portions are set or solidified.
In more detail, in the above-mentioned structure, since solder pillars finally formed on the circuit board do not wet the semiconductor chip, the semiconductor chip is pushed up by the pillars without being moved in a horizontal direction and without being rotated in a horizontal plane, and therefore the connecting or bonding solder for electrically connecting the semiconductor chip and the circuit board is not subjected to torsion but has a controlled form of a circular cylinder or a sandglass.
Further, since the thickness of solder supplied in the state of a sheet or paste and placed on the isolated metallized pads is small as compared with the spacing between the semiconductor chip and the circuit board when the semiconductor chip and the circuit board are positioned so that the semiconductor chip is kept in contact with the board through the solder at the connecting electrode portions, satisfactory soldering can be ensured at the connecting electrode portions when heating temperature is raised. Furthermore, the form and the height of the solder at the connecting electrode portions can be readily controlled by changing the ratio of the volume of the solder placed on the isolated metallized pad to the area of the isolated pad.
In the accompanying drawings: Figure 1 is a plan view showing connecting portions of a semiconductor chip mounted structure through the conventional face down bonding method; Figure 2 is a sectional view of the connecting portions, taken along the line Il-Il in Figure 1; Figure 3a is a sectional view showing connecting portions of a semiconductor chip structure, in which solder spacers are provided between a circuit board and a semiconductor chip, and the positioning has been effected between the board and the semiconductor chip for connection through the conventional face down bonding method; Figure 36 is a sectional view of the structure of Figure 3a as finally bonded, in which the semiconductor chip has been connected and bonded to the circuit board;; Figure 4a is a sectional view showing connecting portions of a semiconductor chip mounted structure, in which solder spacers are provided on a dielectric plate and the positioning has been effected between a semiconductor chip and a circuit board for connection through the conventional face down bonding method; Figure 4b is a sectional view of the structure shown of Figure 4a as finally bonded, in which the semiconductor chip has been connected and bonded to the circuit board; Figure 5 is a plan view showing connecting portions of a semiconductor chip mounted structure in accordance with the present invention; Figure 6 is a sectional view of the connecting portions, taken along the line VI-VI in Figure 5; and Figures 7a, 7b and 7c are sectional views for explaining various steps of a process for bonding a semiconductor chip to a circuit board in accordance with the present invention.
Now, explanation will be made on an embodiment of the present invention with reference to the accompanying drawings.
In Figure 5 showing in plan view connecting portions of a semiconductor chip mounted structure in accordance with the present invention, solder columns 23 for electrically connecting or bonding a semiconductor chip 21 and a circuit board 24 are arranged at many positions on a peripheral part of the semiconductor chip 21, and solder spacers 33 are placed on the circuit board 24 at positions corresponding to a central part of the semiconductor chip 21. Figure 6 is a sectional view of the connecting portions, taken along the line Vl-Vl in Figure 5.
Referring to Figure 6, the semiconductor chip 21 is electrically connected to the circuit board 24 by the bonding solder columns 23 in such a manner that the height and the form of the bonding solder columns 23 are controlled by the solder spacers 33 provided on isolated metallized pads 34 formed on the circuit board 24.
Next, a process of making the structure shown in Figures 5 and 6 will be explained with reference to Figure 7a, 7b and 7c. First, solder is deposited on electrodes 22, which have been provided on a semiconductor chip 21 such as an intengrated circuit, at predetermined positions through evaporation techniques or the like. The solder thus deposited is melted and then solidified by appropriate heating means to form small solder mounds 26 having a diameter of about 150 um and a height of about 80 to 120 ym. In this case, a solder containing lead as the main component and 5to 10 weight % of tin is employed. However, another solder having a lower melting point may be employed.
On the other hand, conductive paste (for example, a conductive Ag-Pd paste) is printed on a circuit board 24 at positions corresponding to those of the electrodes 2 and at other positions on the semiconductor chip 21, and then fired to form electrodes 25 corresponding to the electrodes 22 and to form isolated metallized pads 34. Next, solder is supplied onto the pads 25 by printing solder paste on the pads 25. The solder is then melted and solidified to form on each of the pads 25 a small solder mound 27 having a diameter of about 150 to 200 cm and a height of about 30 to 50cm. The solder for the mounds 27 may be one having the same composition as that used to form the small mounds 26.
Further, solder 35 which may be a sheet about 80 to l50umthickora printed film of paste having a thickness of about 80 to 150 um, is placed on each of the isolated pads 34, and temporarily fixed to each isolated pad 34 by a flux applied thereto. The material for the solder 35 is so selected as to be higher in melting point than the solder for the small mounds 6 and 7 by about 5 to 60C. Then, the positioning is effected between the semiconductor chip 21 and the circuit board 24, which have been subjected to the above-mentioned treatment, using appropriate positioning means, and the semiconductor chip 21 is temporarily fixed to the board 24 by a flux applied to the small solder mounds 27. Thus, there is formed such a structure as shown in Figure 7a.Next, the structure shown in Figure 7a is heated to a temperature which is higher than the melting point of the solder 35 by about 20 C or more, by appropriate heating means such as a heating furnace or a soldering bath. When the temperature of the structure shown in Figure 7a is raised, the small solder mounds 26 and 27 first melt, and form bonding solder columns 43 for connecting the semiconductor chip 21 and the board 24, as shown in Figure 7b. That is, the chip 21 is connected or bonded to the board 24 by the bonding columns 43 made of molten solder. Then, the solder 35 melts, and forms on the isolated pads 34 solder spacers 33 each made of molten solder and having the form of a pillar.The semiconductor chip 21 is pushed up by the solder spacers 33 without being moved in a horizontal direction and without being rotated in a horizontal plane, because the solder spacers 33 don't wet the semiconductor chip 21. Thus, each of the solder columns 43 is elongated so as to have a form of a circular cylinder or a sandglass 23, as shown in Figure 7c. The structure shown in Figure 7c is then cooled to room temperature, and thus the semiconductor chip 21 is bonded to the circuit board 24. That is, electrical and bonding between the chip 21 and the board 24 is completed.
Further, the moment of the gravity applied to the center of gravity of the semiconductor chip 21 with respect to the geometrical center of the semiconductor chip 21 depends upon the weight distribution of wiring conductors provided on the semiconductor chip 21, the weight distribution of the bonding solder columns 23, and the weight distribution of the semi-conductor chip 21 itself. In order for the surface tension of the molten solder 33 formed on the isolated pads 34 to withstand the abovementioned moment of the gravity, and to space the semiconductor chip 21 part from the circuit board 24 by a predetermined distance, the isolated pads 34 are to be arranged at the outside of the electrodes 25, if possible, though such an arrangement is not shown in the accompanying drawings.
As has been explained hereinbefore, according to the present invention, solder spacers only for pushing up a semiconductor chip are formed on isolated metallized pads provided on a circuit board, and each of solder columns for connecting or bonding the semiconductor chip and the circuit board is elongated by the surface tension of the solder spacers so as to have the form of a circular cylinder or a sandglass. That is, the solder columns having a desired shape can be readily formed, and moreover the stress applied to each solder column is distributed uniformly along the axis of the solder column. Thus, the semiconductor chip is connected or bonded to the circuit board with high reliability.
Further, the solder spacers serve as lead for radiating heat generated in the semiconductor chip, thereby further increasing the reliability of the structure. The semiconductor chip mounted structure in accordance with the present invention has such various advantages as mentioned above, and therefore can make a great contribution to a technical field including hybrid integrated circuits which will be employed more widely.

Claims (9)

1. A semiconductor chip mounted structure comprising: (a) a semiconductor chip having on a surface thereof at least one electrode for external connection; (b) a circuit board having on a surface thereof at least one electrode for external connection and at least one isolated metallized pad, said electrode for external connection being provided at a position opposite to said electrode for external connection provided on said semiconductor chip, said isolated pad being provided at a position shifted from said electrode for external connection provided on said semiconductor chip;; (c) at least one bonding column made of solder and having a form of a circular cylinder or a sandglass, said bonding column being provided between said electrode for external connection provided on said semiconductor chip and said electrode for external connection provided on said circuit board, said electrode for external connection provided on said semiconductor chip being opposed to said electrode for external connection provided on said circuit board; and (d) at least one spacer made of solder and provided on said isolated pad, said spacer keeping said semiconductor chip spaced apart from said circuit board without wetting said semiconductor chip, said spacer being higher in melting point than said connecting column, said spacer having the form of a pillar.
2. A structure according to Claim 1, wherein a plurality of isolated pads are provided and a plurality of bonding columns are provided, and wherein said isolated pads are arranged outside of said bonding columns.
3. A method of making a semiconductor chip mounted structure comprising the steps of: (a) forming small mounds of a predetermined amount of solder on a semiconductor chip provided with a connecting electrode and on a circuit board provided with a connecting electrode, said connecting electrodes being to be connected to each other; (b) placing on an isolated metallized pad a layer of a predetermined amount of solder, said isolated pad being provided on said circuit board at a position shifted from the position of said connecting electrode, said solder for forming said layer being higher in melting point than said solder for forming said small mounds, said layer having a thickness smaller than the sum of respective height of said small mounds;; (c) effecting poisitioning between said semiconductor chip and said circuit board, and heating said semiconductor chip and said circuit board to a predetermined temperature, said semiconductor chip being provided with said connecting electrode and said small mound, said circuit board being provided with said connecting electrode, said small mound, said isolated electrode and said layer, said predetermined temperature being higher than the melting point of said solder for forming said layer; and (d) cooling said semiconductor chip and said circuit board to another predetermined temperature lower than the melting point of said solder for forming said small mounds.
4. A method according to Claim 3, wherein said layer has a predetermined size, wherein said small mound made on said semiconductor chip is formed on said connecting electrode provided on said semiconductor chip, wherein said small mound made on said circuit board is formed on said connecting electrode provided on said circuit board, wherein said connecting electrodes are arranged so as to face other, and wherein said solder for forming said layer is higher in melting point than said solder for forming said small mound on said connecting electrode provided on said circuit board.
5. A method according to Claim 3, wherein when layer is heated to said predetermined temperature, said solder for forming said layer melts and the molten solder has the form of a pillar.
6. A method according to Claim 3, wherein said small mounds form a column having the form of a sandglass when heated to said predetermined temperature.
7. A method according to Claim 3, wherein when said layer is heated to said predetermined temperature, said solder for forming said layer melts and the molten solder pushes up said semiconductor chip to a predetermined height.
8. A semi-conductor chip mounted structure substantially as hereinbefore described with reference to and as shown by Figures 5 and 7 of the accompanying drawings.
9. A method of making a semiconductor chip mounted structure substantially as hereinbefore described with reference to Figures 5 to 7 of the accompanying drawings.
GB8035586A 1979-11-12 1980-11-05 Semiconductor chip mountings Expired GB2062963B (en)

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0078480A2 (en) * 1981-10-28 1983-05-11 Hitachi, Ltd. Method for fusing and connecting solder of IC chip
EP0147576A1 (en) * 1983-11-25 1985-07-10 International Business Machines Corporation Process for forming elongated solder connections between a semiconductor device and a supporting substrate
GB2156153A (en) * 1984-03-21 1985-10-02 Pitney Bowes Inc Alignment process for semiconductor chips
WO1987001509A1 (en) * 1985-09-10 1987-03-12 Plessey Overseas Limited Manufacture of a hybrid electronic or optical device
GB2194387A (en) * 1986-08-20 1988-03-02 Plessey Co Plc Bonding integrated circuit devices
GB2280629A (en) * 1993-08-02 1995-02-08 Motorola Inc Aligning and attaching a surface mount component
EP0899787A2 (en) * 1997-07-25 1999-03-03 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
EP0917190A2 (en) * 1997-11-12 1999-05-19 Robert Bosch Gmbh Circuit support board
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
EP1168429A1 (en) * 2000-06-28 2002-01-02 Telefonaktiebolaget L M Ericsson (Publ) Integrated circuit chip and method for mounting an integrated circuit chip to a circuit board
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
DE102005043910A1 (en) * 2005-09-14 2007-03-15 Weissbach, Ernst-A. Flip-chip module comprises a semiconductor chip having contact columns on a surface, a substrate with contact sites joined to the free ends of the contact columns and a rigid spacer arranged between the substrate and chip
US8026583B2 (en) 2005-09-14 2011-09-27 Htc Beteiligungs Gmbh Flip-chip module and method for the production thereof
US10099318B2 (en) 2012-06-19 2018-10-16 Endress+Hauser Se+Co.Kg Method for connecting a component to a support via soldering and component connectable with a support
US10211135B2 (en) * 2016-06-22 2019-02-19 Jtekt Corporation Semiconductor device
WO2023218301A1 (en) * 2022-05-09 2023-11-16 International Business Machines Corporation Electronic structure and method of manufacturing an electronic structure

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE8122540U1 (en) * 1981-07-31 1983-01-13 Philips Patentverwaltung Gmbh, 2000 Hamburg "INFORMATION CARD WITH INTEGRATED BLOCK"
GB8324839D0 (en) * 1983-09-16 1983-10-19 Lucas Ind Plc Mounting carrier for microelectronic silicon chip
US4763829A (en) * 1986-06-04 1988-08-16 American Telephone And Telegraph Company, At&T Bell Laboratories Soldering of electronic components
AU645283B2 (en) * 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
DE4003070A1 (en) * 1990-02-02 1991-08-08 Telefunken Electronic Gmbh Void-free solder joint of semiconductor die on substrate - by precoating die back surface with solder to form dome surface and attaching die by placing on substrate
DE19738399A1 (en) * 1997-09-03 1999-03-04 Bosch Gmbh Robert Method for connecting electronic components to a carrier substrate
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US6960828B2 (en) 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
US7049216B2 (en) 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
FR2918212B1 (en) * 2007-06-27 2009-09-25 Fr De Detecteurs Infrarouges S METHOD FOR PRODUCING AN ELECTROMAGNETIC RADIATION MATRIX AND METHOD FOR REPLACING AN ELEMENTARY MODULE OF SUCH A DETECTION MATRIX

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871014A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform solder wettable areas on the substrate
US3811186A (en) * 1972-12-11 1974-05-21 Ibm Method of aligning and attaching circuit devices on a substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0078480A3 (en) * 1981-10-28 1984-07-25 Hitachi, Ltd. Method for fusing and connecting solder of ic chip
EP0078480A2 (en) * 1981-10-28 1983-05-11 Hitachi, Ltd. Method for fusing and connecting solder of IC chip
EP0147576A1 (en) * 1983-11-25 1985-07-10 International Business Machines Corporation Process for forming elongated solder connections between a semiconductor device and a supporting substrate
GB2156153A (en) * 1984-03-21 1985-10-02 Pitney Bowes Inc Alignment process for semiconductor chips
WO1987001509A1 (en) * 1985-09-10 1987-03-12 Plessey Overseas Limited Manufacture of a hybrid electronic or optical device
GB2194387A (en) * 1986-08-20 1988-03-02 Plessey Co Plc Bonding integrated circuit devices
GB2280629A (en) * 1993-08-02 1995-02-08 Motorola Inc Aligning and attaching a surface mount component
GB2280629B (en) * 1993-08-02 1996-03-06 Motorola Inc Method and apparatus for aligning and attaching a surface mount component
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6392163B1 (en) 1995-04-04 2002-05-21 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps
US6389691B1 (en) 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
EP0899787A3 (en) * 1997-07-25 2001-05-16 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
EP0899787A2 (en) * 1997-07-25 1999-03-03 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
SG99384A1 (en) * 1997-07-25 2003-10-27 Unitive Int Ltd Controlled-shaped solder reservoirs for increasing the volume of solders bumps, and structures formed thereby
EP0917190A3 (en) * 1997-11-12 2000-06-14 Robert Bosch Gmbh Circuit support board
EP0917190A2 (en) * 1997-11-12 1999-05-19 Robert Bosch Gmbh Circuit support board
EP1168429A1 (en) * 2000-06-28 2002-01-02 Telefonaktiebolaget L M Ericsson (Publ) Integrated circuit chip and method for mounting an integrated circuit chip to a circuit board
DE102005043910A1 (en) * 2005-09-14 2007-03-15 Weissbach, Ernst-A. Flip-chip module comprises a semiconductor chip having contact columns on a surface, a substrate with contact sites joined to the free ends of the contact columns and a rigid spacer arranged between the substrate and chip
US8026583B2 (en) 2005-09-14 2011-09-27 Htc Beteiligungs Gmbh Flip-chip module and method for the production thereof
US10099318B2 (en) 2012-06-19 2018-10-16 Endress+Hauser Se+Co.Kg Method for connecting a component to a support via soldering and component connectable with a support
US10211135B2 (en) * 2016-06-22 2019-02-19 Jtekt Corporation Semiconductor device
WO2023218301A1 (en) * 2022-05-09 2023-11-16 International Business Machines Corporation Electronic structure and method of manufacturing an electronic structure

Also Published As

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JPS5678356U (en) 1981-06-25
DE3042085C2 (en) 1984-09-13
GB2062963B (en) 1984-05-23
DE3042085A1 (en) 1981-06-04

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Effective date: 20001104