GB2059122A - Microprocessor based maintenance system - Google Patents

Abstract

Apparatus for use in automated testing of elements in data processing systems such as the central processing unit comprises a microprocessor 10 with associated firmware, RAM 37 and peripheral communications devices. There are two communication interface ports 25 and 26 for receiving commands and instructions from local and remote computer terminals or from data processing units programmed to cause the testing apparatus to perform predetermined sequences of tests. There is also a port for connection to a portable maintenance panel which can be held in the hand of a field engineer for controlling the testing apparatus. The system is designed to replace prior art maintenance panels used for debugging computer hardware. These prior art panels were slow and cumbersome in that data and addresses had to be switched in using numerous toggle switches and data was displayed using numerous LED indicators. Such maintenance panels were also expensive to build. In contrast, the disclosed testing apparatus is relatively inexpensive and allows the field engineers to rapidly perform many tests, thereby minimizing down time. <IMAGE>

Description

SPECIFICATION Microprocessor based maintenance system The present invention is concerned with maintenance arrangements for computer systems and subsystems.

Most of today's large computer systems need provisions for rapid, low cost trouble shooting of hardware failures in the system. Some have complex arrangements of switches and display apparatus connected with the logic of the unit itself for switching in data, addresses and commands and displays internal conditions in the machine. Typically these maintenance panel arrangements allow a field engineer to read data from and write data to registers and memory locations, to supply addresses, set fault conditions, set flags, control display functions, check the condition of various control points, check the status of the system and, in general, trace functioning of the system through each step of each machine instruction. These maintenance panels sometimes consist of long strings of toggle switches for entering data and addresses, and long strings of LED indicators for display of data.Separate command switches are generally required to select timing margins, select the registers or control points to be displayed and to cause the processor to execute commands set into the data switches or enter a single step mode.

Entering data, commands and addresses via these maintenance panels, and displaying data relating to the performance of the machine using these panels, is time consuming and cumbersome.

Servicing computer systems is now the fastest growing segment of the computer industry, according to a recent article in Business Week. A major reason is the spread of distributed processing which is resulting in computer hardware located everywhere. With computer terminals spread throughout a company, very often the data processing system is the central nervous system of the organization.

Computer users are now very often less concerned with price performance ratios than with service turnaround time.

The object of the present invention is to provide an improved testing system for computers.

Accordingly the invention provides in a digital computer system, testing apparatus for testing the system comprising: a memory storing instructions forming a program which the testing apparatus follows in testing the unit; entry means for entering data, addresses, and commands to select the functions performed by the testing apparatus; display means for displaying data from the unit; and control means which reads instructions from the memory and is responsive to the data, addresses and commands from the entry means to send control signals and data to the unit to cause the unit to perform desired operations, monitors the operations performed thereby in the unit, and passes the results to the display unit for display.

A testing apparatus in accordance with the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 7 is a block diagram of the apparatus; Figure 2 shows the front of the maintenance panel; Figure 3 is a flow chart of the program used by the apparatus; Figure 4 shows some details of the circuitry of the maintenance system; Figure 5 is a block diagram of the interface between the maintenance system and the CPU which is tested; Figure 6 shows some details of the interface of Figure 5; Figure 7 is a block diagram of the maintenance panel coupled to the maintenance system; and Figures 8 and 9 show some details of the maintenance panel of Figure 6.

INTRODUCTORY SUMMARY Automated Maintenance Systems FAMES) The testing apparatus described herein is designed to replace prior art maintenance panels with microprocessor technology to streamline field engineering and reduce the manufacturing cost of data processing units in which the testing apparatus is incorporated. The apparatus is incorporated into the structure of the central processing unit or other unit in the data processing system, and has an external interface for control of the testing apparatus from the external world. The preferred embodiment can be controlled from either a portable maintenance panel held in the hand of a field engineer or from a computer terminal located in the vicinity of the tested unit or from a computer terminal anywhere in the world and coupled to the testing apparatus via a communications network.The testing apparatus can be interfaced with another digital computer programmed to run a predetermined series of tests on the tested unit from a centrally located field engineering office for rapid and accurate pinpointing of defects in the tested unit. The testing apparatus thereby enables the mainframe computer manufacturner to maintain a staff of highly trained maintenance specialists in a central location close to the manufacturing plant with the capability of servicing computer systems all over the world. This enhanced maintenance capability both decreases field engineering costs, so lowering hardware costs to the customers, and provides better maintenance support to those customers.

The disclosed system is capable of being adapted to test any type of unit of any type of data processing system merely by changing the firmware and designing a special interface between the testing apparatus and the unit to be tested.

The testing apparatus causes events in the tested unit and displays data from that tested unit indicating the correctness of the performance thereof by performing a number of input/output operations between the microprocessor in the testing unit and the unit under test.

In more detail,the apparatus is a programmable maintenance and testing apparatus used for performing tests on the central processing unit (CPU) or some other unit of a data processing system. By changing the program and designing a specially adapted interface, any CPU or, for that matter, any unit in a data processing system could be tested using this system. The tests to be performed or the events to be caused in the tested unit are under the control of an operator or another digital computer.

Such a computer would be programmed to cause the testing apparatus to perform a sequence of pre-determined input/output operations to the unit under test for causing the desired events in the tested unit and for receiving data indicative of the performance of the unit under test. The testing apparatus allows individual registers in the CPU and individual memory locations to be read from and written to, and allows an operator to examine control points in the tested unit indicating the correctness of performance of the tested unit. The testing apparatus is also capable of selecting process halt conditions, and setting the configuration of the machine.

In order to accomplish the above functions, the apparatus, in its simplest form, requires only three elements. First, there is required a means for storing the instructions comprising the program which the testing apparatus follows in testing the CPU. In the preferred embodiment, firmware is used for nonvolatile storage of the program. Second, there is needed a means for entering the data, addresses and commands to select the functions to be performed by the testing apparatus and to display data from the unit under test indicating its performance. Finally, there is needed a means for processing the data, addresses and commands coming in from the second means and for performing the sequence of instructions stored in the first means relating to the desired test.This third element must then output the proper data to the unit undertestto cause the desired events in that unit. This third means must also receive data from the unit under test relating to its performance and transfer this data to the second means for display. Such data typically would be the contents of a memory location or internal register, or it could be the conditions of a selected set of control points.

These three elements are coupled together in simple fashion to form the testing apparatus. Typically, the third means is a microprocessor, but it could be any digital computer. The data bus of the microprocessor is coupled to the second means for receiving from it the data, commands and addresses for controlling the system. The microprocessor is also coupled to the first means by the data bus and an address bus so that the commands from the second means can be decoded to form the starting address for a sequence of instructions designed to carry out the command. This address is supplied to the first means, and the instruction stored at that address is returned to the microprocessor via the data bus for execution. The data bus is also coupled to the unit under test, usually through a specially designed interface for that particular unit.Data is sent and received over this link by the microproces sor during execution of the instructions. This data causes the specific tests or operation to be performed by the unit under test. Then, if a Read had been ordered, data relating to the performance of the machine will be transferred back to the microprocessor via the data bus for transfer to the second means for display.

The preferred embodiment is slightly more complicated than the above described simple form.

Although there are more elements in combination, the basic operation described above still holds true.

In the preferred embodiment, a programmable read only memory (PROM) is used to store the instructions to be executed by the microprocessor. The microprocessor is coupled to the PROM via the address bus and a data bus. When the microprocessor enters the fetch cycle, an address is supplied to the PROM via the address bus, and the instruction stored at that address is transferred back to the microprocessor via the data bus.

Three possible ports for receiving information from the terminals are used. Data, commands and address information can be sent to the testing apparatus either from the portable maintenance panel orfrom a computer terminal located in the vicinity of the unit under test orfrom a computer terminal located any distance from the unit under test but coupled to the testing apparatus via a communication network. In the alternative, a compu- ter programmed with a predetermined sequence of tests could replace the computer terminals for sending streams of commands, data and addresses to the testing apparatus.Two USART's (universal synchronous/asynchronous receiver transmitter chips) are used as terminal ports to interface between the data bus of the microprocessor and the serial data line from the local or remote computer terminals. The USART coupled to the remote com puterterminal also monitors the ring line of the telephone system used in the preferred embodiment. The purpose of these USART's is to convert information coming from the computer terminals in serial format to parallel format data for transfer to the microprocessor on the data bus. They also serve to signal the microprocessor via a control signal when a data word has been received.The USART's also convert data being transmitted from the microprocessor to the computer terminals for display from the parallel format of the data bus to the serial format necessary for transmission over the telephone lines. The USART sends a control signal to the microprocessor indicating when a word has been transmitted and that the USART is ready to receive another word.

The third means of controlling the testing apparatus is by means of the portable maintenance panel.

The maintenance panel has a limited keyboard for entering data, command and address information for purposes of controlling the operation to be performed by the testing apparatus. The portable maintenance panel also has a means for displaying the data, command and address information that has been entered and individual LED's for displaying prompting and status signals from the microprocessor. The means for display also displays data received from the unit under test relating to its performance. The maintenance panel is linked to the microprocessor via a bidirectional data bus and the address bus. The address bus controls which display device on the maintenance panel displays that data.

In the preferred embodiment, a random access memory (RAM) is coupled to the microprocessor via the data and address busses to act as a scratch pad memory for temporary storage of information necessary to the operation of the system. In some other embodiments, the microprocessor may have on-chip RAM or a minicomputer with associated RAM might be used.

The preferred embodiment also incorporates a timer utilizing three counters. One counter is used to generate an interval timing signal for use by the microprocessor. The other two counters are used to generate baud rate clock signals for use by the USART's.

The preferred embodiment uses a standard microprocessor having an eight bit data/address bus and an eight bit address bus. The sixteen bit addressing capability is achieved by the use of an address latch coupled to the data/address bus. The address latch outputs the lower half of the address used in an operation, and the eight bit address bus carries the upper half. The sixteen bits of address form the ABUS which is coupled to the RAM and PROM. The sixteen bits of address bus are also coupled to an address decoder which is used to generate select signals for the RAM, PROM, maintenance panel and for CPU I/O operations. These select signals, along with the various control signals sent from the microprocessor to the other elements in the system, and those control signals sent from the other elements in the system to the microprocessor, comprise a control bus.These control signals allow the microprocessor to address each individual element in the system without having more than one element at a time attempting to use the common busses. The control bus also allows the microprocessor to be informed of the occurrence of significant events through the occurrence of interrupt signals indicating the arrival of data, command and address information from the maintenance panel or either of the computer terminals.

Finally, there are provisions for coupling the address, data and control busses of the system to a board tester unit for automatic testing of the testing apparatus itself by another automated test system.

CPU Interface Circuits In brief, the interface circuit couples the general purpose microprocessor based automated maintenance system (AMS) having a single 8-bit output data port to the buses and control paths of a specific central processing unit.

In broad perspective, the interface consists of path control and enabling circuitry which converts signals from the automated maintenance system into control signals which control and enable the pathways in the particular CPU which are accessed by the automated maintenance system.

Operation condition and control circuitry converts information from the AMS into control signals to the CPU which control the operation performed by it and the conditions of performance. This circuitry also receives response signals from the CPU which verify the operational conditions set by the automated maintenance system.

A control point register serves to receive control point information from the CPU indicating the internal status of various control flags known as control points. This circuitry also transfers this information to the AMS upon request.

Address buffer circuitry serves to supply the CPU with address information from the automated maintenance system. The supplied address information is used by the CPU in controlling whatever operation has been requested by the AMS. Such operations include reading the contents of cache locations, reading or writing to main store memory locations, and setting stop-on address conditions.

A data buffer assembles AMS supplied data and transfers it to the CPU for use in controlling various operations or writing new data to internal registers or memory locations. This buffer also receives data from the CPU that is to be displayed by the automated maintenance system for analysis by a test operator and holds the data for transfer to the automated maintenance system in smaller bytes.

Finally, there is a byte size bus coupling the automated maintenance system to all the above described circuits. This bus supplies the data needed by those circuits to perform their operations and collects data received by these circuits from the CPU for transfer to and display by the AMS.

Maintenance Panel The maintenance panel comprises a keyboard means for entering encoded information to be transferred to the automated maintenance system to control the function of that system. A plurality of display means display the address, data and command code information sent to the automated maintenance system to control it, and display data received by the maintenance system from the unit under test. A port means coupled to the keyboard means and the display means interfaces with the automated maintenance system to carry data from the unit under test back to the maintenance panel for display by the display means and carry encoded information to the automated maintenance system to control it.The port means also carries address information to the maintenance panel from the automated maintenance system which indicates to the maintenance panel which of the plurality of display means is to display the data from the unit under test indicating the correctness of its performance.

The use of a hexadecimal encoded keyboard and single button function keys for controlling all operations of the maintenance system eliminates the necessity of manipulating long strings of toggle switches used in prior art maintenance panels for entering data, addresses and commands in binary form. The use of LED matrix display devices also speeds up the maintenance process by allowing the field engineer to read the contents of memory location and registers in octal form as opposed to binary form and likewise for the address and command information.

DETAILED DESCRIPTION Automated Maintenance System rAMS) In Figure 1, microprocessor 10 is coupled to bus driver 11 via data bus 12. An eight bit bidirectional bus 13, designated the SBUS, couples bus driver 11 with a specially designed interface for the tested unit. The output operations performed by microprocessor 10 cause various bit patterns to appear on SBUS 13. These in turn cause selectable events in the tested unit. It is the function of the interface for the tested unit to collect and format this data for writing to the proper bus or test input of the tested unit to cause the desired event. The system is capable of carrying out some 70 different I/O operations, each of which results in the 8 bits of the SBUS 13 having certain distinctive significances.

The capabilities of the system are reflected in the l/O operations. Data or addresses can be written to the unit under test, or any one of a number of stop on fault conditions can be set. Further, any internal register or memory location can be displayed by setting a predetermined bit pattern on the CPU display control bus.

The I/O operations fall into 2 classes, read and write. Read operations result in bits reflecting the state of the CPU appearing on the SBUS; write operations involve the operator entering a desired pattern of bits on the SBUS, and these bits are then entered into the CPU, either setting or controlling portions of the CPU or being treated as data by the CPU.

Two of the write operations (CPU enable control) together involve entering 12 bits (plus 4 unused bits) which can enable any internal unit of the CPU. Two more write operations (CPU flag control) can be used to write bits to the proper input of the tested unit to put any internal unit in the step mode, select timing margins, or set various stop on address conditions.

A CPU flag status read operation enables the testing apparatus to determine what internal internal units are in the step mode and which, if any, stop on address or stop on fault conditions are set. It can also be used to determine if the CPU is in the DIS state.

This state requires an interrupt to restart processing.

CPU flag status read also determines whether display of an internal register is possible by checking the busy status of the address register.

12 CPU display bus read operations allow the testing apparatus to read the data in the internal register or memory location selected by the write operations to the CPU display control bus. The 72 bit display bus in the CPU also carries control point information to the CPU interface where it can be read 8 bits at a time by the microprocessor in the testing apparatus. This information indicates the status of various internal contol points.

Six MP data display write operations show the I/O addresses used by microprocessor 10 in writing data to be displayed on maintenance panel 14. For example, referring to Figures 1 and 2, one MP data display write operation having an I/O address of 00 (hex) would light data display locations 0 and 1 indicated as 15 and 16 in Figure 2. The I/O address of 00 (hex) would indicate that the 8 bits represented by the address 00 (hex) would appear on the 8 lines of address bus 17 in Figure 1. These 8 address bits would direct the 8 data bits on data bus 12 to display locations 15 and 16 in Figure 2.Display location 15 displays in octal the first three bits on data bus 12, and display location 16 displays bits 4 to 6 on data bus 12; although the data bus 12 is 8 bits wide, in fact these displays are only used to display the 8 octal digits 0 to 7, not the 16 hexadecimal characters which the system is capable of displaying. The remaining 5 MP display write operations are used to control the display of the remaining 10 characters of the 12-character data display. A similar situation exists for the four MP address display and two MP command display operations. In these write operations, data including the address and command involved in a particular operation is directed to displays 18 and 19 respectively, in Figure 2.

All these I/O operations, like the commands to be discussed shortly, are carried out by respective programs stored in the PROM 23 (discussed later).

The structure and operation of the interface to the unit under test is unique for each type of unit tested.

That is, the interface to a CPU would be different from that for an SCU. There is a ZMP data bus to and from the CPU which the testing apparatus tests is 36 bits wide, and the MPA address bus to the CPU is 34 bits wide. Also, there are 24 separate stop on fault (FLTSTOP) lines to the CPU, and a 40 bit wide display control bus DCL. There are 16 separate CPU enable control lines to enable various units in the CPU, and there are 36 separate flag lines that the testing apparatus can write to, to set various conditions such as overlap, stop on address, step mode, timing margins and various control signals such as scope repeat, execute switches and initiate commands.

Finally, there is a 72-bit display bus BCP for carrying data from the CPU regarding the contents of internal registers. The 36-bit ZMP bus also carries data to and from memory locations. Since all read and write operations by the testing apparatus must read or write from one of these busses, and since the SBUS is only 8 bits wide, it is the function of the CPU interface to collect an format data passing to and from the testing apparatus such that the testing apparatus can read and write from any of these busses using only the SBUS.

The testing apparatus is much simpler and faster to use than the prior art maintenance panels.

Maintenance panel 14 is only one manner of controlling the testing apparatus since, as noted earlier, the testing apparatus is also supported by two USART's.

Maintenance panel 14, as shown in Figure 2, has a 26-key keyboard for entering data, addresses and commands. There is also a 36-bit octal data display, a 24-bit octal address display and a 12-bit hexadecimal command display. Finally, there are 8 discrete indicator LED's that prompt the operator and provide condition status. The data, address and command displays are 4 x 7 matrix LED displays, while the promptig and status indicators are standard panel LED's. Maintenance panel 14 is connected by a cable to a receptacle mounted on the CPU cabinet which in turn is connected to the logic board within the CPU that holds the microprocessor and associated logic of the testing apparatus. Maintenance panel 14 can be either hand held or mounted on a bracket attached to the CPU cabinet.The testing apparatus logic board, which the maintenance panel controls, recognizes when the maintenance panel is attached to the system. When the firmware recognizes that the maintenance panel has been attached, timer 20 in Figure 1 is selected and starts a time-out period resulting in the signal TMR-INTwhich is coupled via control bus 21 to an interrupt input of microprocessor 10. Receipt of this interrupt signal causes microprocessor 10 to activate maintenance panel 14.

Operation of the maintenance panel requires reference to a list of command codes for the various operations. The keyboard shown in Figure 2 has 16 alphanumeric keys used for entering these command codes. The 9 function or control keys to the right of the alphanumeric keyboard are used to provide control information to microprocessor 10.

Only octal keys 0 to 7 are used when entering data or address information.

The 9 control keys perform the following functions. The "enter" key is depressed after each entry of information such as entry of a command code, data, or an address. The "command" key signals that entry of a command is desired. After the operator depresses the key, a command code is selected from the list is entered using the alphanumeric keys. For example, when the operator wishes to read a particular location in main memory, he depresses the command key. Referring to Figures 2 and 3, it is seen that when microprocessor 10 senses depression of the command key it dispatches a prompting signal to light the "command' LED indicator 36. When the operator sees the command LED light, he keys in the hexadecimal command code. The firmware then inputs this command and decodes it at a first level.Then, depending upon what type of command it is, the firmware directs another prompting signal to the maintenance panel if data or an address or both are necessary to the completion of the command. As the operator keys the command code in, it shifts into command display 19 allowing the operator to verify his entry. Similarly, as the operator keys in any data necessary, it shifts into the data display register, and likewise for any address information. After all data, address and command information is keyed in, and the operator is satisfied with his entries, he depresses the "enter" key and the information is then accepted by the microprocessor.

Among these commands are scroll position commands which replace the prior art data point and control point rotary switches. In the prior art maintenance panel, a rotary switch was used to select the batch of internal registers in the various units within the processor that were to be displayed. Likewise, another rotary switch was used to select one batch of a plurality of batches of control points to be displayed. Now each position of these rotary switches is replaced with a scroll position command.

Certain of the commands also activate selected ones of the 8 prompting/status indicator LED's, described in more detail below.

The set of commands can be divided into three major groups. They are: commands to read and write from memory locations; commands to display the internal registers of any of the internal units of the unit under test such as the control unit, decimal unit, virtual unit, etc; and commands to change the configuration of the unit under test.These configuration commands have command codes beginning with F (hex) and include the following commands: to select the step mode in any of the internal units of the test unit; to display or alter the address on the address bus MPS; to display oralterthe data on the display bus or alter the stop on fault selection; to display or alter the timing margins selection; to display or alter the stop on address selection; to display or alter the cache selection; to display or alter the inhibit overlap selection; to enable the remote terminal; and to clear initialize; control initialize; and execute command or execute faults.

The three main processing streams of the firmware embodied in PROM 23 of Figure 1 are shown in Figure 3. When a read memory command having a command code beginning with A (hex) is received, a second level decode is performed to determine whether the command is one to read the memory location or to "test" the memory location by continually addressing it and reading it. The purpose of this "test" command is to allow continuous reading of a memory location so that if there is some difficulty with reading that location, the field engineer can use an oscilloscope to trace through the logic pathways used in addressing and reading the location to find the problem. Next, the firmware prompts the operator by lighting the "address" LED in Figure 2 whereupon the address is keyed in by the operator. Microprocessor 10 then sends the address to the CPU and does some write operations to the DCL bus.The purpose of these I/O operations is to set up the proper bit pattern on the DCL display control bus to cause the CPU to perform a memory read. The firmware then guides the microprocessor to perform the CPU enable control write operation necessary to set the display enable bit. The next step is a number of read operations from 6 successive hex addresses to receive the data in the selected memory locations from the CPU via the MPD bus.

This data is then displayed on the maintenance panel by doing a number of MP Data Display commands, write operations to 6 successive addresses. These operations direct the 72 bits of data received from the CPU, 36 at a time, to the octal display for data. Each data display location displays 3 of the 36 bits received in octal format. Since only 36 bits can be displayed at one time, when the other half of the data is to be displayed, the operator presses eitherthe "upper" or "lower" command key shown in Figure 2. This causes the firmware to shuttle the remaining 36 bits to the data display on the maintenance panel.

It is also possible to write to any memory location.

The next step in the rightmost branch of firmware processing sequence of Figure 3 is to determine whether a write operation is desired. The firmware assumes that a write is desired unless the operator presses the "terminate" key shown in Figure 2. If "terminate" is pressed, the firmware returns to the input command mode and waits for the next com mand. If not, the firmware lights the "data" LED in Figure 2 whereupon the operator keys in the new data to be written to the selected address location.

When the operator presses "enter", the data in the data display on the maintenance panel is written to the memory location having the address displayed in the address display. This data is written on the 36 bit MPD bus in the CPU under test, using six successive write operations. Upon writing this data to the memory location, the microprocessor returns to the input command mode of the firmware.

If a display register having a command code beginning with a number 0 to 6 is received, the flow of processing proceeds down the middle branch of Figure 3. The first step is to decode the command for the register ID identifying which internal unit of the CPU and which register therein will be involved. The next step is to select the data to be placed on the DCL bus to cause various switching events to occur in the CPU enabling access to the desired register. The final steps are to read the data from the desired register via the 36-bit MPD bus, the 8-bit TBS bus or the 72-bit BCP bus, and then display this data on the data display of the maintenance panel. Following display, the microprocessor returns to the monitor to await receipt of the next command.

Processing flowforthe operation commands is very simple. The first step is a second level decode to determine the type of operation command that has been received. Next the current setting of the operation is displayed on the maintenance panel.

Then, if the operator desires to set a new operation, he inputs a new setting using the maintenance panel keyboard and depresses "enter". At that time, the firmware updates the register setting controlling the operation, and then returns to the monitor to await receipt of the next command. The operation commands select single step mode, set data or addresses for use by the CPU, set stop on fault and timing margin conditions, set stop on address conditions, make cache selections and other such operations.

Figure 2 also shows an "advance" key and a "back-up" key on the maintenance panel keyboard.

Some functions, such as the command to read main memory, allow stepping through memory by use of the "advance" key without keying in a new address each time. For example, the operator, after depressing the command key, could key in a command indicating a read write memory operation is desired.

After keying in the command code, the operator would depress the "enter" key at which time the address indicator would be lit by the firmware. The operator would then key in the address in octal format for the location of interest and this address would be displayed in the address display. When the desired address has been selected and displayed, the "enter" key would be depressed again which causes the firmware to light the data indicator LED.

Simultaneously, the firmware of the testing apparatus causes the unit under test to fetch the data in the selected memory location and transfer it to the microprocessor which in turn transfers it to the data display. The "advance" key may then be used to step through the memory. Each time the "advance" key is depressed, the address display is advanced by one location and the data at the new address is displayed in the data display.

The "back-up" key operates in the reverse fashion.

It is active anytime the "advance" key is active. By this, it is meant that only certain command keys are active for certain commands depending upon the particular command involved. For example, if the command was to read a register the "advance" key would not be active because the firmware is programmed to know that depression of the "advance" or "back-up" key in this context would be meaningless.

The "step" key is active during processor step functions where the step mode has been selected for an internal unit of the CPU. The particular unit which is placed in the step mode is selected by use of a select step command having a command code FOO.

After keying in FOO, the operator would key in data which would indicate which unit is to be placed in the step mode. Thereafter, each depression of the step key would cause the internal unit of the CPU to execute one step. The step function is released by selecting the FOO command code again, resetting the particular step function bit to zero, and depressing the step key.

The "terminate" key will terminate the display functions such as scroll display or control unit display of internal registers or memory. It is used where the operator does not desire to write new data into the location display. The "terminate" key has no effect on functions such as step, stop on address, stop on fault, or timing margin commands.

As indirectly referred to above, the maintenance panel has 8 LED prompting status indicators. The "command", "data", "address" and "complete" indicators prompt the operator while the "step/dis", "upper", and "term enable local" and "remote" indicators provide status information. The complete indicator notifies the operator that no further operator entries are required and that the maintenance panel is displaying the final results of the command code entries. When lit, the DIS/STEP indicator shows whether the CPU is in a Dis or Step state. The upper indicator lights when the most significant 36 bits of a 72-bit display are displayed and, when not lit, indicates the lower 36 bits are being displayed.

Where the entire piece of information to be displayed is 36 bits or less, the upper indicator will be lit.

The remote terminal enable indicatorwill be lit when the remote terminal interface is enabled by a command from the maintenance panel. This command allows communication between the testing apparatus and a remote terminal via USART 25 in Figure 1. Likewise, the local terminal enable indicatorwill be lit when the local USART 26 in Figure 1 is enabled.

Address decoder 27 in Figure 1 is used to convert address information on address bus 22 into one of four select signals used to enable either the PROM, RAM, maintenance panel or the CPU input'output interface for a transaction with microprocessor 10.

Since there is only one set of address and data busses, and since during operations as described above, microprocessor 10 must send and receive address and data information to the PROM, RAM, maintenance panel and CPU input/output interface, some means must be provided to switch onto the bus system only the unit directly involved with the microprocessor 10 during the current operation. This is the function of address decoder 27. Each unit in the system is assigned to a particular address. When this address appears on address bus 22, a select signal will be issued to that particular unit thereby coupling it to the address and data busses. All other units in the system will be in a high impedance state so as to not load down the bus system or interface with the current operation.

The board test port formed by the buffers 28 in Figure 1 merely serves to allow connection of the address, data and control busses of the testing apparatus to an external board testing apparatus so that operation of the testing apparatus may be simulated. In this manner testing of the testing apparatus itself may be accomplished.

The microprocessor 10 is a standard microprocessor having an 8-bit address/data port 12, an 8-bit address port 22 and a control port 21 comprised of numerous control input and output ports and three interrupt ports. The microprocessor contains an on-board clock for which two signal lines connect to an external crystal to set the frequency of this clock.

A RESET-In signal is an input signal which sets the internal program counter to 0 and resets the internal interrupt enable and HLDA flip-flops. When this signal goes low, the data address busses and the control lines are in the high impedance state. The microprocessor is held in the reset condition as long as this signal is held low. It is a Schmitt triggered unit, allowing connection to an RC network for power-on reset delay.

A signal RDY is an input which is high during a read or write cycle, indicating that the memory or peripheral is ready to send data orto receive data from the microprocessor. If this signal is low, the microprocessor will wait for it to go high before completing the read or write cycle.

A signal HOLD is an input which indicates that another master device is requesting the use of the address and data busses. The microprocessor will relinquish control of the busses upon receiving this request as soon as the current machine cycle is completed. Internal processing within microprocessor 10 may continue however. The microprocessor can regain the use of the busses only after the HOLD request is removed. When the HOLD request is acknowledged, address/data, RD, WR, and 10 lines are tri-stated. The HOLD request line is connected to the external board test unit. In this manner, an external board tester unit may have control of the busses.

A control signal HOLDA is an output which indicates that the microprocessor has received the HOLD request and will relinquish the busses during the next clock signal. This signal goes low after the HOLD request is removed whereupon the microp rocessortakes the busses one-half clock cycle later.

A hierarchical interrupt structure having three levels or priority is used. The highest priority interrupt is an RST7.5 input. When this signal goes high, microprocessor 10 is forced to jump to an interrupt routine for servicing maintenance panel 14 of Figure 1. This interrupt service routine functions to receive commands from the maintenance panel, decode them, send prompting signals to the indicators LEDS on the maintenance panel and receive data and addresses keyed in by the operator where necessary to completion of the command.

The second highest priority interrupt, RST6.5, is assigned to communications interface USART's 25 and 26. A signal COMM-INT to this interrupt is generated when either USART is ready to transmit a character or has received a character, providing that, prior to that time, a terminal enable command has been received from maintenance panel 14. This is, communications interrupts are enabled only after the operator keys in a terminal enable command.

The lowest priority interrupt port, RST5.5, receives a signal TMR-INT. This signal is coupled to the output of counter 0 of the programmable interval timer 20. This interrupt signal is used by the microprocessor for delay purposes such as where a display is to be sent to one of the communications terminals and displayed there for some predetermined amount of time, such as 10 s, and then redisplayed so that the operator can tell if anything has changed. If is also used to prevent the microprocessor from waiting indefinitely for a response from the unit test which does not occur due to faulty operation. Counter 0 is initialized by the firmware to count out a delay of 0.33 s, and interrupt the microprocessor at the end of each interval. The system initialize function is performed by a signal MINZ coupled to the reset output of microprocessor 10.This signal indicates that the microprocessor has received a reset input.

An ALE signal (Address Latch Enable) occurs during the first clock state of a machine cycle and latches the address on the data/add ress bus into the address buffer of any peripheral chip in the system.

A signal RD serves as the read control signal for the system. A low level RD signal indicates to the selected memory or I/O device that the data bus is available for data transfer. This signal is tri-stated during HOLD/HALT modes and during reset.

A signal WR serves as the system write control.

When this signal goes low, the data on the data bus is available to be written into the selected memory of I/O location. Data on the data bus is set up at the trailing edge of the WR signal.

A CLK signal is a clock output for use as a system clock. The period of this signal is half that of the crystal coupled to the microprocessor.

A signal I/O serves to inform the system of the microprocessor status. It is low during a memory write or a memory read. It is high during an IIO read or write.

Address/data bus 12 is a multiplexed bus that serves in both an address and data capacity. The lower 8 bits of the memory address or the I/O address appear on the bus during the first clock cycle of T state of a machine cycle. Thereafter, during the second and third clock cycles, this bus becomes the data bus.

Address bus 22 serves to carry the 8 most significant bits of the memory address. It is tri-stated during the HOLD and HALT modes and during reset.

Bus driver 31 is an 8-bit driver for the DBUS, controlled by a signal SEL-DBUS comes from control logic, Figure 4, coupled with the control bus.

Communication between the testing apparatus and a computer terminal or other data processing systems located in the general vicinity of the tested unit is accomplished by the use of programmable USART 26, which is specially designed for data communications in microprocessor systems. It has a parallel format data bus input coupled to address/ data bus 12 and also is coupled to portions of control bus 21 in order to send and receive various control signals to and from microprocessor 10 and various other parts of the system. The USART serves to convert from parallel format to serial format data which is being sent from the testing apparatus to a local computer terminal or local data processing system for display.Similarly data being transmitted to the testing apparatus from a local computer terminal or data processing system is converted from serial to parallel format for transfer to microprocessor 10 to control the testing apparatus. The conversions from serial to parallel and from parallel to serial may occur simultaneously.

USART 26 also signals to microprocessor whenever it can accept a new character for transmission or whenever it has received a character for transmission to the microprocessor. The microprocessor can also read the complete status of the USART at any time. USART26 can operate synchronously or asynchronously in a full duplex mode at selectable information transfer rates.

The USART has double buffered data paths with separate I/O registers for the control word, status word, data in and data out. Microprocessor 10 completely defines the functional definition of the USART by writing to it a set of control words under firmware control. These control words program the baud rate, character length, the number of stop bits, synchronous or asynchronous operation and even/ odd/off parity. In the synchronous mode, options are also provided to select either internal or external character synchronization. The signal MINZ coupled to the reset input of USART 26 will, when high, force the USART into an idle mode. The device will remain idle until a new set of control words is written into the USART by microprocessor 10 to program its functional definition.

The signal CK is used to generate internal device timing and must be greater than 30 times the receiver or transmitter data bit rates.

A low signal RD informs the USART that the microprocessor is reading data or status information from it. A low WR signal indicates that the microp rocessor is writing data or control words to the USART.

A signal ABUS-3 (address bus bit 3), when read by the USART in combination with the signals WR and RD, defines whether the word on the data bus is a data character, control word or status information.

When the signal is high the data bus word is either control or status, and when the signal is low, data.

A signal SEL-USART-L, when low, selects USART 26. No reading or writing can occur until the device is elected. The data bus will float when the signal is high.

Asignal DSR-L couples to a general purpose, 1 bit inverting input port. Its condition can be tested by the microprocessor during a status read operation.

This input is normally used to test modem conditions such as data set ready.

A low signal CTS-L enables the USART to transmit serial data if the TX enable bit and a command bit are set to one. If either TX enable orthe signal CTS-L go off during transmitter operation, the transmitter will transmit all the data in the USART written prior to the TX disable command before shutting down.

A signal TXC-L is the transmitter clock controlling the rate at which characters are to be transmitted. In synchronous operation, the baud rate is equal to the frequency of this signal. However, in asynchronous operation, the baud rate is only a fraction of the frequency of this signal. A portion of the mode instruction written to the USART by microprocessor 10 selects either the baud rate factor of 1,1/16, or 1/64 of the TXC frequency.

Similarly, a receiver clock signal RXC-L controls the rate at which characters are received. In the synchronous mode, the baud rate is equal to the RXC frequency, however, in asynchronous operation, the baud rate is a fraction of the RXC frequency.

Modem control such as "data terminal ready" is accomplished by an output signal DTR-L. This signal can be set low by programming the appropriate bit in the command instruction word.

The "request to send" control function for controlling a modem is performed by a signal RTS-L which is coupled to the RTS output port. This signal can be set low by programming the appropriate bit in the command instruction word.

The microprocessor must be signalled when the USART is ready to accept a character for transmission. This function is performed by a signal TXRDY L. This signal can be used to interrupt the microprocessor since it can be masked by TX disable in the control word. This signal is automatically reset by the leading edge of the signal WR when a data character is loaded from the microprocessor.

Receipt of a character by the USART is signaled to the microprocessor by RXRDY-L. This signal like signal TXRDY-L is coupled through gating circuitry to the interrupt input COMM-INTfor interrupting the microprocessor when a data transfer is to be made.

The microprocessor's interrupt routine in response to COMM-INT checks the status of the USART to determine whether it is ready to transmit or receive and then performs the proper input or output operation.

Serial format input from whatever device is connected to USART 26 is carried by a signal RXD-L.

Serial format output is sent to the device connected to the USART via a signal TXD-L.

USART 25 is identical to USART 26, but it is used to interface with a remotely located computerterminal or other data processing system via a communications network which is capable of transferring data over any distance, such as the telephone system. Thus, USART 25 must monitor the ring circuit of the telephone system to enable response by the testing apparatus to a call from the remote terminal or data processing system. The signals for USART 25 have a final R instead of a final L.

The interplay between USART's 25 and 26 and microprocessor 10 is as follows. Prior to starting data transmission or reception, the USART's must be loaded with a set of control words generated by microprocessor 10. These control words define the functional definition as noted previously and must immediately follow a reset operation. The control words are split into a mode instruction and command instruction. The mode instruction defines the general operational characteristics of the USART, sync characters or a command instruction may be inserted. The command instruction defines a status word used to control the operation of the USART.

Neither USART can begin transmission until the TX enable bit in the command instruction is set and it has received a "clear to send" input via the signal CTS.

As noted earlier, during asynchronous operation of USARTS 25 and 26 the baud rate is related to the clock frequency of the signal TXC. A clock signal for each USART is generated by programmable interval timer 20. This device features an 8-bit buffered bidirectional data port for interfacing the timer with the system data bus 12. The data bus buffer serves to receive data words from microprocessor 10 which program the modes of the chip, load the count registers, and hold the count values for reading by the microprocessor. The signal SEL-TIMER, when low, selects the timer so that operations can commence. A low signal RD informs the timer that the microprocessor is inputting data in the form of a count value. A low signal WR informs the chip that the microprocessor is writing data to the timer data bus buffer in the form of mode information or loading the counters.Signals ABUS-0 and ABUS-1 from the address bus of the microprocessor serve to select one of the 3 counters to be operated on or to access the control word register for mode selection by microprocessor 10.

Each counter in the interval timer is a single 16-bit pre-settable down counter. The input, gate, and output ports are configured by the selection of modes stored in the control word register coupled to the data bus buffer. Each counter can count in binary or BCD, and each can operate in a separate mode configuration from the others. The microprocessor, during an initialize routine, must send a set of control words to initialize each counter of the timer with the desired mode and initial count information.

Counter 0 is set to the interrupt on terminal count mode. Counters 1 and 2 are programmed to be divide-by-9 counters. Output signals from counters 1 and 2 are coupled to USARTS 25 and 26 to become their respective signals RXC and TXC.

An input signal BAUD-CLK to counters 1 and 2 is a 1.536 MHz signal derived from modulo 16 counter 32, Figure 4. Counter 32 is a 4-bit binary synchronous bidirectional counter where the four counter stages are triggered on a low to high transition of the count clock input derived from the system clock signal CLK from microprocessor 10. The input signal TMR-CLK to counter 0 is derived in similar fashion from the counter 32. The signal TMR-CLK has a frequency 1/16 that of the count clock frequency CLK.

Address decode circuitry 27 in Figure 1 is shown in more detail in Figure 4. PROM 23 in Figure 1 is selected via the line SEL-DBUS. This signal is coupled to the enable input of bus driver 31 in Figure 1 and serves to connect DBUS 35 to address/data bus 12. Microprocessor 10may then retrieve data from PROM 23. DBUS is connected to the data bus ports of the PROM chips. The signal SEL-DBUS goes low enabling bus driver 31 when the signals ABUS15, 1/O and RD are all high. The signal 10 will be high when the microprocessor is reading memory and not an I/O location. Likewise, the signal RD will be high when the microprocessor is reading the selected device. The signal ABUS-15 will always be high when addressing PROM 23 because of the address assigned to PROM 23.ABUS-15 is derived from the signal A15 which is bit 15 of the upper 8 bits of the address bus 22 from microprocessor 10.

Two signals RD-MBUS and SEL-RAM are used respectively to select maintenance panel 14 and RAM 37 for an exchange with the microprocessor.

Maintenance panel 14 is coupled to address/data bus 12 via bidirectional MBUS 39 and bus transceiver 38.

The signal SEL-MBUS serves to select bus transceiver 38 when low. Driver inputs 12 allow data, address and command display data to be transferred out to maintenance panel 14 via MBUS 39 while receiver outputs 12 allow data, command and address key data from the maintenance panel via MBUS 39 to be placed on the address/data bus lines ADO-7.

The SEL-RAM signal selects RAM bus transceiver 41 when low. This couples RAM 37 to lines ADO-7 via the data output lines DO~-7 and data input lines DI~-7.

Input/Output operations to the unit under test are enabled via the SBUS~-7 lines and bus transceiver 11 when the signal SEL-SBUS goes low. This signal goes low when the input signals 10 and ABUS-7 go high. This would correspond to presenting the address of CPU Interface Logic (43 in Figure 1) on the AD~-7 lines. The I/O signal indicates that the address on the address bus in for an I/O operation as opposed to a memory access.

The port for interface between the address/data lines AD~-7 and an internal board test device is provided by board test port 28 and T-AD~-7 lines.

The firmware which controls the operation of the testing apparatus is stored in PROM 23. In the preferred embodiment, sixteen 2K EPROM chips are used. The address input of each chip is coupled to lines ABUSO-10 of the address bus. The chip select input of each EPROM chip is coupled to an output of a PROM decoder fed by lines ABUS1 1-15. The information located at the address specified by lines ABUS 0-15 is placed on the data bus of the testing apparatus via the lines DBUS-0-7.

The scratchpad function of storing data, commands and addresses temporarily during processing by microprocessor 10 is performed by the system RAM 37. The address inputs of the RAM chips are coupled to lines ABUS 0-11 of the system address bus. Data input to the RAM arrives on the Dl 0-7 bus where each one of these lines is coupled to the data input of each of the eight 4K x 1 bit RAM chips. Data output from the RAM leaves via the DO 0-7 bus. The write enable input to each RAM chip is coupled to the output signal WR from microprocessor 10. The chip select input of each RAM chip is coupled to a RAM select signal obtained by decoding ABUS bits 12-15.The signal RAM-CLKfrom modulo 16 counter 32 is also fed to the RAM, and serves as a RAM refresh signal to turn the enable input on and off in the case where the RAM chips used can be enabled only for a short time before degradation of the data begins.

The board test port and circuitry for establishing system status includes a buffer which serves as the input port for control signals from an external board tester unit. This input simulates the signals RD, WR and ID normally presented by microprocessor 10 to the control bus for controlling the system, and provides a signal MP-PRES which defines the presence or absence of maintenance panel 14 from the system. System status is continually checked by the firmware via this buffer. As noted earlier, a digital computer programmed to perform a predetermined sequence of tests can be used to control the testing apparatus via the local or remove communication ports.A signal DPU-PRES indicates to the firmware that such a specially programmed data processing unit is present on the system, and a signal T-PRES indicates to the firmware that the board test unit is present on the system. These signals are buffered onto the data bus 12.

Two signals CDI-R and RNG-R indicate to the firmware that a remove terminal is requesting command of the system. The signal RNG-R becomes active when the remote terminal calls the testing apparatus via the remote USART 25 and the telephone system. The signal CDI-R stands for carrier detect indicator and indicates to the firmware that the modem coupling USART 25 to the phone lines has answered the phone and made the connection.

These signals are buffered onto the data bus 12.

Two-way dialog between the testing apparatus and the remote computer terminal is accomplished in the following fashion. When the testing apparatus desires to send data to the remote terminal for display, the signal RTS-R is sent. This signal is derived from the RTS output port of the remote USART 25. When the remote modem and terminal are ready to receive the transmitted data, the signal CTS-R is sent to the testing apparatus, and is relayed to the remote USARTvia a multiplexer controlled by a signal WRAP-R, which allows self test of the testing apparatus by providing for a wrap-around capability such that the USART can send data to itself without the necessity of having a remote terminal connected.

Conversely, when the remote terminal or data processing system establishes a communications link with the testing apparatus, the microprocessor signals that it is ready to receive data by causing the remote USART 25 to enable the DTR-R signal. The remote terminal responds that it is ready to transmit by enabling the DSR-R signal. The data is then sent.

The actual data received by the USART comes in via the signal RXD-R. Likewise, the actual data transmitted to the remote terminal is carried by the signal TXD-R.

Synchronous operation of the USART's requires a different clock arrangement than asynchronous. The signal BITCLK-R is used for asynchronous operation and is converted into the receiverclocksignal RXC-R and the transmit clock signal TXC-R. These signals are used by remote USART 25 to control the rate of transmitting and receiving of data. In asynchronous operation, the same clock frequency is used for both transmitting and receiving. However, during synchronous operation, a separate clock signal is used for transmitting and another clock signal for receiving. The receiving clock signal is SCR-R, and the transmitting clock signal is SCT-R. These two signals are received from the local or remove terminal.

Because the PROM 23 has a minimum access time of 450 ns, a wait cycle is needed during access of the PROM by microprocessor 10. This waiting time is provided by flip-flops 53 and 54 in Figure 4. The signal ALE serves to clock flip-flop 53 causing it to be set if the data input is high; this will occur during a PROM access. With flip-flop 53 set flip-flop 54 will be clocked on the next clock pulse of the signal CLK causing the output signal PROM-RDY to go low. This signal is used to generate the RDY signal, and a high RDYsignal allows the microprocessorto continue operation. However, when the signal RDY goes low, the microprocessor will suspend operations and wait for a return by the signal to the high state. Thus, when flip-flop 53 is set, the next clock pulse will set flip-flop 54 and cause the signal RDY to go low thereby putting the microprocessor in a wait state.

The next clock pulse will then toggle flip-flop 54 causing the signal RDYto again go high and enable further operations by microprocessor 10.

A plug in board (not shown) is interfaced with the microprocessor and is used to stop the microprocessor and allow it to be stepped through the microprocessor instructions. This board can be used for debugging the testing apparatus itself.

The logic circuitry supporting the local communications interface USART 26 is very similar to that used for the remove communication USART 25. The local terminal sends data to the testing apparatus via a signal RDX-L, and it signals the testing apparatus when it is ready to transmit by sending a signal DSR-L. Similarly, the local terminal signals when it is ready to receive data by sending a signal CTS-L.

These signals are relayed to the local USART by a multiplexer used to provide for a wrap-around function under the command of a signal WRAP-L.

The microprocessor controls this signal via the zero bit of address/data bus 12.

Bits 2 and 5 of the address/data bus enable interrupts from the local or remote terminals via signals INT-ENA-L and INT-ENA-R. These signals gate interrupt requests from the local and remote terminals to microprocessor 10 via signals INT-L and INT-R. These interrupt requests are generated when the local or remote USART's signal they are ready to receive or transmit characters. The local and remote interrupt requests are ORed together to form one communications interrupt request COMM-lNT.

Bits 0 and 3 of the address/data bus 12 control wraparound mode for the local and remote USART's, and bits 1 and 4 control whether the local or remote USART's are operating in the asynchronous or synchronous mode. The signals SCR-L and SCT-L are the separate clock signals for synchronous transmitting and receiving by the local USART. They are presented as the first inputs to the multiplexer.

When selected, they become the signals RXC-L and TXC-L. In asynchronous mode, the signal BITCLK-L is switched through the multiplexer to become the signals RXC-L and TXC-L.

Finally, operation of the handshaking signals exchanged between the terminal and the local communications interface USART 26 is in all respects similar to the previous description for the remote interface.

CPU Interface Circuits During the course of testing by the automated maintenance system, the contents of certain internal registers or memory locations of the CPU might need examination. Before the contents of those registers can be transferred to data register 160 via ZMPD bus (Figure 5), the proper pathway to the desired memory location or internal register must be selected and enabled. The selection of the pathway is accomplished by writing a particular bit pattern on DCL bus, lines 0-39.

The path control and enabling function is performed by register 100. The basic construction of this register is straightforward. It includes 8 8-bit latches, driven from the 8-bit SBUS; 5 of the latches drive the DCL BUS 0-39, and the remaining 3 drive the enabling signals. An octal decoder is driven by the 3 bits ABUS 0-2, and has 8 outputs, only 1 of which is true at any given moment, which are fed to the latch inputs of the 8 latches. Each latch is set to the 8-bit pattern on the SBUS when the select signal is true, and latches the pattern set into it when the select signal goes false.

The pattern of logical l's and 0's on the DCL bus serves to operate switches in the CPU which control the pathways therein which can be accessed by the data register circuitry 160.

Once the correct bit pattern has been latched on the DCL bus to select an internal pathway in the CPU, a single line enable signal must be generated which will cause the CPU to switch the selected pathway into communication with the ZMPD bus. Once the proper pathway is coupled to the ZMPD bus, the automated maintenance system may read the contents of an internal register or the memory location addressed by the MPA bus. These enable signals are necessary because a single bit pattern on the DCL bus may access more than one internal register in the internal units. The precise register or memory location desired will be determined by which of the enable signals is activated by the AMS. For example, a given DCL pattern could access both an A register in the decimal unit and a B register in the control unit, but only the decimal unit register is desired.In such a case, a signal DU-DISP-ENA would be activated. This is one of the signals produced by the remaining 38-bit latches of register 100, these latches serving to convert information presented via the SBUS by the automated maintenance system into the single line enable signals seen as the outputs of these latches. For example, should the automated maintenance system desire display of a register in the control unit, bit 2 of the SBUS would be set "on" and hex address AS would be written on the automated maintenance system address bus.

This address AS is decoded to cause the appropriate one of the 8-bit latches to store the data on line 0-7 of the SBUS. The above events will cause a signal CU-DlSP-ENAto be activated. This signal causes the CPU to interpret the bit pattern on the DCL bus as the designation of the particular register in the control unit which is to be examined. The CPU then couples that particular register to the ZMPD bus and strobes its data into data register 160. There are separate enable signals for port display (DISP-ENA), decimal unit display, control unit display, virtual unit display, display of cache contents, memory locations in the main store, and an enable signal to allow the automated maintenance system to write to a loction in the main store (WRITE).There are also separate enable signals for the upper and lower halves of the cache store, and two signals for controlling timing margins in the control unit and memory, i.e., INH- CU-OVLP and INH-MEM-OVLP.

In order to properly test a central processing unit, certain of its operating conditions must be controlled by the automated maintenance system. The operating condition control register 190 performs this function. As with the path control and enable register 100, the operating condition control register consists basically of a set of latches fed from the SBUS, and a decoder fed from the ABUS (ABUS 0-3) whose outputs select the various latches. The latches are, for convenience, a mixture of 8-bit and 6-bit latches.

Many different operating conditions need to be controlled for a complete debug capability. For example, very often in central processor debug operations it is advantageous to have the ability to run the logic circuitry in both fast and slow modes.

Sometimes a problem in the fast mode is caused by a slow chip such that the problem disappears when the logic circuitry is run at a slower clock rate. The central processor for which this interface circuit was designed has the ability to run each of its internal units in both fast and slow modes. Two 8-bit latches serve to convert information on the SBUS to control signals which dictate which mode each internal unit of the processor is operating in. For example, when the test engineer desires that the virtual unit run in the slow mode, a command will be entered causing the AMS to activate bit 1 of the SBUS such that an output signal VU-SLOW will be latched into one of these latches to cause the virtual unit to enter the slow mode.

A further 8-bit latch serves to convert the information on the SBUS to one of five output signals used for the following purposes in controlling the CPU. A signal FINIT-CTL is used to initiate all control flipflops in the CPU. Similarly, a signal FINIT-CLR is used to clear all registers and control flags in the CPU. A signal DSCOPE-RPTtelIs the CPU to repeat the instruction stored in data register 160. When the signal is activated, the CPU will continually execute the single instruction represented by these data switches at the beginning of a scope sweep so that the testing engineer can examine critical points in the logic with an oscilloscope.Signals EXECUTE and DEXE-SWcombineto control whether the CPU executes the execute fault vector or whether it is to execute an instruction the op code of which is stored in the data registers 160. The fault vector is an address to which the CPU goes when a particular fault condition occurs. The fault condition address represents the beginning of a routine to take whatever corrective action is necessary to cure the fault encountered by the CPU. Typical stop on fault conditions are an overflow condition in an arithmetic operation or master mode entry fault where some problem occurs in a transfer between an application program and the operating system.

The stop on fault conditions are set by the automated maintenance system via a set of 4 6-bit latches in register 190, producing signals FLTSTOP 00-23 each of which represents a particular fault condition which could occur. The automated maintenance system controls which, if any, of the particular stop on fault conditions is set.

A A further 8-bit latch in register 190 sets selected stop on address conditions in the CPU. For example, a signal SOA-WS will cause the CPU to stop processing when a particular address in the working space of the virtual memory is accessed. Likewise, signals SOA-VA & WS and SOA-VA-SEGID cause the CPU to stop when a particular virtual address in the working sense or a virtual address constituting a segment ID descriptor in a disc storage backup unit are accessed by the CPU.

Another 8-bit latch sets signals which stop the CPU upon certain other conditions. For example, a signal SOA-OPND indicates a stop is desired when the address of a certain operand appears. A signal SOA-lNSTR signals a stop when a certain instruction address appears. A signal SOA-ALL causes the CPU to stop any time a particular address is accessed.

A final 6-bit latch produces signals which serve to place various internal units of the CPU in the step mode of operation. For example, a signal VU-STEP causes the virtual unit to execute only one instruction and then stop. A signal STEP serves to clock pulse generator 44 to cause a strobe pulse $STEP.1 to be generated and sent to the CPU causing the step to occur. This signal STEP is controlled by bit 6 of the SBUS, thereby vesting full control of the step strobe in the automated maintenance system.

Some of the circuitry comprising the operation condition and control register 190 is shown in detail in Figure 6. Part of this circuitry is used to generate strobe signals for use in reading and writing memory locations and reading the contents of the cache.

This circuitry also generates the strobe pulse used by the CPU in the step mode and gates the output of the pulse generator between the memory strobe and step strobe outputs the CPU. Pulse generator 44 is a flip-flop. When the automated maintenance system sets the step bit in register 190, the signal STEP is applied to the flip-flop, which changes state. Delay line 46 feeds the Q output back after a short delay to the reset input. This causes an output pulse with a duration equal to the amount of delay imposed by delay line 46.

Gates 60 and 61 serve as the output gates for the memory strobe ($AR-MP) and the step strobe ($STEP) signals. The purpose of these gates is to prevent the strobe pulse from the pulse generator from reaching the CPU under certain circumstances involving the step and display states of the CPU. The CPU has a step state and a display state controlled by a display enable flip-flop in the CPU. The state of this flip-flop is controlled by the signal DISP-ENA from register 100, this signal being under the control of the automated maintenance system. Gates 60 and 61 prevent the step strobe output signal from gate 61 from reaching the CPU when the display enable flip-flop is in the display state. That is, the signal $STEP can reach the CPU only when the CPU or a unit therein is in the step mode.Gate 60 has two additional inputs beside the strobe input from the pulse generator 44. These inputs are the signal CACHE/STORE and the signal AR-BUSY-CC. These two signals act as prerequisite conditions for transmission of $STEP.1 strobe signal to the CPU as the $AR-MP strobe signal. The signal CACHE/STORE in the output of gate 62 which has the signals CACHE DISP and STORE-DlSP as inputs. These two signals come from register 100. As noted in discussing register 100, these two signals serve to enable display by the automated maintenance system of designated locations in the cache or the main memory.Thus, when either of these two signals is active, the signal CACHE/STORE indicates that the automated maintenance system is working with memory and the pulse from generator 44 should be steered through gate 60 instead of gate 61 to act as memory strobe signal $AR-MP. The one other condition to gating the pulse through gate 60 is that the CPU signal that is ready to access another memory location. This is the purpose of the AR BUSY signal from the CPU. This signal indicates that the address register in the CPU is not busy, and the CPU is ready to make another memory access. When these two conditions are met, the memory strobe signal is gated to the CPU thereby causing a read or write operation to a memory location or a read of a cache location selected by the automated maintenance system.

Likewise, there are two conditions to gating the strobe pulse from pulse generator 44 through gate 61. Those conditions are that the automated maintenance system is not accessing cache or the main memory, as indicated by the inverted CACHE/STORE signal. The other condition is that the CPU must signal that it has stopped processing under its own control and that it is ready for control to be given to the automated maintenance system. This state of affairs is indicated by the signal STEP/DIS which is the output from gate 62. The inputs (shown collectively as FSTEP) to this gate are signals from the CPU indicating its internal status. For example, when the CPU has stopped its normal processing and the virtual unit has been placed in the step mode, the CPU will signal these facts by sending a signal FVUSTEP-VL to gate 62.

The input signals to gate 62 do more than just signal that the CPU has stopped and a particulari unit has been placed in the step mode. Essentially, they serve as stop and go signals for the automated maintenance system. That system may not have control of the CPU until one of these signals indicates regular processing therein has ceased and the AMS may have control of the internal pathways of the CPU. Such cessation of processing occurs when any stop on address or stop on fault conditions is met. When stop on address condition has been met, a signal FADDRSTOP-CC will be sent to gate 62.

Likewise, when a stop on fault condition has been met, a signal FSTOPONFLT-CP will be sent to gate 62. Similarly the automated maintenance system may not examine any internal register or memory location until a signal FDIS-CP has been received.

The output signal STEP/DIS from gate 62 is inverted and serves to enable the display enable 8-bit latch in register 100 when the CPU is in a state where it can receive the display enable commands.

The inputs FSTEP to gate 62 comprise some 7 different signals from the CPU. These, along with signal AR-BUSY and a signal CPU-TEST, form the response signals 82 (Figure 5). These signals are fed to a pair of 6-bit buffers, which are controlled by suitable select signals from the AMS and feed the SBUS. Thus these response signals can be passed through to the SBUS for inspection by the AMS.

The register 190 also includes a 6-bit buffer fed from the SBUS which serves as a buffer for signals from the automated maintenance system expanding the systems self test capability. There are certain problems in the automated maintenance system which cannot be tested by the board tester of the AMS. The outputs of this buffer are connected to individual indicator LED's (not shown) which are visible to the testing engineer. When a certain problem is detected which the board tester cannot indicate, the automated maintenance system can indicate this fact by lighting the specific LED assigned to that particular problem.

The interface circuit described herein has a wrap around test capability allowing the automated maintenance system to self test without the presence of a CPU. This wrap around is provided by the output signals DO-STEP and the signal TSB-WRAP from 2-bit latch 63. Bit 2 of the SBUS controls the signal DO-STEP, and bit 1 of the SBUS controls the signal TSB-WRAP. By setting bit 2 of the SBUS, the automated maintenance system can simulate a response from an imaginary CPU indicating that it is ready to receive the step strobe signal $STEP-MP.

This step strobe signal serves to start the CPU in operation again after it has been stopped. By setting bit 1 of the SBUS, the automated maintenance system may simulate control point data coming back from an imaginary CPU via the TSB bus. The output signal TSB-WRAP goes to an additional 8-bit latch in register 100 and serves as an enabling signal thereof. That latch serves as a self test register allowing a bit pattern on the SBUS simulating a control point bit pattern from an imaginary CPU to be transmitted to the control point register 57, which transfers the bit pattern back to the SBUS where the automated maintenance system can read it.

The control point register 57 includes an 8-bit buffer which serve to store control point information regarding the status of various control flip-flops in the internal units of the CPU so that the automated maintenance system can test the status of those units. Normally, this control point information comes in on lines TSB 00-07 comprising the TSB bus which forms part of the enabling signals bus from register 100.

The automated maintenance system may be reset by the CPU under test or manually via an initialize switch. A monostable (not shown) serves to generate the pulse necessary for this initialization. The monostable is triggered by a signal from the CPU on power up, or the initialize switch for the CPU, or the manual initialize switch mounted on the interface circuit board.

Some means must be provided to provide an address to the CPU for use in setting stop on address conditions, reading the cache and reading or writing to main store memory locations. This function is performed by the address to CPU register 58. This circuitry comprises 6 6-bit latches fed from the SBUS, and a decoder fed from the ABUS and selecting the 6-bit latches. The latches serve to convert information on the SBUS into a 34 bit address for transfer to the CPU by the MPA bus.

In the prior art maintenance panels, a long string of manually operated switches was used to enter data into the CPU and a long line of LED indicators was used to display data in binary form from the CPU. Use of these devices was difficult and slow. In the present system, both are replaced by the data register 160. This comprises a set of latches and a set of buffers, each set with its associated decoder for selection, fed from the ABUS. The set of latches are 6 6-bit latches fed from the SBUS and feeding the ZMPD bus, which is a 36-bit bidirectional bus. The set of buffers are 6 6-bit latches fed from the ZMPD bus and feeding the SBUS; these buffers only feed their contents onto the SBUS when selected and enabled.These sets of latches and buffers are used to write data into internal registers or memory locations of the CPU, to provide instruction op codes and to transmit data such as the contents of an internal register or memory location back from the CPU to the automated maintenance system for display. The register 160 also replaces the prior art data scroll wherein a manually operated rotary switch was used to select one of a plurality of data scrolls for display on the LED indicators of the prior art panels. By operation of the rotary switch, the test engineer selected which of the internal registers of the machine he wanted to examine.

The control points in the decimal unit of the CPU are accessed through the BCP bus coupling the CPU to DU control point register 76. There are 72 individual lines comprising the BCP bus, and these are condensed into 6 bits on the SBUS by the register 76. This register consists of 12 6-bit multiplexers, 2 (one upper and one lower) for each of the 6 bits of the SBUS fed from register 76. The ABUS feeds the multiplexers, each of which thereby selects 1 of its 6 inputs. In addition, a pair of select signals are produced by the AMS to select either the upper or the lower multiplexer of each pair. Thus the 72 BCP bus lines are divided into 12 sets of 6, and any desired set can be coupled through to the SBUS.

Maintenance Panel Figure 7 is a highly simplified diagram of the maintenance panel. The panel consists of a keyboard 34 and logic circuitry 33. The keyboard is coupled to the logic circuitry 33 by two buses, one carrying signals F1 -F4 which correspond to the 4 function keys "enter", "command", "terminate, and "clear", and the other carrying signals B1-6 which carry a binary coding representing which of any of the other keys is depressed. (Conventional signals, such as voltage level signals and strobe signals, are omitted.) The logic circuitry 33 is coupled to the AMS by means of the ABUS (4 bits), the bidirectional MBUS (8 bits), and a number of control signals on bus 21, both to and from the AMS.

One function of the signal F1-F4 is to cause an interrupt to microprocessor 10 in Figure 1 to force it to enter an interrupt routine for servicing the maintenance panel. This routine reads the data on the MBUS to determine which key has been depressed.

Generation of this interrupt request signal MP-INT is the responsibility of flip-flop 70 in Figure 8. This flip-flop will be set by any of the four function signals F1-F4. When any of these signals is energized, gate 73 sets flip-flop 70. The signal MP-INTthen signals that the maintenance panel is requesting service.

Information is transferred to and from microprocessor 10 by the 8-bit MBUS 39. Information from the data keys of the encoded alphanumeric keyboard comes in as inputs to a bus driver 75 on signal lines B1-6. This bus driver drives the MBUS. The MBUS is also coupled to an 8-bit latch 78 which functions to convert the signals F1 -F4 into a 8-bit pattern for each key. Each pattern comprises a logical 1 at bit 5 and all 0's on the other 7 bits except for one which corresponds to the particular key that was pressed.

The MBUS must be switched between bus driver 75 and latch 78 to allow coupling of the four function keys and the alphanumeric data keys to the microprocessor. This switching function is performed by flip-flop 79 which is set when any key other than an F1-4 key is depressed. When flip-flop 79 is set, bus driver75 is enabled, thereby connecting the MBUS to the data key signal lines. When flip-flop 79 is reset, this enables latch 78 and couples the four function keys to the MBUS. The signal RD-MPD from the microprocessor is ANDed with the outputs of flipflop 79 so that the microprocessor can control reading the MBUS. The state of flip-flop 79 is controlled by the 0 output of flip-flop 70 and the strobe signal STB from the keyboard. The latter signal is a 1 when any of the four function keys is depressed and a 0 when any of the data keys are depressed.

Figure 9 shows the circuitry controlling the display meansforthe data, address, and command displays (Figure 2). A decoder 82 is fed with the ABUSO-3 signals, and has 16 outputs, 15 of which are used.

Three of the outputs are used to select 3 8-bit latches 85 to 87, which are fed from the MBUS as shown.

The displays themselves consist of a total of 23 hexadecimal display latches; 12 for the data display, 8 for the address display, and 3 for the command display. The first 2 display latches, 15 and 16, for the data display are shown in Figures 2 and 9. Each of these display latches can display a hexadecimal character, and therefore 2 such display latches can be set simultaneously from the 8-bit MBUS. The display latches are therefore paired into 12 pairs (with the last pair, one of the 2 pairs for the command display, having one display latch omitted). To select one of these 12 pairs for setting data therein, the remaining 12 outputs from the decoder 82 are used; these outputs are labelled D01 to D1011, A01 to A67, and C01 to C2 as shown. Thus by means of decoding the signals ABUS0-3, any desired pair can be selected for latching information therein from the MBUS.A signal WR-I from the microprocessor 10 serves as the enable signal for an octal latch 83.

The latch 83 feeds the eight individual LED's CR1-8 serving as prompting and status indicators. Thus it is seen thatthe microprocessor can light any of these individual LED's by raising the appropriate bit on the MBUS.

An oscillator 84 produces an output signal BLANK which will tri-state the output lines of latch 83 at the rate of 1 kHz. This causes the indicator LED's to flicker on and off at a rate too fast for the eyes to see, but serves to conserve energy used by the display means of the maintenance panel. This signal BLANK is also coupled to the three octal latches 85,86 and 87. Again, this signal serves to tri-state the output of these latches. The outputs of these latches control the hex display latches. The blanking outputs from latches 85,86 and 87 serve to blank the hex display latches.

When microprocessor 10 wishes to write data into a particular pair of hex display latches on the maintenance panel, it writes the desired bit pattern on the MBUS bits 0-7. Simultaneously, it writes the correct address via bits 0-3 on the system ABUS.

This causes four-line-to-sixteen-line decoder 82 to lower one of its inputs which is coupled to the latch input of the desired hex display latch pair. This causes the hex display latches to light their displays with the desired characters. When a display must be blanked so that new data may be displayed, microprocessor 10 writes the correct information on to the system MBUS, causing one of latches 85,86 and 87 to raise the blank input of the desired hex display latch, thereby blanking out the information. New information can be written to this hex display latch and a new latch signal sent to it while the display is blanked.

Claims (15)

1. In a digital computer system, testing apparatus for testing the system comprising: a memory storing instructions forming a program which the testing apparatus follows in testing the unit; entry means for entering data, addresses, and commands to select the functions performed by the testing apparatus; display means for displaying data from the unit; and control means which reads instructions from the memory and is responsive to the data, addresses and commands from the entry means to send control signals and data to the unit to cause the unit to perform desired operations, monitors the operation performed thereby in the unit, and passes the results to the display unit for display.

2. Testing apparatus in a digital computer system according to Claim 1, wherein the control means is a digital computer.

3. Testing apparatus in a digital computer system according to Claim 2, wherein the digital computer is a microprocessor.

4. Testing apparatus in a digital computer system according to any previous Claim, including interface means coupled to the control means such that data, addresses, and commands may be entered from a remote location via the interface means and data from the unit sent for display at the remote location via the interface means.

5. Testing apparatus in a digital computer system according to Claim 4, including a plurality of such interface means.

6. Testing apparatus in a digital computer system according to either of Claims 4 and 5, wherein the or an interface means is coupled to a communications network.

7. Testing apparatus in a digital computer system according to any of Claims 4 to 6, wherein a or the interface means includes means for converting data between parallel format in the testing apparatus and serial format for passage between the interface means and the remote location.

8. Testing apparatus in a digital computer system according to any previous Claim, wherein the entry means comprise a keyboard for entering the data, addresses, and commands.

9. Testing apparatus in a digital computer system according to any previous Claim, including also a maintenance panel having entry means for entering data, addresses, and commands and display means for displaying data from the unit.

10. Testing apparatus in a digital computer system according to Claim 9, wherein the maintenance panel is portable.

11. Testing apparatus according to either of Claims 9 and 10, wherein the keyboard includes a plurality of function keys and a plurality of data keys, operation of a function key causing a distinctive signal to be sent to the control means.

12. Testing apparatus according to Claim 11, wherein the display means includes a plurality of indicators which display prompting signals indicating to an operator the status of the system or the stage reached in the entry of information.

13. Testing apparatus according to any previous claim, including an interface circuit, coupling the testing apparatus with the digital computer system undertest, comprising: a first means for converting information from the testing apparatus into signals for controlling the pathways in the system accessed by the testing apparatus and for controlling the operations performed and the conditions of performance of the system; a second means for receiving control point information from the system indicating the internal status thereof and for transferring it to the testing apparatus; a third means for supplying address information from the testing apparatus to the system for use by it in certain operations;; a fourth means for transferring data supplied by the testing apparatus to the system and for receiving and holding data from the system as requested by and for transfer to the testing apparatus; and a a data bus coupling the testing apparatus to the first, second, third and fourth means for supplying the proper information to those means for performing its operations and for collecting information from these means for transfer to the testing system.

14. Testing apparatus according to Claim 13, wherein the interface circuit is coupled to the rest of the testing apparatus by means of the data bus, an address bus, and a control bus, the address bus controlling which registers in the interface circuit are enabled for transactions with the data bus; the first means comprises a path control and enabling means, comprised of a plurality of registers, which receives data for transfer to the system via a DCL bus for defining the pathway to be accessed in an enabling signals bus for selecting and enabling the selected pathway to be accessed; and an operations condition control register means, comprised of a plurality of registers for receiving data for transfer to the system in the form of control signals that set the desired conditions of operation for the system, and for receiving response signals from the system verifying that the desired conditions of operations have been set; the second means comprises a control point register means comprised of a plurality of registers for receiving control point information from the system indicating the status of the control flags therein; the third means comprises an address register means comprised of a plurality of registers for transferring address information to the system via an MPA bus for controlling certain selected operations in the system; and the fourth means comprises a data register means comprising a plurality of registers for transferring data to the system via a ZMPD bus for causing certain selected events to occur in the system, and for receiving data from the system.

15. Testing apparatus in a digital computer system substantially as herein described and illustrated.