GB2054328A - Improved teletext decoder - Google Patents

Abstract

The decoder comprises an input TIM, processor PM and display DM. Module TIM includes an input memory arranged to store for each t.v. frame period the two lines of teletext data transmitted in each field banking period. Module DM includes a page memory arranged to store information on all the characters to be displayed to make up a page display. Processor module PM during the t.v. raster field, following the reception of two lines of teletext information, processes that data and updates the display memory. Module DM drives the t.v. display TVR autonomously with the microprocessor having over-ride access to the display page memory. During the reception of the two line teletext data the microprocessor is inhibited. Keyboard KB controls data selection via module PM. <IMAGE>

Description

SPECIFICATION Improved teletext decoder The present invention relates to teletext decoders for use in television based information systems.

Description of the Prior Art Currently there are two broad types of Teletext decoders in production; the MSI/SSI (mainly TTL) based designs, in use with professional organisations and enthusiasts, and the custom LSI designs, e.g. the "TI FAX" module by Texas Instruments. The latter type is being incorporated into new domestic television sets by makers and, as a result, the price of these decoders is falling slowly. However, such decoders are not readily modified or upgraded since they are designed to perform a highly specialised function.

With the advent of the British Post Office PRESTEL system, it has become clear that the role of the domestic television is open to fundamental change; not only can it be a highly cost effective home computer terminal in its own right. T.V. games, computing facilities, and information display in general, all share a large amount of functions in common yet their precise requirements are still subtly different.

Aim of the invention It is the aim of the invention to provide an improved teletext decoder which can readily be adapted to accommodate viewdata facilities and which may also be adapted to provide a small data processing system.

According to the invention there is provided a teletext decoder comprising (i) an input circuit including an input memory to store for one television (t.v.) frame period the data from the two field blanking interval t.v. video signal lines allocated to the teletext information system, (ii) a display circuit including a second memory arranged to store a full teletext page and arranged to independently drive a domestic television receiver to produce a teletext page display and (iii) a micro-processor arranged to process the data received in the input circuit to produce display information in the display circuit during the t.v. period immediately following the reception of the input data.

It may, on first consideration, appear to be expensive to use a micro-processor to perform a task which can be handled by existing dedicated hardware. However, it is the fact that the processor has so much processing capacity which gives the system of the invention flexibility and so in the longer term, makes it cost-effective. For this reason, one embodiment of the invention makes provision for later additions; buffered address and data lines give the system spare drive capability for example. The addition of PRESTEL for example involves the addition of an extra module containing "viewdata software" in a PROM, plus interface circuitry to communicate with a telephone line driven Modem, which may be internal or external to the system.

Description of the drawings The invention will be more readily understood from the following description which should be read in conjunction with the accompanying drawings. Of the drawings Figure 1 shows a block diagram of one embodiment of the invention.

Figure 2 shows in more detail the modules of Fig. 1.

Figure 3 shows in block diagram form the equipment required for the storage of the teletext data lines as they are received while Figure 4 shows in block diagram form the equipment used for the display store.

Description of one embodiment Before describing the embodiment in detail, the requirements for decoding and display of Teletext information will be examined briefly.

The teletext information is contained in two hitherto spare lines transmitted by the boradcasting authority during the field blanking interval of the normal 625 line television waveform; each line contains enough information to define a complete 40 character row on a teletext page which comprises 24 rows.

The information consists of coded characters (similar to ASC11 code but using the standard TELETEXT/VIEWDATA character set) intended for display purposes, and additional words to define the particular magazine and row being transmitted. A 'special' row, called the Header (row 0) also carries further information, i.e. the Page number for that row and subsequent rows of the same magazine.

(Group of 100 pages). The coded characters and addresses, preceded by synchronising and framing signals are transmitted directly in NRZ (non-return-to-zero) form.

The bit rate of the transmitted signal is 6.9375 Mb/S which is 444 times the line frequency. Data words are 8 bits long with odd parity for display characters and Hamming-coded words for address and control. This enables error detection, and correction in some cases.

It can be seen that decoding such transmissions is quite a complex task. Basically, however, the function breaks down into four main parts: 1) Recovering the data, correctly framed, from the video signal.

2) Checking whether incoming data is that requested by the user.

3) Storing this data at the appropriate address in a display memory.

4) Displaying the memory contents on the t.v. screen.

The main criterion in designing the decoder according to the invention is to decide exactly which tasks should be performed by the processor, and those that have to be performed by additional hardware. Fig. 1 shows the Three basic modules which are used as follows: 1) Teletext input circuitry and memory module (TIM) 2) Processor module (PM) and 3) Display module (DM).

These modules are connected to a domestic t.v. receiver TVR.

The composite video input CVI to the teletext input module TIM is derived from the IF strip IFS of the t.v. receiver and the red R, green G and blue B signals are fed to a video switch interface VSI and then to drive the t.v.

tube.

The details of the operation of the modules will be more readily appreciated with reference to Fig. 2.

Data In put Function Data from the two data lines is transmitted at 6.9375 Mb/S. This is too fast to be handled by the microprocessor module PM in real time. The incoming DATA is converted by a serial-to-parallel converter SIPO to 8-bit bytes at a rate of 867.1 8K bytes/second.

Dedicated decoders are used to handle this information since they can perform several tasks at once (e.g. checking parity and performing error correction simultaneously), whereas the micro-processor module by its very nature is constrained to function "one step at a time". For complex operations, such as hamming checks, this would mean following bytes would arrive before the processor module PM was ready to accept them. Fortunately the average data rate is very much lower, approximately 1 page (1 K bytes) per second (4K bytes/sec) i.e. over 200 times slower.There is thus sufficient time for the processor unit PM to handle the incoming data during the display period, so the two data lines are transferred to a temporary store TSR (a small read only memory RAM) after minimal processing; in fact the input data stream is examined for framing code by detector FCD in order to locate byte boundaries, converted to 8-bit bytes and put into the 2line store TSR without any other operations being performed on it. This store, therefore, contains the whole data stream complete with framing code, magazine and row address groups etc. as well as the 40 characters per row (or 32 for row 0) intended for display. At this stage no parity or hamming checks have been made, no page numbers checked; all these functions are performed during the following frame scan period (display period) by the micro-processor PM.The location of each byte in the temporary store is determined by the counter BYC which is initialised (or RE SET) by the detection of framing codes by the framing code detector FCD and incremented by the byte boundaries being detected again by the framing code detector FCD. The processor read address is applied to the RAM via an ored buffer OR so that the processor PM can gain access to the contents of the store TSR during the following t.v. raster period; similarly the RAMI/O lines can be driven by the input bytes or can drive the processor data bus as appropriate.

Fig. 3 shows in more detail the equipment required to handle the reception of the two lines of teletext information received for each t.v. frame. The composite video signals enter the equipment of Fig. 3 on lead CVI and this is applied to a synchronisation separator circuit SS and to a serial data extraction circuit SDE. The synchronisation separator circuit SS extracts the frame start FS and line start LS signals which are used in the teletext line window circuit TLW to produce signal HLT indicating a "window" spanning the two line period of the reception of the teletext information. Signal HLT is also used to halt the microprocessor for the two-line window period.

The output from the serial data extraction circuit SDE is used to drive a serial to parallel converter SPC and a clock recovery generator CG. The serial to parallel converter is also fed with the recovered clock signals CLK to clock the data bits received. The eight bit parallel byte output of the serial to parallel converter SPC is fed to a data buffer DBFR for intermediate storage and is monitored by a framing code matching circuit FCM. The framing code snatching circuit produces a signal MS each time the framing code is detected.

The recovered clock signals CLK drive a byte counter BYC which is reset at the start of the two line period by the MS signal. The byte counter is also controlled by the line sync signal LS. The byte counter BYC is used to generate addresses in the two line read only memory 2LRAM (TSR) over leads RAL to allow successive outputs from the data buffer DBFR to be inserted in the correct location in the RAM.

In operation the equipment of Fig. 3 extracts the composite video signal and converts it to eight bit parallel bytes. Under the control of the recovered clock driven byte counter BYC successive parallel data bytes are fed into the two line random access memory 2LRAM.

During this period (i.e. the two line teletext data reception window period) the signal HLT is generated by the teletext line window circuit TWL and this signal is used to inhibit the micro-processor so that the two line random access memory 2LRAM is exclusively under the control of the byte counter BYC and the data buffer DBFR during the data window period. During the following t.v. frame raster period, after the reception of the teletext data, the byte counter BYC is disabled and the micro-processor halt signal HLT is removed.

This allows the micro-processor to return to the program it was executing to for example access the bytes in the memory 2LRAM as required. The micro-processor addresses the RAM over leads uPAL and receives the information read from the RAM on its data bus uPDBUS.

Assuming that the contents of the RAM had been processed, and is required for display, the micro-processor MP (Fig. 2) proceeds to compute the required address in the display Page Memory DRAM and transfers the information to the display store in the display module DM under software control. These operations will be described more fully later.

First, however, it is appropriate to consider the larger RAM used in the display module DM and its addressing scheme in more detail.

Page Memory RAM Addressing scheme A full Teletext page consists of 24 rows of 40 characters each, i.e. 960 characters in all.

Two 1024 X 4 bit RAM chips are used to store a page leaving 64 spare locations. However, if direct RAM addressing is attempted a problem arises as follows; 24 rows require a 5-bit code to specify each column number; eleven bits therefore, are required to define any given location. However, the 1 K X 4 RAMS have only 10 address lines. It is possible, however, to take advantage of the restricted range which the row and column numbers have, and use combinational logic to "condense" the 11 bits to 10 bits prior to applying these to the RAM. The disadvantage of this method is that for the processor module PM to compute any given address is complex and, therefore, time consuming, since there is no simple algorithm to be followed. A different scheme is employed in this system.The RAM is addressed by one of two sources; in the display mode by a 1 0-bit presettable counter, located on the input module, and in the writing mode by the processor module PM address bus. Both are fed to the RAM by way of ored buffers which are enabled as appropriate. The processor also has read access to the display RAM.

During the display period, the 10 bit counter is preset to 40 times the current row number (during line syncs) and incremented by READ CLOCK during active line time. Thus the address of any characters in RAM is simply (40R + C) where R is the row number (0-23) and C the character number (0-39).

This decimal address is expressed as a 10bit binary number. During writing mode, the processor module is transferring data from the temporary store to the Page Memory RAM; the destination of each character is computed and applied to the address bus on A0-A9, and the tristate buffers are switched to disable the 10bit display counter from driving the RAM address lines.

The operation of the display store will be better appreciated with reference to Fig. 4.

During each t.v. raster display period the row counter RC is stepped on for each row and is reset when the frame sync signal FS is produced. The output of the row counter is multiplied by 40 in the X40 circuit and the result is set into the display character counter DCC. Accordingly the DCC counter provides the absolute character address and this is incremented by the read clock signal RCS which is generated by the logic which controls the ROM converting the characters for display into a dot matrix. The periodicity of RCS is of the code of 1 uS.

The counter DCC is also controlled by the processor write strobe PWS which is used to inhibit the output of the counter, not its counting function, whenever the micro-processor requires to write into the display store.

The micro-processor applies the required random address to leads uPAB together with feeding the data to be written into the display store DS into the buffer DSBFR which is enabled by the processor write strobe PWS.

The signal PWS also is used to inhibit the display store DS read-out buffer DSRB to stop the display store addressing the ROM when the processor is feeding data into the display store. Due to tube persistance the latter "freezing" of the display store cycling will not be detected by the user.

Thus it can be seen that the micro-processor's task is mainly concerned with functions (2) and (3) mentioned above while the faster, real-time operations are performed by dedicated hardware in the input circuit TIM and the display circuit DM. However, it should be bourne in mind that it is not completely desirable to fully occupy the processor so as to give flexibility to the design. Also, the split chosen means that the processor module is not restricted to the prime function of decoding teletext transmissions, which could have been the case otherwise. Generally, however, the processor is simply too slow, by orders of magnitude, to handle serial data directly. Returning now to Fig. 2 the function of the micro-processor will be discussed.

Processor Function Time is the prime consideration in the teletext program as there are roughly 20 milliseconds to process two lines of data. The basic oscillator on the processor card is 921.6 KHz giving a cycle time of 1.08 microseconds.

Most display control functions are controlled by software, e.g. CLEAR PAGE, RE VEAL/CONCEAL, NEWSFLASH/SUBTITLE, PAGE SELECTION, TV ONLY, UPDATE, ETC.

The interface to the software is via a keypad or keyboard KB which drives a keyboard latch circuit KBL interfacing into the micro-processors data bus DO-D7. The keyboard KB is used to select the various software routines, i.e. PAGE SELECTION, TIME CODING, TV/TELETEXT/Vl EWDATA SELECTION, TV CHANNEL, UPDATE, SELECT NEXT PAGE, FREEZE PAGE, REVEAL/CONCEAL.

The keypad itself produces a 4 bit word, plus "data valid" strobe. The system will, therefore, accept other control inputs (e.g. an ultrasonic link) which can be made to output the same format. The full keyboard uses the full 8 bits of the keypad register.

The great advantage of this flexible system is that its operation is capable of being modified as the user wishes, merely by re-programming these PROMS, or substituting other PROMS containing different instructions. This covers not only modifications such as whether for example headers should roll or not, but more fundamental changes as well.

The basic processor module PM contains primarily the micro-processor and PROM chips. Address and data busses are buffered (true address, inverse data) with provision for extra RAM, PROM.

The micro-processor used in one embodiment is the M6800 which cannot directly check parity. This function is implemented in hardware shown as PG in Fig. 2 when the MPU writes a word to the parity circuit it is, in fact, loading a 4 bit register with the result (which, being hardware generated, is available shortly after the data stabilises on the bus). A micro-processor read operation gates the 4 bit register contents back onto the data bus. One by-product of this solution is that parity over full byte, plus that over fewer-bit groups, can be determined simultaneously. This saves time when the processor is performing its Hamming check subroutine.

The teletext software occupies approximately 1 K of the 4K PROM (2 x 2716) available on the processor card. The remaining 3K or so is thus available for other software, e.g.

BASIC or machine code monitor program.

Of course the processor is designed to support fully system expansion with teletext facilities. Prestel/Viewdata is one such application, whereby the addition of a Modem plus appropriate software makes the system of the invention a fully fledged auditing terminal; other applications are just as easily catered for.

The keypad (or keyboard) register KBL is located on this the processor bus also. Like the parity register, its contents may be read by the micro-processor when required; however, it is loaded asynchronously by a strobe pulse from the keypad KB. The micro-processor can, however, write zeros to this 8 bit register KBL by the simple expedient of applying a pulse to the reset line. Although the keypad requires only 4 bits the keyboard register KBL is arranged to hold a full 8 bits.

This is to cater for the provision of full keyboard facilities.

Display Function DSP Assuming that the processor has transferred information to the main display DRAM, the only task remaining is to convert this into signals which, when fed to the RGB output stages of the TVm produce a full colour display on the screen. This form of interconnection is generally called 'direct interfacing' since it involves modification to the receiver circuits; for 'aerial input' decoders the electronically generated video signals are PAL encoded and modulated onto a spare channel (Ch 36), by way of a tuner/encoder unit.

The display consists of 24 rows of 40 characters, the first 8 of Row 0 being blank (space characters) in Teletext displays. In this design, a row consists of 10 TV lines per field. This means that the viewer "sees" 20 lines per row every 20 ms, due to persistance of vision and, to a lesser extent, the time taken for the phosphor output to decay. Thus 20 X 24, i.e. 480 TV lines are used for display. Taking into account the lines lost during frame blanking and the curvature of screen boundaries, this number lines fits nicely into the available space. Display height is thus fixed at 480 lines, although the read addressing circuitry can be made to commence counting at a variable time after frame sync, in order to centre the display.

Display width is dependent on the speed of an oscillator on the display card DSB in the display clock control logic RCC. This may be adjusted to centre the display in a horizontal sense with the left margin determined by a monostable triggered by line syncs. Displaying the RAM contents requires the generation of three signals (Red, Green and Blue) to drive the TV interface card or PAL encoder unit. If we assume that the left and right hand margins each correspond to 7uS of scan time per line, then 40uS are available to display 40 characters which conveniently means each character period is 1 uS. This figure is, of course, altered slightly by adjustment of the display width control.

Every 1 uS, therefore, the display card requires an 8 bit input from the display RAM. 7 bits are used to define upper and lower case characters based on a 5 X 7 matrix (by means of a character generator ROM) and also graphics shapes (by direct gating of bits 1, 2, 3, 4, 5 and 7). The extra bit is to control the cursor. The entire page memory (display RAM) is accessed sequentially during the display period via the read addressing circuits on the input card. The circuitry is controlled by row clock" and "read clock" signals from the display clock control logic RCC to provide all the display facilities in the latest BBC/I BA/BREMA Teletext Joins Specification, including Double Height Characters, Graphics Hold etc.

It produces the Reveal/Conceal function under instruction from the MPU using the control register CR (Fig. 2). Outputs R, G, B and "OPEN BOX" giving full colour full-facili ties, display with newsflash/subtitle boxing and inserts.

T.V. display character generation is performed by the ROM (Fig. 4). This is fed by the 7 bit ASC11 output from the display memory DS and the 4 bit line address from DS routing the relevant count from DCC. The dot patterns for display are loaded into shift registers CCSR which generate the required tube control signal R, G and B.

Claims (8)

1. A teletext decoder comprising (i) an input circuit including an input memory arranged to store for each television (t.v.) frame period the two lines of teletext data transmitted in the t.v. field blanking period, (ii) a display circuit including a second memory arranged to store a full teletext page and adapted to independantly drive a display device which produces teletext information on a domestic t.v. receiver and (iii) a micro-processor arranged to process the data received in the input circuit to produce information in the display circuit during the t.v. raster field period immediately following the reception of the input data.

2. A teletext decoder according to claim 1 in which the input circuit includes (a) a serial to parallel converter for converting the incoming teletext data stream into parallel bytes, (b) a byte counter and (c) a two line random access memory and in which during the reception of the teletext data the byte counter controls the writing of successively received data bytes into random access memory.

3. A teletext decoder according to claim 2 in which the input circuit inhibits the microprocessor while the teletext data is being received.

4. A teletext decoder accrording to any one of the preceding claims in which the display circuit includes a cyclic counter adapted to cyclically address the second memory in synchronisation with the t.v. raster to provide a stream of character information which is used to address a read only memory to generate the information for controlling the t.v. picture circuits to display the required characters.

5. A teletext decoder according to claim 4 in which the second memory includes an output buffer which is inhibited when the micro-processor writes to the second memory.

6. A teletext decoder according to claim 5 in which the micro-processor inhibits the output of the cyclic counter when the microprocessor writes to the second memory.

7. A teletext decoder according to any one of the preceding claims in which the microprocessor data bus is terminated such that external devices are connectible thereto.

8. A teletext decoder substantially as herein described with reference to the accompanying drawings.