GB2048529A - Error detection and correction system - Google Patents

Abstract

In an EDAC system, words to be encoded are partitioned, by interface 10, into 2 interleaved field of odd and even bits. Each field is separately encoded, at 11 and 12, and the encoded fields are interleaved at 13. For decoding, the encoded word is partitioned, at 14, and each field is decoded (16, 17) and corrected (20, 21) before interleaving at 24 to reproduce the original word. Greater immunity to errors bursts is achieved. Further, a cyclic redundancy code (CRC) check is used (25, 26) for additional error detection, using an polynomial f[g(x)] which is chosen as a factor of the EDAC generator polynomial g(x). The same check bits in the code word are thus used for both the EDAC check and the additional CRC check. <IMAGE>

Description

SPECIFICATION Error detection and correction system The present invention relates to error detection and correction (EDAC) systems.

Such systems are known from the book "Error Correcting Codes", W.W. Peterson, MIT 1861. Among the codes known there are parity checks, cyclic codes, Hamming Codes, BCH codes, and Fire codes.

It is a characteristic of such codes that they permit a trade-off between error detection and error correction.

For example, a particular code may produce code words which differ from each other by a minimum of 5 bits. This may be used for pure error detection, with errors of up to 4 bits being reiiably detected but not corrected; for error detection and correction, with errors of up to 3 bits being reliably detected and errors of 1 bit being corrected; or for pure error correction, with errors of up to 2 bits being detected and corrected.

It is well known to select a Hamming, BCH or Fire code as the main error detection and correction code of the system; to provide each code word with an additional check bit as a parity check to detect errors in the received word; and to select a secondary cyclic redundancy code (CRC) to provide enhanced error detection capabilities.

It is seen that the addition of EDAC check bits, cyclic redundancy code checks bits, and parity check bits to a given information word directly affect its length and therefore have a direct bearing upon system capabilities. Thus, the length of a code word may determine the speed with which information may be transmitted, and may be determinative of the amount of information which may be stored within a given storage medium. The problem of avoiding a miscorrection has generally been approached by selecting EDAC codes having capabilities of detecting errors beyond the realm of those which are statistically probable in any given system. Enhancing the error detection capabilities of a given system by the selection of a more complex code polynomial tends to increase the complexity of the EDAC encoder and decoder circuitry and to inefficiently increase the length of the code word.

The present invention therefore has as its object the improved efficiency in the utilization of code words used to provide error detection and correction and supplementary detection capabilities.

Accordingly the present invention provides an error detection and correction system comprising: partitioning a data word into at least two interleaved fields; encloding each partitioned field in accordance with a selected EDAC code generator polynomial; decoding each of the partitioned field in accordance with the polynomial to provide an error syndrome; correcting the partitioned fields in accordance with the error syndromes; and interleaving the corrected partitioned fields to reproduce the data word.

According to a second aspect, the invention provides an error detection and correction system according to either previous claim comprising further decoding each partitioned field in accordance with a cyclic redundancy code (CRC) generator polynomial f[g(x)] which is a factor of the EDAC code generator polynomial g(x).

An error detection and correction system embodying the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure lisa block diagram of an EDAC system in a typical operating environment.

Figure 2 shows a prior art EDAC encoder.

Figure 3 shows a prior art EDAC decoder.

Figure 4 shows an EDAC system embodying the present invention.

An error detection and correction system is illustrated in Figure 1. Information from a data source 1 is fed to an EDAC system 2 which, in accordance with a selected code generator polynomial g(x), complements the incoming data by the addition of coded check bits which may later be decoded to determine whether an error has crept into the data.

From the EDAC system, the coded data may be output directly to a user device or provide the input to a storage or transmission device. In either case, the device to which the data is input may provide for error detection. This may assume either or both parity check and a check against a cyclic redundancy code. If an error is detected at this time, a request for retransmission of the data would be made.

If the data has been placed in a storage device such as indicated by 3, retrieval of the data will be via the same EDAC system which provided the original coding, or a similar system utilizing the same generator polynomial, g(x), as the original coding system used. In passing through the EDAC system, the output of the stored data will be checked to confirm that no errors have been incorporated into the data as a result of defects within the storage device or noise in transiting the interface between the storage device 3 and the EDAC system 2. If an error is detected within the EDAC system 2, it will be corrected therein and the corrected data output to a user device such as indicated by 4 Figure 1.To detect the presence of errors introduced in traversing the interface between the EDAC system and the user device a CRC and a parity check may be performed and a request for a retransmission of the data made if an error is detected.

An encoder for generating code check bits in accordance with the polynomial g(x) X3 + X + 1 is illustrated in Figure 2a. This hardware embodiment of a cyclic code generator utilizes a linear feedback shift register.

Since cyclic code encoders and decoders are well known in the prior art, the discussion of them, as illustrated in Figures 2 and 3 respectively, will be somewhat cursory, being set out here primarily to place the invention in context.

In general, an encoder or decoder for use with a cyclic code will use linear feedback shift registers comprised of a number of flip-flops, as determined by the degree of the code generator polynomial employed, and will contain feedback paths to those flip-flops corresponding to the terms of the selected code polynomial. Thus, for the generator polynomial g(x) selected to illustrate Figures 2 and 3, the linear feedback shift register is comprised of three flip-flops since the polynomial, g(x), is of degree of three.

Feedback through Exclusive OR circuits is shown to flip-flops corresponding to the terms X1 and XO in the polynomial g(x).

Referring specifically to the encoder of Figure 2A, theinformation word l(x) comprising information sequence 1101 is input to the encoder through Exclusive OR 5 and is simultaneously fed to OR gate 6. While the code checkbits are being generated, switch S1 is in the closed position and switch S2 is open. The information word l(x) is thus being output through OR gate 6 at the same time that the encoder check bits are being generated. The table of Figure 2B illustrates, step by step, the sequencing of the linear feedback shift register flip flops XO, Xa, and X2 as the information sequence flows through the encoder.

As the last bit of information enters the encoder through OR gate 5 and switch S1, the register contents are as illustrated in the bottom line of Figure 2B. The code check bits thus indicated are 001. At this time switch S1 is opened and switch S2 is closed. The contents of the linear feedback shift register is then clocked out through switch S2 and OR gate 6 to join the information stream l(x) at the output to form code word F(x). The code word F(x) contains both the information sequence 1101 and the check bit sequence 001, as indicated in Figure 2A.

A decoder for use with code words generated by the encoder of Figure 2A is illustrated in Figure 3A. As may be seen, the hardware implementation of a decoder is essentially the same as that of the encoder with the addition of buffer register 7. It takes but little thought to realize that the same hardware may be implemented and utilized for both encoding and decoding within a given EDAC system. In practice, such implementation is frequently employed. To illustrate the function of the decode and of its error correcting capabilities, it is here assumed that the code word F(x) was transmitted, but the word received at the input to the decoder is the word H(x), comprised of the code word F(x) and an error E(x). Specifically it is assumed that the code word transmitted was 1101001 and the word received 11 11001.

The received word is input to buffer register 7 and simultaneously through OR gate 8 to the decoder.

Figure 3B illustrates the step by step sequencing of the linear feedback shift registerflip-flops. As the least significant bit of the received word enters the decoder, the decoder contents, 001, are denoted as the "Error Syndrome". This implies that an error is present in the received word. Were the error syndrome to be all zeroes, that is 000, the implication would be that there was no error contained within the word Since the error syndrome is not all zero, the EDAC system will go into its error correction mode.

Coincident with the derivation of the error syndrome, the received word H(x) has been stored in buffer register 7. Upon recognition of a non-zero syndrome, a sequence of logical 0 inputs is injected into the decoder input. With each zero input of the correction process, one bit of the word stored within buffer register 7 is gated out. Each time a zero is input, the contents of the flip-flops are also checked until all but the most sigificant bit is zero. At that time switch S3 is opened and switch S4 is closed. The contents of buffer register 7 and the linear feedback shift register, comprised of the three flip flops XO, X1, and X2, are simultaneously gated out to Exclusive OR gate 9. The output of OR gate 9 is the corrected code word F(x).

This sequence is shown, step by step, in the lower portion of the table illustrated in Figure 3B. The Peterson text, noted earlier herein, may be referred to for more detailed background in the operation of linear feedback shift registers for encoding, checking and error correction purposes.

The present system makes use of encoder and decoder circuitry well known in the prior art, but utilizes them in a manner which provides benefits not previously realized in DAC systems. In the present system, the requirement to correct burst errors of length four and to detect without miscorrection 100% of the errors of length sixteen or less will be assumed. A burst-error detection-and-correction system is concerned with errors which occur within any given length span of bits within a code word. For example, if the EDAC system is designed around a sixteen-bit-length burst error; it will detect errors in one or more bits within a span of sixteen bits. The bits in error need not be consecutive bits, i.e., the first and last bit may be in error within any given span of sixteen bits, while those bits in between the erroneous bits may or may not be correct.

Burst errors are usually associated with surface defects in disk memories or tape storage devices, or may be derived from atmospheric transmission of data or long line transfers thereof. Fire Codes are in the family of cyclic codes and provide simple-to-implement burst error correction utilizing the encoder and decoder circuitry described above. The discussion herein will assume the use of a Fire Code.

In Figure 4the internal features of EDAC system 2 of Figure 1 are set forth. The binary word l(x) is input to EDAC system 2 from the data source through interface 10. In addition to supplying the necessary interface between the data source and EDAC system 2, interface 10 provides the means for partitioning the data fields of the incoming word l(x). The odd positioned data bits of l(x) are fed to EDAC encoder 11, while the even position bits are input to EDAC encoder 12. Following the generation of the code check bits in each encoder, 11 and 12, the odd and even coded data bits are reassembled by interleaving within interface 13 and output as the code word F(x) to the storage or transmission device associated with EDAC system 2. The partitioning and interleaving of data fields is well known in the prior art. Such partitioning is often done when the data transfer rate exceeds the available clock rate of the EDAC hardware. However, for the purposes of the teachings herein, the fields are partitioned and separately encoded for purposes of reducing of miscorrection errors to minimal levels.

One of the criteria for selecting a code generator polynomial, g(x), is the establishment of the bounds of the error detection capability of the EDAC system. When it is said that a system will detect errors of length sixteen bits or less, it is meant that it will detect 100% of such errors without causing a miscorrection. In practice, such a system may be capable of detecting errors of three, or four, or more times greater length.

However, in such cases, the possibility of miscorrection exists. In establishing the 100% detection-withoutmiscorrection bound, the designer does so based on the statistical probability that burst errors of such length are highly improbable. Thus, run-of-the-mill errors will always be detected without miscorrection.

Nevertheless, it is an awareness of the atypical error burst which frequently causes the EDAC system designer to over-design the system circuitry and provide complex encoders and decoders which produce error code check bits far in excess of that which may be efficiently utilized by the overall system.

By partitioning the data field bits, the present system provides for an error detection and correction system of less complexity which makes more efficient use of storage capacity and conserves processing time in the devices associated with the EDAC system. For example, in the system under discussion the prior art techniques might well call for an EDAC system capable of 100% detection-without-miscorrection of error bursts in excess of sixteen bits in order to avoid miscorrection of the atypical burst error. As will be seen, such over-design is not required with the present system.

Referring again to Figure 4, coded data enters interface 14 as the word H(x). The word H(x) may be considered to comprise the original coded information F(x) plus an error E(x). Interface 14 provides a direct output to buffer register 15 and a partitioned output to even-bit-position decoder 16 and to odd-bit-position decoder 17. Buffer register 15 is implemented to serve the purposes described with respect to buffer register 17 in the discussion of Figure 3A, except here buffer 15 services both decoders 16 and 17. While decoders 16 and 17 are acting to derive an error syndrome on the partitioned field data provided to each, the even and odd bit information is being made available, on lines 18 and 19 respectively, to their respective correction logic blocks, 20 and 21.The odd field bits are output on line 23 from correction logic block 21, while the even partitioned bits are output on line 22 from correction logic block 20. Lines 22 and 23 provide the inputs to interface 24, wherein the even and odd bit information is interleaved and output to the User Device.

In the course of the operations just described, word H(x) is preserved in buffer register 15, although the input word H(x) is made immediately available to the User Device. This latter arrangement provides the User Device- with immediate access to the input word H(x), so that there need be no delay in utilizing the data if the error term E(x) is equal to zero. Should either or both of decoders 16 and 17 detect an error in input word H(x), the User Device will be alerted and instructed to ignore the erroneous input and await receipt of the corrected information.

As the data are output from correction logic block 32 along line 23, they are subjected to CRC check 25.

Check circuit 25 provides a backup for the EDAC decoder and provides a self-check of the EDAC system itself including buffer 15. CRC check circuitry 26 serves identical purposes with respect to the even position bit data on line 22.

In addition, as previously mentioned, it is assumed that the storage and transmission devices, as well as all other user devices associated with the EDAC system, will provide for parity and CRC checks of the data input to such devices. Failure to pass a parity or a CRC check will cause a fault indication and require a retransmission of the data word.

Should either of decoders 16 or 17 detect an error, the User Device will be immediately notified and the EDAC system will go into the error correction mode. If the error syndrome derived in the decoder indicates a correctable error, the operation will be in accord with that previously set forth in the description accompanying Figure 3B. The output of buffer register 15 and the correction code output from decoder 16 or 17 will be combined within their respective logic circuitry, 20 or 21, and the corrected word will output on lines 22 or 23, respectively.

If the error syndrome derived indicates that the fault is not correctable, correction logic circuit, 20 or 21, will indicate a fault, and a retransmission of data word H(x) will be initiated.

In a conventional EDAC system capable of correcting burst errors of length four and of detecting-withoutmiscorrection burst errors of length sixteen, it is likely that a Fire- Code polynomial of degree forty-eight might be utilized. This would require the use of linear feedback shift registers having forty-eight flip-flops. By partitioning the data into even and odd field bits, it is possible to use encoder and decoder circuitry designed around a Fire Code generator polynomia, g(x), of degree twenty4our, requiring only twenty-four flip-flops in the associated linear feedback shift registers.Further, while the probability of making a miscorrection with the non-partitioned prior art system would, in all likelihood, be much less than unity, the probability of miscorrecting in a partitioned system is approximately the square of the miscorrection probability of the older, non-partitioned EDAC system, thus reducing that probability drastically. With the partitioned EDAC system taught here, both decoders must output acceptable code words upon receipt of non-correctable error data to effect a miscorrection. The probability of doing so with dual decoder systems is virtually nil. It is thus seen that partitioning the fields within the EDAC system results in the need for less complicated encoder and decoder circuitry, and greatly reduces the probability of making a miscorrection.

It may be further noted that, although reference has been repeatedly made to CRC checks being performed within the EDAC system, as well as at the various devices associated with that system, there has been no indication made in the discussion herein, not in the associated drawings, of any CRC encoder devices. In prior art systems it was necessary to provide separate encoder circuitry to allow the performance of CRC checks. The code word required EDAC check bits plus additional CRC check bits. The present system obviates the need for CRC encoder circuitry, as well as eliminating the need for extending the length of the code word and expending the time and storage capacity to handle such an extended code word.

In Figure 4, the notation g(x) will be found alongside encoders 11 and 12 and decoders 16 and 17. This indicates that all these devices are related by their use of the same Fire Code generator polynomial, g(x). The relationship of the CRC check circuits 27 and 28 is indicated by the notation: f[g(x)]. This notation indicates that the code used for the CRC check is a factor of code polynomial g(x) used to generate the Fire Code check bits. It is a characteristic of cyclic codes, of which the Fire Codes represent one example, that polynomials which are factors of the selected generator code polynomial are themselves legitimate code polynomials.

Thus, if a cyclic redundancy code (CRC) polynomial is selected which is a factor of the selected Fire Code polynomial, a CRC check may be successfully performed on code words encoded by the use of the Fire Code generator polynomial alone. To illustrate the applicability of this concept assume that a Fire Code geerator polynomial, g(x)=(X15+X14+X13+X12+X11 +X3+X2+X+ 1 )(X9+ 1), is selected for use in the EDAC system of Figure 4. It may be easily shown that this expression may be rewritten as: g(x)=(X8+X7+X6+X5+X4+X3+X+ 1 )(X16+X11 +X4+ 1).

The indicated additions are performed modulo two. Referral to the previously referenced Peterson text will show that g(x), as first written above, is a recognized Fire Code, while the expression in the rightmost parenthesis of the second writing of g(x) above is a recognized CRC code. Thus, the particular g(x) indicated may be used to provide the EDAC Fire Codes as well as the means necessary to perform a CRC check.

The illustration above exemplifies good design techniques in practicing the methodology espoused herein, since the particular CRC polynomial, X1'+X"+X4+1, is specifically available for implementation using a commercial integrated circuit chip. Because many of the devices associated with the EDAC system will employ buffer registers at their input, the simple addition of one such IC chip at the input to the device will provide the means for performing a CRC check of the incoming data. The encoder and decoder for use with the Fire Code itself may be implemented using other integrated circuit chips.

The present system shows that partitioning the fields of an incoming data word may be utilized in an error detection and correction system to drastically reduce the probability of making a miscorrection in the received data word, H(x). There may be used cyclic codes for error detection and correction which have as a factor of the code generator polynomial a CRC code polynomial such that no additional encoding circuit is required to permit the performance of CRC checks on the coded data words.

The example has been here given in terms of odd/even partitioning but it should be remembered that other partitioning schemes may be used to advantage, e.g. partitioning every third or fourth bit and using three or four encoders and decoders would further enhance the system's ability to avoid miscorrection.

The system disclosed provides the means for a simple maintenance test check of the system. If a test code word is made up of alternate sets of paired ones and paired zeroes, the partitioned field will be identical.

Comparison of the fields and identification of problems is then relatively simple.

As a modification, the partitioned fields may be coded and then transmitted to the decoder without transiting the intermediate interleaving and repartitioning apparatus.

Claims (5)

1. An error detection and correction system comprising: partitioning a data word into at least two interleaved fields; encoding each partitioned field in accordance with a selected EDAC code generator polynomial; decoding each of the partitioned fields in accordance with the polynomial to provide an error syndrome; correcting the partitioned fields in accordance with the error syndromes; and interleaving the corrected partitioned fields to reproduce the data word.

2. An error detection and correction system according to Claim 1 wherein the encoded partitioned fields are interleaved to produce a coded data word and the coded data word is partitioned prior to decoding.

3. An error detection and correction system according to either previous claim comprising further decoding each partitioned field in accordance with a cyclic redundancy code (CRC) generator polynomial f[g(x)] which is a factor of the EDAC code generator polynomial g(x).

4. An error detection and correction system comprising: a) encoding data words with coded check bits derived in accordance with a selected cyclic error detection and correction (EDAC) code generator polynomial g(x); b) decoding the encoded data words in accordance with the polynomial g(x) to provide an error syndrome for error detection and correction purposes; c) fu dcoding the encoded data words in accordance with a cyclic redundancy code (CRC) generator polynomial f[g(x)j which is a factor of the polynomial g(x) to give supplementary error detection of the encoded data words.

5. An error detection and correction system substantially as herein described with reference to Figure 4.