GB2042846A - Secret television - Google Patents

Abstract

A composite signal including an information portion and a synchronisation pulse is encoded by a random signal generator which varies the level of the synchronisation pulse. The coded composite signal is transmitted together with a signal representing the random signal and a receiver uses the received random signal to decode the received composite signal. A receiver without a decoder will not be able to synchronise the information portions. The information portions themselves may also be encoded by inverting the composite signal during successive information portions for alternate periods whose length depends on said random signal.

Description

SPECIFICATION Encoding of information This invention relates to encoding a television signal, and it is also concerned with the transmission of such an encoded signal, and the reception and decoding of such a signal.

Coding of information is required when it is desired to restrict the reception of the information in intelligible form to certain recipients, for example the subscribers to a television service.

In co-pending application 48.79/77 there is described a coding arrangement in which random groups of information-bearing portions of lines are inverted, and in which the accompanying audio information is coded by conversion of the audio signal to digital form. The present invention is an improvement of the earlier coding system.

According to one aspect of the invention there is provided encoding apparatus for encoding a composite signal including an information portion and a synchronisation pulse, the apparatus comprising a random signal generator and means for varying the level of the synchronisation pulse in response to said random signal. Further encoding may be achieved, as described in the copending application, by providing means for encoding the information portion said means comprising means for inverting the signal during successive information portions for alternate periods whose length depends on said random signal.

The invention also includes transmitting apparatus for transmitting the composite signal encoded as described above, and the invention may also inciude receiving apparatus for receiving the transmitted signal and decoding the received signal to provide a composite signal restored to its original form.

An example of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a block diagram of an encoder for use with a transmitter of a composite video signal, Figure 2 is a block diagram of a receiver for use with the apparatus of Figure 1.

Figures 3 and 4 represent waveforms appearing respectively in the apparatus of Figures 1 and 2, and Figure 5 is a detail of the apparatus of Figure 1.

As shown in Figure 3, wave form C1 shows five line periods of a composite video signal. Each line period comprises an initial negative-going DC line synchronisation pulse, a short synchronising burst of high frequency signals and a period of positive going amplitude modulated carrier wave signals representing the video information in the line. The signals representing the video information are shown to have a saw-tooth envelope, but in practice will have an irregular envelope. The composite waveform is related to ground potential in that the negative extreme potential of the linesync pulse and the maximum possible potential of the video signal are equal and opposite.

For the encoding process to be described it is convenient if the whole composite video signal is of single polarity. The signal is therefore applied to a distribution amplifier 11 (Figure 1) and a signal from a DC level inserter circuit 51 is applied on line 52 to the amplifier 11 to shift the whole composite signal to positive polarity, as shown at waveform C2.

The amplifier 11 has a second output at which the unshifted amplified composite video signal appears and which is connected through a low pass filter 12 to a synchronisation separator circuit 1 3. This circuit produces an output to a line synchronisation separator circuit 14 which separates out the initial negative-going DC pulse of the composite signal, and an output to a field integrator 1 5 which produces a signal representing field synchronisation pulses of the vertical blanking period at the beginning of a field.

Since the line and field pulses produced do not occur right at the beginning of the lines and fields respectively, delay circuits 16, 1 7 are included after respective circuits 14 and 1 5 producing an output exactly at the start of the next line and field, the delays being slightly less than one line and one field period respectively. The output of the circuit 1 6 is shown at waveform C3. Each pulse occurs accurately at the beginning of a line, whereas the input signal derived from the line synchronisation pulses of waveforms C1 and C2 are slightly delayed at the beginning of the line.

Connected to the line delay circuit 1 6 is line chop pulse generator 1 8 which responds to the output pulse at the start of a line and produces a chop pulse during the video period of the composite line signal which is applied to one input of an AND gate 21. The chop pulse does not occur during the time sync or sync burst periods. Similarly, a vertical chop pulse generator 19 responds to the output of the field delay circuit 1 7 at the start of a field to produce a signal starting at the end of each AND gate 21. The AND gate 21 will therefore produce a signal except during the horizontal and field synchronisation periods, i.e. the signal is produced during the period available for video information in every line.

Pulses at field frequency produced by the field integrator 1 5 are applieci to a random number generator 22. On the receipt of an input pulse, the number generator 22 generates a random binary number on parallel output lines which are connected firstly to a divide-by-N counter 23 (which can be a logic unit SN 74193) and secondly to a parallel to serial converter 24 which converts the signals on the parallel lines into a train of pulses representing the random number generated and the train of pulses is applied to a data processor 25 to be discussed below. The divide-by-N counter 23 is fed with signals occurring at line frequency (waveform C7) from the line synchronisation separator 14 and is a special form of shift register.The counter is arranged to respond to only the Nth pulse received on its data input line 26 and to forward the counted pulses (waveform C8) to a flip-flop 29 whose output (waveform C9) energises an input of AND gate 31 between alternate sets of N line pulses. The value of N is the random number generated for each field. The output of the vertical chop pulse generator 1 9 also operates a data inhibit gate 32 whose output continues after the vertical chop pulse for the period of the first few lines of the field which are to be used for transmitting data. The output of gate 32 is connected to the other input of the AND gate 31 so that the AND gate only produces an output alternating every N lines other than during the vertical blanking and data periods. The output of the AND gate 31 is applied to one input of AND gate 33.The other input of AND gate 33 is connected to the output of AND gate 21. The AND gate 33 is therefore enabled during alternate N line pulse periods except during the horizontal and the vertical blanking periods. The output of AND gate 33 causes complementary actuation of two analog transmission gates 35 and 36, the connection to gate 36 being through an inverter 58.

AND gate 34 has one input connected to the field integrator 1 5 and the other input connected to a line from the random number generator 22 to the converter 24. This line is also connected through a programmable counter 59 to an audio coding unit 61 as described in co-pending application 7905930. The gate 34 thus produces an output at certain of the vertical synchronisation periods according to the presence or absence of a digit in the random number generated and this output is applied to the vertical synchronisation scrambler 53 to shift the level of certain vertical synchronisation periods according to a digit of random number generated for that field. When the sync pulsed in the transmitted signal are shifted, a receiver cannot respond to them and will be unable to synchronise the frame.

When the pulses are not shifted, a receiver will synchronise itself as usual. Waveform Dl (Fig. 4) shows the vertical blanking period including the fly back period of five negative-going pulses, the vertical synchronising period of five positivegoing pulses and an equalisation period of five negative-going pulses. Waveform D2 shows the vertical synchronisation period shifted by a positive voltage by AND gate 34.

The outputs of the line synchronisation separator 14 and of the field integrator 1 5 are also applied to a synchronisation processor 62 connected to a clock pulse generator 63. The clock pulse generator output is also applied to the converter 24 and the data processor 25. The processor 62 shapes the line and field synchronisation signals with the assistance of the clock pulses and feeds the shaped signals to the converter 24 and a line selector and coding starter 37. The starter 37 is fed with the output of a zero time reference generator 38 activated by the output of field integrator 15 to signal the beginning of a field, and provides an output to a data insertion unit 56 during selected lines of a field during which lines data (as distinct from video information) is to be transmitted.The data information is assembled in the parallel to serial converter 24 in the form of a train of binary signals representing in turn the random number generated by 22, the subscriber's identity data (e.g. the state of his account) and the billing data (e.g. the rate at which the programme is to be charged). The processor 25 converts the binary signals into biphase signals and feeds them to the data insertion unit 56. The starter 37 also resets the counter 23 at the end of each field to be ready for a new value of N generated by 22 for the next field.

The composite video signal amplified by the distribution amplifier 11 and shifted in level by the circuit 51 passes to the vertical synchronisation scrambling circuit 53 which is enabled in response to the output of AND gate 34 to shift the DC level of the vertical synchronisation signal in a random manner depending on the random number generated. The output of the shifting circuit 53 is supplied to a phase splitter 54 which provides two signals of equal and opposite polarity which ale fed through complementary analog transmission gates 35 and 36 whose outputs are combined in an adding circuit 55 and connected through the data insertion circuit 56 to a modulator 57. The analog transmission gates 35 and 36 are enabled alternately by signals connected respectively directly to the output of AND gate 33 and through inverter 58 to the output of the AND gate 33.Thus during the video periods of certain lines as selected by the random generator 22, the polarity of the transmitted signal will be reversed. The horizontal synchronisation pulses are unaffected since the line chop pulse generated by 1 8 only starts at the beginning of the video period. the outputs from the gates 35 and 36 combined in the adding circuit 55 are combined with the output of the data processor 25 during the times selected by the starter 37 in the data insertion circuit 56 which is then used to modulate a carrier signal in the modulator 57. The modulator 57 is also fed with two channels of coded audio information by a coder 61 fed from the converter controlled by the random number generator 22 as described in copending application 7905930.

Waveform C2 shows five line periods of the composite video signal, non-inverted, as applied to gate 35. Waveform C4 shows the same five lines periods inverted as applied to gate 36.

Waveform C5 shows the switching pulses applied to gate 35, causing gate 35 to transmit the first, fourth and fifth lines compietely and the line synchronising periods of the second and third lines. During the negative going periods of the switching pulses, gate 36 is enabled by inverter video signal is transmitted for the second and third lines. The signal combined by adder 55 is shown at waveform C6.

The composite video signal is thus encoded in two ways. The vertical synchronisation DC level is shifted in random manner by the circuit 53, and certain groups of video information are reversed in polarity according to the random number generated by 22 for each field. A receiver which was not fitted with a matching decoder would produce a picture which "rolled" since the vertical hold circuits in such a receiver could not use the shifted vertical synchronisation pulses to synchronise the field of the receiver picture.

Furthermore, alternate groups of lines would appear distorted due to the inversion of the video signal and the width of these groups would change in each field so that no part of the picture would be likely to remain undistorted long enough to be enjoyed by the viewer. The random number is generated anew for each field so that the change in the line group pattern occurs generally at 50 or 60 hertz.

The modulator 57 feeds a transmitter not shown, and the coded signals are received in a receiver as shown in Figure 2.

Figure 5 shows some components of Figure 1 in greater detail. The distribution amplifier 11 comprises a field effect transistor TR 1 to whose gate the composite video input is applied. An additional DC level is added to the composite video input from switch S3 under the control of a signal from the line sync separator 14 on line 52.

The amplified signal appears across a load resistor ofTR1.

The output of gate 34 is applied to the base transistorTR2 in the scrambler 53 which also comprises two switches S4 and S5. When a signal is received from gate 34, S4 and S5 close and add the positive potential pulse from 34 to the input of the phase splitter 54 (an operational amplifier) in order to effect the DC common mode balance in the vertical sync pulse period. The vertical scrambled composite video signal is passed through the phase splitter 54 to the switches S1 and S2 forming gates 35, 36 respectively. The outputs of the switches S1 and S2 are added by the grounded resistor forming the adder 55 and passes to the data insertion circuit 56.

The received signal is fed through a tuner 101, intermediate frequency amplifier 102 to separate sound and video signal detectors 103 and 104.

The decoding of the sound signals is described in co-pending application No. 7905930. The detected video signal is applied from 104 to a distribution amplifier 105 and also to a low pass filter 106 and a synchronisation separator circuit 107 whose output is shown at waveform Do. A delay circuit 114 applies a delay of almost one line period to the output of the separator 107, in a similar manner to the circuit 16 of Figure 1, and a horizontal chop pulse generator is connected to the circuit 114 to generate horizontal chop pulses (waveform D3) to cover the whole line period except for the video information period.The output of the circuit 11 4 is applied through a DC level inserter circuit 11 7 to adjust the level of the received composite video signal to compensate for the shift of potential applied by circuit 51. The adjusted signal is applied through a vertical sync unscrambler 109 to a phase splitter 143.

Since the encoded signal has certain vertical synchronisation periods shifted in DC level (see waveform D2), the output of the synchronisation separator circuit 107 will occasionally be blank since it will not respond to shifted pulses (see waveform D4), and a missing vertical synchronisation detector 108 is used to detect these blank periods and to reconstitute the vertical synchronising pulses missed (see waveform D5).

The reconstituted vertical sync pulses are fed through a line drive generator 123 to a preset line selector 122 which selects the same lines after the beginning of the field as those selected by 37 in the encoder for response to data signals, by enabling a data gate 111 which connects the output of the distribution amplifier 105 to a data processor 124 which converts the biphase data in the composite video signal to ordinary binary signals. The data lines of the signal have not been inverted, since gate 32 inhibits gates 31 and 33 during the selected data period. The data processor 124 feeds a serial to parallel converter 125 which produces decoding data, billing data and subscriber identity data.The decoding data represents the random number in parallel form corresponding to the output of the converter 24 in the encoder, and this is latched in a latch 126 and caused to operate a divide-by-N counter 1 27 which is also fed with the output of the synchronisation separator 107 to synchronise its counting with the lines of the picture. The selector 122 enables a programmed decoding starter circuit 112 to enable the counter 127 after completion of the data period, thus producing an output every N lines, which output is fed to a flipflop 128 which enables an AND gate 129 for alternate periods of N lines.The other input of the AND gate 1 29 is fed from a vertical chop pulse generator 119 described below, and the output of the AND gate 129 passes to an input of an AND gate 1 35 through a gate 131, the other input of the AND gate 135 being supplied by the output of the AND gate 121.

An equalisation pulse detector 1 52 is fed with the output (waveform D1) of the sync separator 107 and with the output (waveform D3) of the horizontal chop pulse generator 11 8. During the vertical blanking period, there will be some sync pulses not chopped out by the chop pulses, and these (waveform D6) are applied to a wide vertical pulse generator 1 53 the leading edge of whose output (waveform D7) is delayed in a time delay 1 54 (to allow for the fly back period) to generate in generator 1 55 a vertical sync shift pulse (waveform D8) to correct the level of the vertical sync singals in the composite video signal in the unscrambler 109. This shift of the sync signals is only required when the received signal contains shifter vertical sync signals and the generator 1 55 is disabled by a signal representing the random number from the converter 125 when the shift pulse of waveform D8 is unnecessary. The regenerator 153, the time delay 1 54 and the pulse generator 1 55 may all comprise monostable vibrators.

When the vertical sync signals are missing from the output of the sync separator 107, their absence will be sensed by the detector 108 and regenerated by that circuit. When they are present (ie when the scrambler 53 was not actuated), they are integrated in an integrator 1 56. An OR gate 1 57 is connected to the outputs of the regenerator 108 and the integrator 1 56 so that its output will always represent the vertical sync pulses, which are applied through a delay circuit 11 5 giving a delay of almost one field (corresponding to the circuit 17 of Figure 1) to a vertical chop pulse generator 119. The outputs of the generators 11 8 and 11 9 (waveforms D3 and D9 respectively) are applied through an AND gate 121 to the other input of AND gate 135.

Each subscriber has a magnetic card 132 which is placed in a card reader 133 and the reader output is compared in a card data comparator 134 with the subscriber identity data from the converter 125.

Provided that the identity of the subscriber on his card does not match the list of unacceptable subscribers received from the transmitter, the gate 131 is enabled to pass the decoding data to the first input of gate 135, and the gate 131 also passes the billing data from the converter 125 to a card recorder 136 which acts on the magnetic card 132 to record on the card the charge to be made for the programme being watched. At intervals, the card 1 32 is processed to establish the charge to be paid by the subscriber for the reception service.

The output of the AND gate 135 operates complementary gates 141 and 142 supplied by the phase splitter 143 which receives the output of vertical sync unscrambler. The gate 141 is fed directly from the output of the AND gate 135, and the gate 142 through an inverter 144 from the output of the AND gate 135, so that the gates 141 and 142 are enabled alternately.The adder 145 which receives the outputs of gates 141 and 142 has both the video information restored to its original polarity and level and the vertical synchronisation signals restored to their original level, and this is fed to a modulator 149 in which the standard carrier signal is modulated with the decoded audio signals from the audio decoding circuit indicated generally at 1 51 supplied with decoding data from the converter 125 and coded audio signals on two channels from the sound detector 103 in a manner as described in copending application No. 7905930. The output of the modulator 149 is then applied to the standard television receiving antenna input. The decoder 1 51 produces an audio output on a second channel which is used as desired.

Various modifications will occur to the skilled reader. For example, the complementary operation of a pair of gates can be achieved by connecting them to respective outputs of a flip-flop rather than connecting one directly to an actuating signal and the other through an inverter to the actuating signal as described above.

Claims (8)

1. Encoding apparatus for encoding a composite signal including an information portion and a synchronisation pulse, the apparatus comprising a random signal generator and means for varying the level of the synchronisation pulse in response to said random signal.

2. Apparatus as claimed in claim 1 further comprising means for encoding the information portion, said means comprising means for inverting the signal during successive information portions for alternate periods whose length depends on said random signal.

3. Apparatus as claimed in claim 1 or claim 2 wherein the random signal generator is a random number generator, said varying means operating at a frequency dependent upon the random number.

4. Apparatus as claimed in claim 3 wherein the composite signal represents a succession of fields, the generator being arranged to generate a random number for each field.

5. Apparatus as claimed in claim 4 wherein the fields contain lines, the varying means operating after every said random number of lines.

6. Encoding apparatus substantially as hereinbefore described with reference to and-as illustrated in Figure 1 of the accompanying drawings.

7. Transmitting apparatus comprising encoding apparatus as claimed in any one of the preceding claims and means for transmitting said encoded composite signal together with a representation of said random signal.

8. Receiving apparatus for receiving a signal from transmitting apparatus as claimed in claim 7 comprising means for restoring the received signal to the original form of the composite signal in response to the received representation of said random signal.