GB2041707A - Arrangement for distribution of television games and the like - Google Patents

Abstract

An ensemble of video game controlling programs are multiplexed (e.g., on a time division, word-interleaved basis) and distributed over a common communications link 11, e.g., a CATV cable. Each authorized TV user thereto connected has an adapter with a read/ write (RAM) memory 59. A particular game specified on an input device, e.g. a keyboard 42, selects the words of the game program listing for reception and loading into the RAM. Once loaded, the RAM causes the microprocessor controlled unit 30 to execute the selected game with operator participation in a per se conventional fashion, communicating with the TV receiver 67 via a modulator 44 feeding the aerial socket. For a new game the input device is changed to replace the adapter RAM contents with the instruction set for the new game. <IMAGE>

Description

SPECIFICATION Improved system arrangement for distribution of television games and the like Disclosure of the invention This invention relates to electronic video games and, more specifically, to a communications system and terminal equipment permitting subscribers at diverse receiving stations to select, receive/load and execute a desired one of an ensemble of video games or the like.

Electronic video games are now a matter of common experience. One class of such games involves "hitting" and "hit" spots traversing across the face of a television cathode ray tube in accordance with a set of rules to simulate contests such as ping pong, tennis, hockey and so forth. As used herein, "video games" is used generically for all such sports - as well as informational diplays and other presentations of interest, dynamic and/or static, which may be developed on a user's television set Such video games typically have user controls for at least a portion of the display (e.g., to control paddle/racket position for ping pong/tennis), game controlling electronics, television master synchronizing signal generating circuitry, and a modulator to generate an output signal spectrum corresponding to a VHF television channel to permit reception and display bys standard television receiver.

The "game" rule implementation is of two general forms. First in time was the dedicated, special purpose "hardware" approach, pursuant to which special purpose circuitry was built to perform one or, at best, a fixed and iimited repertory of games. The other, "software" approach utilizes a microprocessor player which is controlled by a read only memory (ROM) having stored therein a program containing the rules of one (or several) games. In this software approach, games can be changed by simply replacing a ROM of a player with another ROM loaded with different microporcessorcontrolling programming to implement the rules and constraints of a different game.

It is an object of the present invention to provide improved video game program distribution/user terminal equipment apparatus.

More specifically, it is an object of the present invention to permit each subscriber station connected to a common communications medium (e.g., a community antenna television (CATS) coaxial cable network) to load a desired one of an ensemble of game-controlling program listings; and to thereafter execute the "game" of the selected program.

The above and other objects of the present invention are realized in a specific, illustrative system arrangement wherein an ensemble of video game controlling programs are multiplexed (e.g., on a time division, work-interleaved basis) and distributed over a common communications link, e.g., a CATV cable. Each authorised user station connected to the cable has an adapter with a read/write (RAM) memory disposed between a stored program controlled video game player and the cable.

A particular game specified at an input device of the user station selects the corresponding game program listing for reception and loading into the adapter RAM. Once loaded, the RAM causes the microprocessor controlled player to execute the selected game in a perse conventional fashion.

When a new game is desired, the input device setting is changed to appropriately replace the adapter RAM contents with the program listing for the new game.

The above and other features and advantages of the present invention will become more clear from the following detailed description of a specific embodiment thereof, presented hereinbelow in conjunction with the accompanying drawing, in which: Figure lisa block diagram depicting specific television game program distribution, reception and utilization apparatus of the present invention; and Figure2 is a flow chart characterizing operation of a program controlled central processing unit 32 included in the Figure 1 embodiment.

Referring nowto Figure 1, there is schematically shown an improved system arrangement for distributing an ensemble of television signals which includes as a part thereof, program listings for implementing a plurality of television games. Again as stated hereinabove, the expression "television games" is used generically, and includes all simulated sports contests, informational displays, and any passive or interactive presentation of interest. In overview, a system head end or common station 10 is employed to generate and disseminate an ensemble of radio frequency signals, typically including a plurality of television programs (at VHF and/or mid, sub or super band).There is further included one frequency band including a program instruction carrier modulated with digital information corresponding to the program instruction sets for a plurality of stored program microprocessor controlled video games. Any communication link may be employed. Thus, for example, the head end 10 may be connected to an array of subscriber stations 12 (a representative one being shown in detail) via a common coaxial cable 11, e.g., a community antenna television (CATV) or master antenna television (MATV) cable.

The program instruction sets may be modulated and multiplexed onto the cable 11 in any of numerous ways perse well known those skilled in the art. For concreteness, it will be assumed for specificity and not limitation, that the instruction sets for the ensemble of games modulate the program carrier in a time division interleaved fashion, with the words of successive game instruction sets serially following one another. That is, the plural bits forming one digital instruction (or one byte thereof) for one program serially modulate the carrier, followed by the next-in-order instruction from the next program listing and so forth. This repetitively continues until all instructions of all program sets have been transmitted, whereupon the entire transmission cycle repeats.By way of further illustrative particular formatting for the game program information transmitted at the beginning of an instruction cycle the head end 10 sends a sequence of binary zero words (e.g., arbitrarily, fifteen in number), followed in turn by a digital word specifying the number of program instruction sets to be transmitted; any other desirable administrative header information; finally and principally followed by the time division multiplexed interleaved instruction sets themselves and any desired message terminating words. It is assumed that the transmitted binary information includes a modulating process with an embedded clock, i.e., where bit (digit) timing may be recovered from the received digital wave itself. Embedded clock modulated schemes are perse well known to those skilled in the art, e.g., including a transition each bit-time.Any other manner of obtaining bit synchronization between head end and each receiver loca tion,persewell known, may alternatively be employed. Still in overview each subscriber station 12 connected via cable 11 to the head end 10, e.g., the illustrative station 12 shown in detail, includes adapter or interface apparatus connected to a perse known microprocessor (or other stored program computing element) controlled video game player 30. More specifically, the adapter 12 apparatus includes a read/write (RAM) memory 59 which stores the video game program instruction set desired for the subject station as signalled by a user via an input source 42, e.g., a keyboard, thumb wheel switch or the like. A read only memory (ROM) 57 contains the fixed executive program for controlling RAM loading.

In general terms, the adapter apparatus 12 receives the incoming video game program listing information under central processing unit (CPU) 32 control. Of the ensemble of consecutive, interleaved instructions, only those belonging to the desired game program listing are selected and stored in RAM 59. Since these are spaced apart by a number of intervening words of no present interest (corresponding to the number of other game programs multiplexed on the cable game channel), the composite Figure 1 station data processing equipment need operate relatively slowly vis-a-vis the word transmission rate obtaining where consecutively transmitted words are part of the same game controlling program.

When all the program instructions for a desired game repose in RAM 59, the video game player 30 performs the game (executes the program) in aper se conventional manner for such players under control of the executive program in an internal ROM 39. To this end, a game/standard television program selector switch 65 is connected to its lower position to connect a standard television receiver 67 to player 30. The player 30 generates television base band video and synchronizing signals under CPU 32 control, employing ROM 39 for an executive program, RAM 59 for specific game controlling instructions, player actuated input devices (part of input source 42) for spot display location or other interactive response control, and a RAM 41 for scratch pad memory.A modulator 44 and video carrier source 45 raise (by a conventional hetrodyne process) the frequency of the base band video modulation, e.g., to that of a standard television channel.

Again, player 30 operation is perse standard. Also, the receiver 67 may view regular television (either directly or via a converter) by placing switch 65 in its upper position. Accordingly, the remaining technical discussion pertains to the manner in which a desired program set of the ensemble modulating the program carrier is received and loaded into RAM 59.

The CPU 32 controls the various ancillary elements connected thereto via a common control bus 35 and, external to the player 30, a command decoder 50.

The command decoder 50 may simply comprise per se well known combinatorial coincidence gates (which also may distributed and located at the various controlled elements) for providing appropriate enabling, address, count and like signals. Thus the decoder 50 generates gate 22 (R01) and 27 (R02), ROM 57 (R03) and address register (AR) enabling, RAM 59 read (R)/write (W), and a counter 25 presetting PRESET command signals responsive to CPU impressed command words on the bus 35.

Thus, particular ROM 57 and RAM 59 addresses for reading or writing are stored by conditioning register 55 for loading (active AR), and an address to be loaded sent by the CPU 32 on address/data bus 33.

Similarly, counter 25 is preset to a desired initial count bya PRESETsignal, and a particular count impressed by CPU on data bus 33. Memory (57,59), latch 19 and counter 25 CPU reading via bus 33 merely require corresponding control signalling.

Turning now to particular operation for the illustrative subscriber station 12 shown in detail in Figure 1 to depict RAM 59 program loading, demodulator 13 tunes and demodulates the data (program instruction) modulation on the program carrier. The embedded clock in the demodulated data digital wave is recovered at a clock recovery circuit 16 (e.g., an oscillator snychronized or triggered by a bittransition sensing differentiator). The demodulator 12 data output is delayed (element 14 to permit clock recovery), and then clocked into a shift register 18.

It will be assumed that a digital "1 " is transmitted for control purposes at the beginning of each data word, i.e., atthe beginning of each initialization and header word and each following instruction word.

When this "1" initial bit of each word progressesto the last stage in the shift register 18, the full program instruction (or data of other significance) is contained in register 18. Accordingly, a one-shot (monostable) circuit 21 is triggered to enter the incoming digital word in a word-preserving latch 19, thereafter clearing register 18 via delay 24. At an appropriate time (see below) under central processing unit 32 control, the incoming latch 19-stored word passes through gate 22 and onto a data/ address bus 33 for delivery to the CPU 32 and RAM 59. (It is assumed that RAM loading is via the CPU, although direct memory access may be utilized).

The incoming received digital words, each signalled by an output pulse from one-shot circuit 21, are counted by a selectively preset counter 25, with the counter 25 contents being passed by a gate 27 to the CPU 32 on bus 33 under CPU control. The counter 25 is preset by the CPU 32 to an initial number (more fully described belo.w) such that it will reach a predetermined state (e.g., empty or all "O's") when the next word of the program set desired for reception resides in latch 19 ready for transmittal to the CPU 32 and RAM 59. Thus, the CPU 32 examines counter 25 via gate 27, and accepts information from latch 19 only when the counter 25 reposes in the predetermined (e.g., all "0") state. This conveniently discards all instructions of game controlling programs not presently desired for the RAM 59.

Loading of instructions for the desired game into RAM 59 proceeds under stored (ROM 57) program control, and is typified by the control program flow chart of Figure 2. As a first matter, while the composite receiver is looking for the beginning of a composite interleaved message field, each incoming word stored in the latch 19 is passed by the CPU 32 via gate 22 onto the data bush 33 for delivery to the CPU. Each incoming word may be signalled by any means perse well known to those skilled in the art, e.g., by connecting the output of the one-shot circuit 21 to an interrupt port of the CPU 32; or by simply enabling gate 27 sufficiently rapidly to note any change in the state of the counter 25, such a state change corresponding to receipt of a new incoming word. In the flow chart terms of Figure 2 this is reported by the "READ WIZIRD" instruction 80.The CPU examines the incoming word to determine whether or not it is an initial one of the sequence of zeroes (branching test 82). If it is not, control passes backto program state 80 to again examine the incoming word for the initial "0" data. Correspondingly, if the incoming word is a zero ("YES" branch from test 82), a computational storage variable "ZEROES" accumulating the number of "O's" is incremented by one (instruction 84) and the ZEROS variable then tested to determine whether the requisite fifteen initialization words have been accumulated. If they have not, control returns to the program state 80 to look for the next initialization word.

After the requisite fifteen zeroes have been received ("YES" output from branching state 85), the next following header information is read into appropriate storage cells. This includes at least data yielding the number of interleaved game controlling programs modulating the program carrier which is stored in a RAM 41 variable location (NP), followed by any other desired administrative type header information, of indeed any is present.

Following completion of message synchronization (the fifteen "ZER" words) and administrative type variable loadings, the CPU 32 presets the counter 25 to a value < PRESET such that the counter will be at the predetermined state (assumed above to be all "O's") when a number of incoming words have passed and the first instruction for the desired program specified by the user at the input source 42 is then contained in the latch 19. The specific number to be initially preset is given by the modulus (M(ZlD) of the counter 25, i.e., its full count state minus the sum of the fixed, known number of header words and the number of the program desired for viewing (PN(Zl) as determined by CPU 32.Thus, beginning from the PRESET state, the counter 25 will reach the predetermined cleared, or all zero state when the first instruction for the particular desired program specified by the user via input source 42 is contained in latch 19. Following counter 25 presetting (program function 89) and entry of header information (if any), the CPU 32 is released to do other work (if any) since the next following sequence of words are first instructions for game controlling programs other than that desired by the particular user at the Figure 1 adapter station.

The CPU 32 periodically examines the state of the counter 25 by issuing a gate 27 enabling R02 command via control bus 45 and command decoder 50. So long as the counter 25 is not at the all zero predetermined state ("NO" output of branching test instruction 92), Figure 2 control passes to the READ CUNTER state 90. This occurs until the counter 25 is in fact at the all zeroes predetermined state ("YES" output from test 92), thus indicating that the first instruction for the desired program is contained in latch 19. CPU inputs the contents of latch 19 via gate 22 (enabled by an active R01 signal at this time) and bus 33 (READ WRD state 93). Following this, the incoming instruction word is processed (if appropriate for storage format or other purposes) and the first instruction stored either as received or as modified during processing in the game controlling program RAM 59.The availability of new information in the latch 19 may alternatively be signalled to CPU 32 by connecting the counter 25 overflow to a CPU 32 interrupt port.

The CPU next asks whether or not the subject incoming program listing is fully loaded in RAM 59.

For the assumed initial traverse through in the lower iterative program loop 32 of Figure 2, the program has of course not been fully loaded in the ("DNE" test fails "NO" branch). The program test 95 may be implemented in any mannerperse known to those skilled in the art, e.g., by terminating each program with a special program completion code during head end 10 transmission.

Assuming the program is not fully loaded in RAM 59 ("NO" branch from test 95), the counter 25 is now preset by CPU 32 to a state equal to its modulus (M(ZlD) minus the number of interleaved programs (NP), thus assuring that the counter 25 will clear to the predetermined zero state when the next interleaved instruction for the desired game controlling program is contained in latch 19. Following this counter 25 presetting operation of flow chart state 96, the CPU 32 is again released for other work if desired.

As before, the CPU 32 reads the counter 25 (instruction state 98) looking for the data signalling all zero state (test 99). When new data is in hand, i.e., the next following instruction for the interleaved program desired is in latch 19, test 99 returns program instruction control to state 93 to input the instruction whereupon it is processed if desired and stored in RAM 59 (flow chart block 94).

This lower loop of Figure 2 iteratively repeats until the desired game controlling program is fully contained in RAM 59 ("YES" output of test 95). The composite Figure 1 arrangement is then in a condition to execute the desired television game with a complete program in RAM 59, and program control passes to a program completed game EXECUTE state 95. As above discussed, with the game controlling program fully contained in RAM 59, the televi sion game player 30 simply uses the RAM 59 as a program memory and permits a user to execute the television game via switch 65, the standard television receiver 67, and the input source 42 as long as desired.

When a new program is desired, the user simply changes the desired program number (thereby changing the computational variable PN) by changing his thumb wheel switch setting orthe like, forming a part of data input source 42. This causes the new desired program to replace that previously reposing in RAM 59 as above discussed. Again, the CPU may sense the desire for a new program in any way perse known to those skilled in the art. This may be done under software control simply comparing the present setting of the program identifier in input source 42 with the previous setting available either directly as a storage variable or via the contents of the storage location PN, and switching to state 80 responsive to any change. Alternatively, as just one further example among many, a separate "change" button switch or the like may be included in input source 42 to directly signal CPU 32 as via a flag bit, interrupt or the like that a new program is desired.

The above-described arrangement has thus been shown to readily permit plural subscribers connected to a signal distribution medium such as a CATV cable or the like to implement a desired one of an ensemble head end of transmitted video games by simply interposing adapter equipment 12 between a cable and a program controlled conventional game player 30.

The above-described arrangement is merely illustrative of the principles of the present invention.

Modifications and adaptations thereof will be readily apparent to those skilled in the art without departing from the spirit and scope of the present invention.

Claims (10)

1. In combination in terminal means for recovering and utilizing a digital television game controlling program instruction set serially transmitted on a common transmission medium; program controlled television game playing means including a microprocessor, and a modulator coupled to said microprocessor for frequency converting an output of said microprocessor to the television radio frequency spectrum; a data bus and a further bus connected to said microprocessor; a program demodulator for recovering the transmitted digital program instruction set information; a plural stage shift register having an input connected to said demodulator for receiving, storing and shifting said recovered prog ram information; means selectively connecting the outputs of said shift register stages with said data bus; and read and write memory means connected to said data bus and to said further bus and controlled by said microprocessor for storing the program instruction set recovered by said demod ulator in said read and write memory.

2. A combination as in claim 1 wherein said terminal means includes selection means for recovering a desired one of plural time division multiplexed transmitted game program instruction sets, said selection means including input means for entering the designation of a particular one of said plural program instruction sets, and means actuated at spaced time intervals for loading successive instructions of the desired program instruction set in said read and write memory.

3. A combination as in claim 2 further comprising a coaxial signal distribution cable having said terminal means connected thereto, and head end means for impressing on said coaxial distribution cable a program carrier modulated with said plural time division multiplexed, interleaved digital television game controlling program instruction sets.

4. A combination as in claim 3 wherein said program instruction sets are modulated onto said carrier with an embedded clock, and furthercom- prising clock recovery means connecting the output of said program demodulator and a clock input of said plural stage shift register.

5. A combination as in claim 2 further comprising a first read only memory included in said television game playing means and connected to said data and said further buses for storing television game program utilization instructions, and second read only memory means connected to said data and further buses for containing read and write memory means loading program instructions.

6. A combination as in claim 2 further comprising additional read and write memory means included in said television game playing means and connected to said data bus and said further buses, said additional read and write memory means being in part employed by said microprocessor as scratch pad memory during utilization of a digital television game.

7. A combination as in claim 2 further comprising counter means selectively changing its count responsive to complete incoming program instruction words being contained in said plural stage shift register, and means for connecting the output of said additional counter means with said data bus.

8. A combination as in claim 7furthercompris- ing means for presetting said additional counter means to a count stage dependent upon the number of time division multiplexed game programs received by said terminal means.

9. A combination as in claim 3 further comprising a standard television receiver, and means for connecting the input of said receiver to one of said television game playing means orto said cable.

10. Terminal means including program controlled television game playing means including a microprocessor, and a modulator coupled to the microprocessor, substantially as hereinbefore described with reference to the accompanying drawings.