GB2039102A

GB2039102A - Buffer memory system

Info

Publication number: GB2039102A
Application number: GB7936817A
Authority: GB
Original assignee: Le Materiel Telephonique Thomson CSF
Current assignee: Thales SA
Priority date: 1978-10-27
Filing date: 1979-10-24
Publication date: 1980-07-30
Also published as: PL219201A1; GR67725B; ES8306282A1; BR7906965A; FR2440058B1; IT1124654B; IT7926799A0; FR2440058A1; ES485363A0

Abstract

A buffer memory system operates between two asynchronous functional units which may use different word lengths to allow the simultaneous exchange of data between the buffer memory and the first functional unit, and between the buffer memory and the second functional unit. The buffer memory comprises a first part P1 for data passing from the first functional unit to the second, and a second part P2 for data passing from the second functional unit to the first. Each part comprises a write availability indicator ID1 or ID2 read by the first and second functional units respectively and written into by the second and first functional units respectively and indicating the availability in the respective buffer parts of word locations in which data may be written, and a write indicator IE1 or IE2 read by the second and first functional unit respectively and written into by the first and second functional units respectively and indicating in which word locations in the respective buffer parts words have been written. <IMAGE>

Description

SPECIFICATION A buffer memory system The present invention relates to a buffer memory system for use in the intermediate storing of data to be exchanged between two functional units, and more particularly to a random-access buffer memory system for placing between two asynchronous functional units.

Buffer memories are required in data processing systems to provide, for example, an adaptation interface between functional units possessing transmission paths for data having different pulse widths and different data rates.

It is therefore possible for the format and number of data blocks exchanged during a working cycle between the buffer memory and one functional unit to be different from the format and number of data blocks exchanged between the buffer memory and the other functional unit.

According to the present invention there is provided a buffer memory system for a data exchange unit which is to operate between two asynchronous functional units to allow the simultaneous exchange of data between a buffer memory in the buffer memory system and the first functional unit, and between the buffer memory and the second functional unit, the data formats possibly being totally different for each of these exchange operations and the buffer memory comprising two parts: -a first part relating to passage of data from the first functional unit to the second functional unit, comprising an n-word data exchange zone in which the first functional unit is to write and from which the second functional unit is to read, and two n-bit indicators: a first availability indicator for indicating the availability for writing of word locations in said n-word data exchange zone, the first availability indicator being read by the first functional unit and written by the second; and a first write indicator for indicating the presence of words in said n-word data exchange zone, the first write indicator being read by the second functional unit and written by the first function unit; and -a second part relating to passage of data from the second functional unit to the first functional unit, comprising an n-word data exchange zone in which the second functional unit is to write and from which the first functional unit is to read, and two n-bit indicators: a second availability indicator for indicating the availability for writing of word locations in the n-word data exchange zone of said second part, the second availability indicator being read by the second functional unit and written by the first functional unit, and a second write indicator for indicating the presence of words in the n-word data exchange zone of said second part, the second write indicator being read by the first functional unit and written by the second functional unit.

The buffer memory access time may be shared between the two functional units such that data can be simultaneously loaded into and extracted from the buffer memory.

Moreover, it may be necessary to prevent the read process by extraction from the buffer memory from preceding the process for writing into the data memory, and vice-versa.

For a better understanding of the invention and to show how it may be put into effect reference will now be made, by way of example, to the accompanying drawings in which: Figure 1 represents an example of a data processing system in which use is made of a buffer memory system in accordance with the present invention: Figure 2 schematically illustrates an example of the buffer memory system in accordance with the present invention, as used in the data processing system shown in Fig. 1; Juxtaposed Figures 3a and 3b represent in greater detail a practical form of the example shown in Fig. 2; and Figure 4 represents the structure of the buffer memory.

Fig. 1 represents a data processing system in which use is made of a buffer memory system in accordance with the present invention in a data exchange unit 1 between a central processor 2 and x peripherals 3, to 3x The central processor 2 is connected via an input/output bus 4 to the data exchange unit 1, which possesses a microprocessor 5, a logic interface 6 interposed between the central processor and microprocessor 5, and a buffer memory system 7 interposed between the central processor and the microprocessor.

The microprocessor is connected by bothway buses 8 to the peripherals 3, to 3x The data exchange unit 1 relieves the processor of controlling the exchange of data with the peripherals, thereby avoiding processor delays, since the processor operating speed is much higher than that of the peripherals.

In addition, the same processor 2 can be connected to several data exchange units such as 1, this possibility being illustrated by dashed lines to other possible data exchange units. In this case, a signal is provided for enabling one or another of the data exchange units during the processor working cycle.

Fig. 2 schematically illustrates the buffer memory system 7 in the data exchange unit 1.

This system 7 possesses a buffer memory 10 which receives the addresses AD via an addressing multiplexer 11 fed with the addresses ADC from processor 2 and addresses ADM from microprossor 5.

It also possesses a data switching circuit 12 connected to the buffer memory 10 (data D) on one side, and to processor 2 (data DNC) and microprocessor 5 (data DNM) on the other side.

Finally, it possesses a control register 13 which generates from the signals received from the central processor 2, microprocessor 5 and logic interface 6 the signals controlling the addressing multiplexer 11, memory 10 and data switching circuit 12.

This system can be described in detail only if the working conditions of the processor and microprocessor are determined.

In the practical example shown in Fig. 3a and 3b, the central processor operates on 32bit words, whilst the microprocessor operates on 8-bit words. A buffer memory containing 32-bit words is therefore used. The buffer memory is provided by means of four readwrite memory blocks 100, 1 01, 102 and 103, each containing 8-bit words.

The addressing inputs A of the four blocks 100 to 103 are fed with the same signals AD produced by the addressing multiplexer 11.

The buffer memory access time is divided between the processor and microprocessor by means of a clock signal DBE produced by the microprocessor and controlling multiplexer 11. When the clock signal DBE is in the upper logical state, the microprocessor is able to access the buffer memory and signals AD are equal to signals ADM. When signal DBE is in the lower logical state, it is the turn of the processor to access the buffer memory and signals AD are equal to signals ADC.

By means of this addressing procedure, both functional units, the processor and microprocessor, have access to the buffer memory and conflicting situations are avoided by the system.

Buffer memory operation is synchronous with clock DBE produced by the microprocessor, and data exchange between the buffer memory and microprocessor are synchronous with respect to this clock. On the other hand, data exchange between the buffer memory and processor is asynchronous with respect to this clock and is initiated only when enabled by the processor when the latter is required to perform a data exchange cycle.

The buffer memory is divided into two distinct parts (see Fig. 4). The first part P1 is reserved for the passage of data from the processor to the peripherals. The second part P2 is reserved for the passage of data in the other direction. Each of these two parts possesses an n-word data exchange zone ZEl or ZE2, and an indicator consisting of an n-bit word.

In the example described, the size of an indicator is limited to a memory word, and the number n of data exchange zone words, is limited by the number of bits of a memory word, which in this case is n c 32. It is possible, however, to envisage indicators consisting of more than one word each if a larger data exchange zone is required.

In each of these parts, the first bit of each indicator is assigned to the first word of the corresponding zone, the second bit of each indicator is assigned to the second word, and so on, up to the thirty-second bit of each indicator, which is assigned to the thirtysecond word.

The first indicator ID is known as the availability indicator, since when a bit of this indicator is a "1", it indicates that the corresponding word is free for writing.

The second indicator IE is known as the write indicator, since when a bit of this indicators is a "1", it indicates that the corresponding word has been written and can be read.

The description starts with the case of feeding data from the processor to the microprocessor, i.e. to the peripherals.

The first part P1, which is concerned with the passage of data from the processor to the peripherals, possess a 32-word data exchange zone ZEl into which the processor writes data and in which the microprocessor reads the messages intended for the peripherals, a memory word being assigned for example to each of the peripherals.

The first indicator ID1 is set by the microprocessor and read by the processor, whilst the second indicator lEl is set by the processor and read and reset to zero by the microprocessor, as stated in the following description of data exchange.

When the processor requires to communicate data, it starts by reading the 32 bits of indicator ID1 in order to determine which words in ZEl are available for a write operation.

The processor then writes one or more 32-bit words, each in one of the available locations and as a function of the data exchange requirements.

The processor then updates indicator El, i.e. it sets to "1" those bits of lEl corresponding to the words it has just written.

Finally, the processor sends an interrupt to the data exchange unit microprocessor.

The microprocessor then accepts the interrupt and updates indicator ID1 in accordance with the contents of indicator IEl, i.e. it sets to "0" the bits of ID1 corresponding to the words which have just been written by the processor, thereby indicating that these words are no longer available for writing. It then sets indicator lE1 to zero.

The microprocessor then returns to the interrupted program after resetting the interrupt.

Thereafter, when the microprocessor is available, it read the words at its own rate (the reading of a word requiring four read operations) and sets indicator ID1 each time the reading of a word is completely terminated.

During the processing of interrupts produced by the processor, i.e. during the updating of indicator ID1, the memory cannot be accessed by the processor.

For the remainder of the time, the memory may be accessed by either the microprocessor or the processor, the access time being shared by clock DBE as explained above.

Data exchange occurs in the same manner in the other direction from the microprocessor to the processor. Indicator ID2 is set by the processor, being read and reset to zero by the microprocessor, whilst indicator IE2 is set by the microprocessor and read by the processor.

When the processor wishes to read data, it starts by reading the 32 bits of the write indicator IE2 in order to determine which words have been written by the microprocessor and are therefore to be read.

The processor then reads one or more 32-bit words in the locations to be read and in accordance with the data exchange requirements.

The processor then updates the availability indicator ID2, i.e. it sets to "1" the bits of ID2 corresponding to the words it has just read and which are available for writing by the microprocessor.

The microprocessor then accepts the interrupt and updates the write indicator IE2 as a function of the contents of ID2, i.e. it sets to "0" the bits of IE2 corresponding to the words it has just read and are to be written. It then sets indicator ID2 to zero.

It should be noted, however, that in practice a write operation immediately follows a read operation for the processor and that for this reason a single interrupt generated by the processor and sent to the data exchange unit at the end of the write operation suffices.

Indicators ID1 and lE1 are reset jointly in the data exchange unit upon reception of the interrupt from the processor.

Thereafter, when the microprocessor is available and as a function of the data produced by the peripherals, it writes by means of four write operations for each word one or more 32-bit words in the locations to be written and sets indicator IE2 each time a word has been completely written, i.e. it sets to "1" the bits of IE2 corresponding to the word it has just written.

Having described the data exchange procedure, it remains to describe the operation of the system shown in Fig. 3a and 3b during the course of read and write operations.

The control register 13 is firstly described.

The buffer memory receives from the control register a write order signal WERAM obtained from an AND gate 20 which is fed with the processor write order signal WEC and a microprocessor write order signal WEM, signals which are also used for controlling the data switching circuit.

Signal WEC is produced by a NAND gate 21 which is fed with a processor address validation signal COP obtained from the interface logic 6, a signal which is the complement of signal EWM indicating the working mode (read/write) of the processor and obtained from the processor, and a signal which is the complement of clock signal DBE obtained from the microprocessor.

Signal WEM is obtained from a NAND gate 22 which is fed with a microprocessor address validation signal MOP obtained from the interface logic 6, a signal which is the complement of signal R/W indicating the working mode (read/write) of the microprocessor and clock signal DBE, the last two of these signals being obtained from the microprocessor.

Finally, each of the buffer memory blocks 100, 101, 102 and 103 is fed with a block selection signal CSO, CS1, CS2 and CS3 respectively. When the processor is operating, all four blocks are selected, since it operates on 32-bit words. When the microprocessor is operating, only one block is selected at a time, since it operates on 8-bit words.

Signals CSi (i = 0, 1, 2, 3) are obtained on the outputs of AND gates 3i. The selection inputs of these gates 3i are fed during processor operation with a signal RDC produced by NAND gate 23 which is fed with signals COP and DBE, such that if the processor is enabled for operating in the write or read mode, all four blocks are selected. The selection inputs of these gates 3i are also fed during microprocessor operation with two signals, a signal WMi relating to write operations and a signal RDMi relating to read operations.

Signals WMi are produced by NAND gates 4i, each of which is fed with clock signal DBE and the complement of the signal obtained on the ith output of a two-input and four-output decoder 24 determining as a function of the address signals ADMO and ADM1 obtained from the microprocessor which memory block is selected for a write operation. This decoder 24 is enabled only when the microprocessor writes, and for this reason its input G is fed with a signal produced by a NAND gate 25 fed with signal MOP and the complement of signal R/W.

Signals RDMi are produced by NAND gates 5i, each of which is fed with clock signal DBE and the complement of the signal obtained on the ith output of a decoder 26 determining as a function of the address signals ADMO and ADM1 obtained from the microprocessor which memory block has been selected for a read operation. This decoder 26 is enabled only when the microprocessor reads, and for this reason its input G is fed with a signal produced by a NAND gate 27 fed with signal MOP and signal R/W.

The overall operation of the system is now described.

Firstly, for a processor write operation (EWM = O, COP = 1, DBE = 0), the processor data DNC 00/31 are applied to the memory via gates 8i (i = O to 3) producing three output states and connected by signal WEC. The write signal is established by (WEC = 0 and WERAM = 0) and applied to all the memory blocks (CSO = O, CS1 = 0, CS2 = 0 and CS3 = 0, since RDC = O) as long as DBE is in the lower logical state. The 32 bits are written simultaneously.

In the case of a processor read operation (EWM = 1, COP = 1, DBE = O, WEC = 1, WEM = 1, WERAM = 1), all four blocks are selected since RDC = 0, resulting CSi = O (i = 0, 1, 2, 3) and the data appear on the outputs of the four blocks. They are stored in register 28 on the rising edge of signal CLKDM produced by a NAND gate fed with signals EWM and COP and the complement of signal DBE, and are applied to the processor bus via open-collector NAND gates 90, 91, 92 and 93 during the presence of pulse RAC obtained from the interface logic 6.

In the case of a microprocessor write operation (MOP = 1, R/W = O, DBE = 1), data DNM 00/07 are aplied simultaneously to all four memory blocks via gates 7i (i = O to 3) having three output states and connected by signal WEM. The write signal is established (WEM = 0 and WERAM = 0) and applied to a memory block (one of signals CSi being 0 and the three others being 1 's) whilst signal DBE is in the upper logical state. The memory block has been selected by means of signals WMi obtained from decoder 24. The eight bits are written simultaneously.

In the case of a microprocessor read operation (MOP = 1,R/W = 1,DBE =1), only one memory block is selected by means of signals RDMi produced by decoder 26. The data on the output of the selected memory block are fed to the microprocessor bus via a gate 6i with three output states and connected by signal RDMi corresponding to the selected memory block.

This buffer memory system avoids overlapping of read and write operations in a simple manner and without any additional circuits by the use of indicators located in the memory itself.

Although the principles of the present invention are described above in relation with a specific practical example, it should be clearly understood that the said description is given as an example only and does not limit the scope of the invention.

Claims

1. A buffer memory system for a data exchange unit which is to operate between two asynchronous functional units to allow the simultaneous exchange of data between a buffer memory in the buffer memory system and the first functional unit, and between the buffer memory and the second functional unit, the data formats possibly being totally different for each of these exchange operations and the buffer memory comprising two parts: a first part relating to passage of data from the first functional unit to the second functional unit, comprising an n-word data exchange zone in which the first functional unit is to write and from which the second functional unit is to read, and two n-bit indicators: a first availability indicator for indicating the availability for writing of word locations in said n-word data exchange zone, the first availability indicator being read by the first functional unit and written by the second; and a first write indicator for indicating the presence of words in said n-word data exchange zone, the first write indicator being read by the second functional unit and written by the first functional unit; and - a second part relating to passage of data from the second functional unit to the first functional unit, comprising an n-word data exchange zone in which the second functional unit is to write and from which the first funcational unit is to read, and two n-bit indicators: a second availability indicator for indicating the availability for writing of word locations in the n-word data exchange zone of said second part, the second availability indicator being read by the second functional unit and written by the first functional unit, and a second write indicator for indicating the presence of words in the n-word data exchange zone of said second part, the second write indicator being read by the first functional unit and written by the second functional unit.

2. A buffer memory system in accordance with Claim 1, wherein the operation of the buffer memory is to be synchronous with the second functional unit, whereas the first functional unit is to operate at a faster rate and intervene in an asynchronous manner on a data exchange validation signal, and wherein for the exchange of data from the first functional unit to the second, the buffer memory system is such that this procedure can be executed in said first part of the buffer memory as follows:: the first functional unit will read the first availability indicator in order to determine the word locations available for writing; ~the first functional unit will write in the available locations and in accordance with predetermined data exchange requirements; ~the first functional unit will update the first write indicator in order to indicate the written locations; the first functional unit will send an interrupt signal to the second functional unit to indicate that a write operation has been performed; ~the second functional unitl will accept the interrupt signal; ~the second functional unit will read the first write indicator; ~the second functional unit will update the first availability indicator as a function of the contents of the first write indicator; ~the second functional unit will reset the write indicator to zero;; ~the second functional unit will return to an interrupted program after resetting the interrupt signal; and then when it is available: ~the second functional unit will read the words contained in the locations to be read; ~the second functional unit will set the first availability indicator each time a word has been read.

3. A buffer memory system in accordance with claim 2, wherein for transferring data from the second functional unit to the first functional unit, the buffer memory system is such that this procedure can be executed in said second part of the buffer memory as follows: ~the first functional unit will read the second write indicator to determine the locations which have been written by the second functional unit and are therefore to be read.

~the first functional unit will read the locations to be read and in accordance with predetermined data exchange requirements; ~the first functional unit will update the second availability indicator in order to indicate the locations available for writing by the second functional unit; ~the first functional unit will send an interrupt signal to the second functional unit to indicate that a read operation has been performed; ~the second functional unit will accept the interrupt signal; ~the second functional unit will read the second availability indicator; ~the second functional unit will update the write indicator of the second part as a function of the contents of the availability indicator; ~the second functional unit will reset the availability indicator to zero; ~the second functional unit will return to an interrupted program after resetting the interrupt signal; and then when it is available: ~the second functional unit will write data into the locations to be written; ~the second functional unit will set the second write indicator each time a word has been written.

4. A buffer memory system in accordance with any one of the preceding claims, which is such that each of said first and second functional units can operate at its own data rate and can modify the corresponding write indicator only when the memory word write operation has been completely terminated and the corresponding availability indicator only when the memory word read operation has been completely terminated.

5. A buffer memory system in accordance with any one of the preceding claims, wherein the availability for writing of the ith location word of each respective one of said zones is indicated by setting the ith bit of the corresponding availability indicator to "1", and the writing of the ith word of each respective one of said zones for reading is indicated by setting the th bit of the corresponding write indicator to "1".

6. A buffer memory system in accordance with any one of the preceding claims, in which the buffer memory is arranged to receive addresses from the functional units via a multiplexer controlled by a clock signal, thereby sharing the memory access time between the functional units.

7. A buffer memory system in accordance with any one of the preceding claims, and comprising a data switching circuit connected to the buffer memory and for connection to the functional units, wherein the data switching circuit comprises gates with three output states controlled by a control register which allows for the differences between the formats and data rates of the functional units by using a write signal associated with the first functional unit and write signals associated with the second functional unit for use in controlling the three-state gates.

8. A buffer memory system substantially as herein before described with reference to Figs. 3a, 3b and 4 of the accompanying drawings.

9. A buffer memory system in accordance with any one of the preceding claims, when forming part of a data exchange unit connected between two asynchronous functional units.