GB2034559A - Communications processor for selectively connecting an input/output terminal to any of a plurality of transmission lines - Google Patents

Abstract

A system (50) for selectively coupling to an input terminal (52), eg a teleprinter to any of a plurality of transmission lines (54,56,58,60) eg Private line, Direct distance dial line, telex line or TWX line respectively, having different transmission speeds and characteristics is provided. The system (50) includes decode circuitry (74,76) to selectively couple the input terminal (52) to any one of the transmission lines (54,56,58,60). An electronic digital processor (64) eg a microprocessor is responsive to input address signals generated from the input terminal (52) for being operated under the control of stored application programs (70) for causing the decode circuitry (74,76) to couple the input terminal (52) with an addressed one of the transmission lines (54,56,58,60) for transmission of data thereover at the transmission speed associated with the addressed transmission lines (54,56,58,60). The processor may provide storage (68) for incoming and outgoing data, editing facilities and ciphering for secure data transmission. <IMAGE>

Description

SPECIFICATION Communications processor for selectively connecting an inputloutput terminal to any of a plurality of transmission lines Technical field This invention relates to communications systems, and more particularly to a communication processor for controlling the interconnection of telecommunication systems via Telex, TWX, DDD and private line networks, in addition to providing accesoryfeatures such as data storage and editing capabilities.

Background of the invention Teleprinters of various types have been long used to transmit digital messages. In particular, teleprinter terminals of various types are commonly used to transmit messages over such transmission lines as Telex and TWX channels, as well as over telephone lines with the use of external modems.

For some time, it was normal to use a different specialized teleprinter for each different type of transmission line. It has heretofore more recently been known to utilize various mechanical switching arrangements to enable a single teleprinter to transmit messages over a plurality of different types of communications channels by suitable operation of mechanical switches. However, such mechanical switching arrangements are not only relatively bulky and subject to mechanical breakdown, but also often require substantial operator intervention and are relatively slow in operation. In addition, previous mechanical switching systems have not been able to provide substantial accessory features, such as automatic message switching, editing, polling, security, self-diagnosis, and the like.

The need has thus arisen fora self-contained electronic switching system which may be utilized in conjunction with a conventional inputioutput terminal to enable transmission of digital messages over a wide variety of communications channels. Such an electronic system should not only provide ease of channel switching through the keyboard of the teleprinter to enable transmissions at various speeds and according to various characteristics, but should also be compact, have high operational speeds, and provide a plurality of accessory features.

Summary of the invention In accordance with the present invention, the disadvantages and problems associated with previously developed devices have been substantially reduced or eliminated. An electronic switching system is provided which enables the conventional teleprinter to be automatically switched through operation of the teleprinter keyboard for communication with a plurality of different types of communication lines.

In accordance with the present invention, a system is provided for selectively coupling an input terminal to any of a plurality of transmission lines, each having different transmission speeds and characteristics. The system is adapted to be connected between the input terminal and the plurality of transmission lines, and includes decode circuitry operable to selectively couple the input terminal to any one of the transmission lines. An electronic digital processor is responsive to input address signals generated from the input terminal, while being operated under the control of stored application programs, for operating the decode circuitry. The decode circuitry couples the input terminal with an addressed one of the transmission lines for transmission of data thereover at the transmission speed associated with the addressed transmission line.

In accordance with yet another aspect of the invention, a system is provided for selectively coupling a teleprinter having an input keyboard and an output printer to any of a plurality of transmission lines, each having different transmission speeds and characteristics. A serial I/O may be connected to the teleprinter for receiving transmission line selection signals input through the keyboard. A digital microprocessor is connected to the I/O. A storage is associated with the microprocessor for storing a plurality of application programs. Each of the application programs corresponds to a different one of the transmission lines. The microprocessor is responsive to the transmission line selection signals for addressing one of the application programs.A line decode is connected between the microprocessor and a plurality of transmission lines, and is operable under the control of the microprocessor and the addressed application program for coupling the selected transmission line for communicating data with the teleprinter. The storage receives and stores dialing data from the teleprinter keyboard. The microprocessor, under the control of the addressed application program, causes the dialing data to be transmitted from the storage and through the line decode to the selected transmission line.

In accordance with yet another aspect of the invention, a method of selectively coupling a teleprinter to any of a plurality of transmission lines having different transmission speeds and characteristics includes receiving input address signals from the teleprinter. In response to the input address signal, a digital processor is operated in accordance with a stored application program in order to couple the teleprinter with an addressed one of the transmission lines. Data may then be transmitted over the addressed transmission line at the transmission speed and with the characteristics associated with the addressed transmission line.

Brief description of the drawings For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following Detailed Description taken in conjunction with the accompanying drawings, in which: Figure lisa block diagram of the communications processor of the present invention; Figure2 is a schematic diagram of the central processing unit and system clock circuitry shown in the block diagram of Figure 1; Figure 3 is a schematic diagram of the counter/timer circuitry shown in the block diagram of Figure 1, along with the port decode circuit; Figure 4 is a schematic diagram of the random access memory circuitry shown in the block diagram of Figure 1, along with the memory decode circuit; Figure 5 is a schematic diagram of the random access memory cells of the circuitry shown in Figure 4;; Figure 6 is a schematic diagram of the read only memory circuitry in the block diagram of Figure 1; Figure 7 is a schematic diagram of the read only memory cells of the circuitry shown in Figure 6; Figure 8 is a schematic diagram of the serial input/output circuitry shown in the block diagram of Figure 1, along with the band rate selection circuit; Figure 9 is a schematic diagram of the parallel input/output circuitry shown in the block diagram of Figure 1, along with a DAA interconnect circuit; Figure 10 is a schematic diagram of a portion of the line decode circuitry shown in the block diagram of Figure 1; Figure 11 is a schematic diagram of the Telex interface circuit; Figure 12 is a schematic diagram of the modem circuitry shown in the block diagram of Figure 1; Figure 13 is a software flow diagram illustrating the system initialization monitor subroutine;; Figure 14 is a software flow diagram illustrating the call-up subroutine; Figures 15a, 15b and 15c are software flow diagrams illustrating the edit routine; Figure 16 is a software flow diagram illustrating the list NL subroutine; Figure 77is a software flow diagram illustrating the full duplex command routine; Figure 18 is a software flow diagram illustrating the DDD command routine; Figure 19 is a software flow diagram illustrating the TWX command routine; Figure 20 is a software flow diagram illustrating the Telex command routine; Figure 21 is a software flow diagram illustrating the clear command routine; Figure 22 is a software flow diagram illustrating the private line command routine; Figure 23 is a software flow diagram illustrating the half duplex command routine; Figure 24 is a software flow diagram illustrating the status command routine;; Figure 25 is a software flow diagram illustrating the time command routine; Figure 26 is a software flow diagram illustrating the data command routine; Figure 27 is a software flow diagram illustrating the phone command routine; Figure 28 is a software flow diagram illustrating the secure command routine; Figure 29 is a software flow diagram illustrating the dial command routine; and Figure 30 is a software flow diagram illustrating the transmit receive command routine.

DETAILED DESCRIPTION System block diagram Referring to Figure 1, the communications processor of the present invention is illustrated in block diagram form and is generally identified by the numeral 50. Communications processor 50 is interconnected between a teleprinter 52, or any other suitable input/output terminal having a keyboard, and four possible data transmission lines. The data transmission lines include a private line 54, a direct distance dial telephone line 56, a Telex line 58 and a TWX line 60. The function of the present communications processor 50 is to control the connection of the teleprinter 52, under the control of inputs applied through the keyboard of teleprinter 52, and any selected one of the four output data transmission lines 54, 56, 58 and 60.The operator of teleprinter 52 can select which type of output transmission line he desires and direct connection is then established from teleprinter 52 to the selected transmission line. The present communications processor selects and connects the desired communication lines and performs various peripheral functions to be subsequently described.

Teleprinter 52 is connected to a serial input/output circuit (SIO) 62 which applies data to a central processing unit (CPU) 64. Also associated with the central processing unit 64 is the system clock. A counter/timer circuit (CTC) 66 is connected to SiO 62 and CPU 64. A random access memory (RAM) 68 is connected to CPU 64. A read only memory (ROM) 70 is also connected to CPU 64. A parallel inputloutput circuit (PIO) 72 is connected between CPU 64 and a line decode circuit 74. Line decode circuit 74 functions to interconnect one of the four communication lines 54, 56, 58 or 60 to teleprinter 52. A modem 76 is interconnected to line decode 34 and direct distance dial telephone line 56 and TWX line 60 for providing modem functions between DDD telephone line 56 and TWX line 60.

In operation of the present communications processor 50, the operator of the teleprinter 52 inputs data in a series of characters. For example, the operator might input the word "Telex". These characters are applied through SIO 62 to the CPU 64. These characters cause a stored program in ROM 70 to be addressed, which in the present example would comprise the Telex program. The stored program controls the operation of CPU 64 and causes an acknowledge character such as "Telex Network" to be printed at teleprinter 52. Additional input of the word "Phone" through teleprinter 52 causes a request symbol ":" to be displayed to the operator. This request symbol asks for a number to be input by the operator in order to designate the network desired to be communicated with. This number is input by the operator through teleprinter 52 and is stored in RAM 68.CPU 64 then causes a prompt to be displayed to the operator. The operator then inputs the word "Dial" plus any request for a number for automatic redialing. CPU 64 then causes PIO 72 to address the desired communication line through line decode 74. The previously stored dialing information is then extracted from RAM 68 and applied via CPU 64 and PIO 72 for application of the dialing signals to the selected transmission or communication line 54, 56,58 or 60. The dialing signals are then transmitted over the communication lines to the addressed remote terminal and a communications link is established.

As will be subsequently described, the present communications processor 50 also has the capability of storing incoming communications to the processor 50 until requested at a later time. Additionally, messages can be prepared and stored in memory and polled by a remote terminal for future transmission such as during low cost rate hours. The present communications processor 50 also includes the capbility of encoding messages for secure and confidential transmission of messages and data over private lines, direct distance telephone lines, Telex and TWX lines.

Inputloutput logical signal mnemonics To assist in the explanation of the present communications processor, the following is a tabulation of some of the more important mnemonics used to denote ones of the more important logic signals of the system and a brief functional description. As used throughout the following detailed description and drawings, the symbol " " or a bar above a mnemonic in the drawings, such as IORQ and the symbol following a mnemonic utilized in the Detailed Description such as lORQ-will interchangeably indicate a logic signal having an active low state.

MNEUMONIC FUNCTION A0-A1 5, AB0-AB1 5 Address Bus.

The address bus constitutes a 16-bit address bus and provides the address for memory data exchanges and for input/output device data exchanges.

D0-D7, IDB0-IDB7 Data Bus.

The data bus constitutes an 8-bit bidirectional data bus and is used for data exchanges with memory and input/output devices. The data bus is a Tri-state input/output, and has an active high.

M1- Machine cycle 1.

The machine cycle 1 is an output, active low signal and indicates that the current machine cycle is the operation code fetch cycle of an instruction execution.

MREQ-, MRQ- Memory Request. This signal indicates that the address bus holds a valid address for a memory read or memory write operation and is a Tri-state output, active low.

IORQ- Input/Output Request.

This signal indicates that the lower half of the address bus holds a valid input/output address for an input/ output read or write operation. The input/ output request is a Tri-state output, active low signal.

RD- Memory Read. The memory read signal indicates that the CPU wants to read data from memory or an input/output device. This signal is a Tri-state, output, active low.

WR- Memory Write. The memory write signal indicates that the CPU data bus holds valid data to be stored in the address memory of input/output device. The memory write signal is a Tri-state output, active low.

RFSH- Refresh. The refresh signal indicates that the lower seven bits of the address bus contain a refresh address for dynamic memories. The refresh signal is an output, active low signal.

HALT- This signal indicates that the CPU has executed a HALT software instruction and is awaiting either a nonmaskable or a maskable interrupt before operation can resume.

The HALT- signal is an output signal, active low.

WAIT- The WAIT- signal indicates to the CPU that the addressed memory or input/output devices are not ready for a transfer of data. The WAIT signal is an input, active low signal.

INT- This signal is an interrupt request signal and is generated by input/output devices.

The INT- signal is an input, active low signal.

NMI- Nonmaskable interrupt signal is an input, negative edge triggered signal.

The nonmaskable inter rupt request line has a higher priority than INT- and is always recognized at the end of the current instruction.

RESET-, MRST- This is a reset signal and forces the program counter to zero and initializes the CPU. The RESET signal is an input, active low signal.

BUSRQ- Bus Request. The bus request signal is used to request the CPU address bus, data bus and Tri-state output control signals to go to a high impedance state so that other devices can control these buses.

The BUSRQ- signal is an input, active low signal.

BUSAK- Bus Acknowledge.

The bus acknowledge signal is used to indicate to the requesting device that the CPU address bus, data bus and Tri state control bus signals have beensetto their high impedance state and the external device can now control these signals. The BUSAK signal is an output, active low.

1$, l/2l System clocks ABO, B/A Port B or A select.

This signal defines which port will be accessed during a data transfer between the CPU and PIO.

A low level input signal selects Port A and a high level signal selects Port B.

AB1, C/D Control or data select.

This signal defines the type of data transfer to be performed between the CPU and the PIO.

GP4, GP6, CE- Chip enable. The chip enable signal is an input/active low and enables the PIO to accept command or data inputs from the CPU during a write cycle orto transmit data to the CPU during a read cycle.

IEl Interrupt enable in.

This signal is used to form a priority interrupt daisy chain when more than one interrupt driven device is being used. The signal is then input active high signal.

IEO Interrupt enable out.

This signal is another signal required to form a daisy chain priority scheme and is an output, active high signal.

PI OA0-A7 Port A, Bus.

This signal is a bidirectional Tri-state 8-bit bus used to transfer data and'or status or control information between Port A of the PIO and the line decode circuitry.

PIOB0-B7 Port B Bus. This signal is a bidirectional, Tri-state 8-bit bus used to transfer data andior status or control information between Port B of the PIO and the line decode circuitry.

CTSB- Clear to Send.

The clear to send is an input, active low signal to the SIO.

DCDB- Data Carrier Detect.

This signal is an input, active low to the SIO and is used to receive inhibits.

RXDA, RXDB Receive Data. This signal is an input, active high to the SIO.

TXDA, TXDB Transmit Data. This signal is an output, active high from the SIO.

Z0,Z2 Receiver and Transmitter Clocks. These clock signals are generated by the CTC and are inputs, active high to the SIO.

RTSB- Request to Send.

This signal is an output, active low from the SIO.

DTRA- Data Terminal Ready.

This signal is an output, active low from the SIO.

SYNCB- External Character Synchronization. This signal is an input/ output active low signal of the SIO.

System hardware Referring to Figure 2, the schematic circuitry which corresponds to the CPU and system clock, block 64 of Figure 1, is illustrated. A crystal oscillator 90 having a fundamental frequency of 19.6608 MHz provides an output to a divider 92. Counter 92 is a synchronous 4-bit counter and may comprise, for example, a 74161 I/C.

The output of counter 92 generates the l and 1/2 system clock timing signals. The 1(Z) timing signal is applied to a central processing unit (CPU) 94. CPU 94 may comprise, for example, a Z80-CPU manufactured and sold by Zilog, Inc. of Cupertino, California. The operation of CPU 94 including the architecture and instruction set are contained in the "Z80-CPU, Z80A-CPU Technical Manual" copyright 1977 by Zilog, Inc.

The lDBo-lDB7 data bus signals generally identified by the numeral 96 are also applied to CPU 94 as shown.

Additionally, the NMi-, WAIT-, BUSRQ-, and INT-signals are applied to CPU 94.

A reset switch 98 is interconnected in parallel with a capacitor 100. Upon actuation of reset switch 98, a signal is generated that is applied to an inverter 102 whose output is applied to an inverter 104 to generate the RESET- signal applied to CPU 94. The output of inverter 102 is also applied to a NAND gate 106 to generate the MRST- signal.

The output of CPU 94 is applied to drivers 108, 110, 112 and 114. Drivers 108, 110, 112 and 114 are Tri-state hex buffer drivers and may comprise, for example, LS367 I/Cs. Drivers 108, 110 and 112 generate the address bus signals AB0-AB1 5. Additionally, driver 110 generates the Ml signal, driver 112 generates the RFSHsignal and driver 114 generates the WR-, lORQ-, RD-, HALT-, and BUSAK- signals as previously described.

The outputs of drivers 108, 110, 112 and 114 amplify the output of CPU 94 which generates the AB0-AB15 address bus, M1-, RFSH-, WR-, lORQ-, RD-, MRQ-, HALT- and the BUSAK- logic signals.

Referring to Figure 3, the schematic circuitry corresponding to the counter/timer circuit, block 66 of Figure 1, is illustrated,also with port decode circuitry. The address signal AB5 is applied through an inverter 130 to a NAND gate 132. Address signal AB7 is also applied to NAND gate 132, whose output is applied to a decoder 134. Decoder 134 may comprise, for example, an LS138 I/C. The output of NAND gate 132 together with the AB6 address signal and the lORQ-signal provides the enable inputs to decoder 134. Address signals AB2-AB4 are applied to decoder 134 and comprise the select inputs. The output of decoder 134 are the signals GP4- GP7-. The address bus signals AB1 and AB0 are applied to a decoder 136. Decoder 136 may comprise, for example, an LS139 I/C. Decoder 136 generates the SG1- signal.Decoders 134 and 136 function to interface between CPU 94 and SIO 62 and PIO 72.

The GP5- output signal of decoder 134 is applied to a counter/timer 140 providing an enable signal for counter/timer 140. Counter timer 140 may comprise, for example, a Z80-CTC manufactured and sold by Zilog, Inc. of Cupertino, California. The structure, architecture and programming for a Z80-CTC counter/timer is described in the product specification dated october, 1977 and entitled "Z80-CTC, Z80A-CTC" published by Zilog, Inc.

The data bus 96 is applied to counter/timer 140 and functions to strobe counter/timer 140. Counter/timer 140 is fully programmable and functions as a modulo M divider. The input value from data bus 96 determines the value which counter/timer 140 will use to perform the division. The outputs of counter/timer 140, ZO and Z2, will have a frequency which is directly proportional to the 8-bit character input to counter/timer 140 via data bus 96. The operation of counter/timer 140 functions to establish the operating parameters for the frequency of the transfer of gata from the SIO 62.

Additional inputs to counter/timer 140 include the M1- IORQ-, RD-, MRST, im, and 1/2 logic signals. The lORQ-signal and RD- signal are also applied to an OR gate 142 which generates the IORD- signal. Additional outputs of counter/timer 140 include the INT- signal and CTCIEO signal. An external clock having a frequency of 60 Hz is provided from the power supply through an amplifier 144 to counter/timer 140.

Referring simultaneously to Figures 4 and 5, the schematic circuitry corresponding to the RAM, block 68 of Figure 1, is illustrated. Address signals AB0-AB13 are applied to either a multiplexer 160 or a multiplexer 162.

Multiplexers 160 and 162 are quad-two-line to one-line data selectors/multiplexers and may comprise, for example, LS1 57 I/Cs. The output of multiplexers 160 and 162 is applied to a RAM cell array generally identified by the numeral 164. RAM cell array 164 as more clearly illustrated in Figure 5 includes thirty-two RAM cells arranged in four banks being eight cells wide. This configuration provides an 8-bit word. RAM cell array 164 includes bank 166 including cells 166a-166h; bank 168 including cells 168a and 168h; bank 170 including cells 170a-170h; and bank 172 including cells 172a-172h. Each RAM cell comprising banks 166, 168, 170 and 172 is a 16K x 1-bit dynamic RAM and may comprise, for example, a Z61161/C manufactured and sold by Zilog, Inc.

The CAS- signal generated by multiplexer 162 is applied to RAM cell array 164 and functions as a column address strobe to strobe the particular column of the RAM cell array 164 to select the particular RAM cell within banks 166,168,170 and 172 of RAM cell array 164. Additional inputs to RAM cell array 164 comprise the RAS0-, RAS1 -, RAS2- and RAS3-signals which comprise the row address strobe for selecting which row of the banks 166, 168, 170 or 172 is being addressed.

Referring again to Figure 4, multiplexers 160 and 162 gate in the low order and high order address bits from the address bus AB0-AB1 5 into the RAM cell array 164 along signals A0-A6 as previously described.

Each half cycle of multiplexers 160 and 162 applies the low order address bits AB0-AB6 and the high order address bits AB7-AB13 to RAM cell array 164. The output of RAM cell array 164 is applied from signal lines DO0-DO3 to a driver 180 and along signal lines DO4-DO7 to a driver 182. Drivers 180 and 182 are Tri-state hex buffer drivers and may comprise, for example, LS367 I/Cs. The output of drivers 180 and 182 applies the output of RAM cell array 164 to the data bus 96.

Address bits AB12 and AB13 are applied to a decoder 184 and a decoder 186 together with address bits AB1 4 and Ambi 5. Decoders 184 and 186 are two-line to four-line decoders and may comprise, for example, LS139 I/Cs. The outputs of decoders 184, and 186 are applied to AND gates 190,192,194 and 196 through strapping arrangements 198 and 200. The particular configuration of strapping arrangements 198 and 200 determines the boundary size of the RAM cell array 164 to be utilized by the present system. The strapping arrangements 198 and 200 therefore allow the system to be customized, such that smaller area of the RAM cell array 164 is utilized for the software package. In this manner a portion of RAM cell array 164 can also be used for read only memory functions.Strapping arrangement 200 selects one of four 16K blocks of memory and strapping arrangements 198 selects one of four 4K blocks of memory. The outputs of AND gates 190, 192, 194 and 196 are applied to AND gates 202, 204, 206 and 208 together with the RFSH-signal applied through and AND gate 210. The outputs of AND gates 202,204,206 and 208 are applied to NAND gates 212, 214,216 and 218 together with the MRQ- signal. The outputs of NAND gates 212,214,216 and 218 generate the RAS0-, RAS1-, RAS2- and RAS3- signals for application to RAM cell array 164.

The outputs of decoders 184 and 186 are also applied through strapping arrangements 198 and 200 to a NAND gate 220. The RFSH- signal is applied to an AND gate 222 whose output is applied together with the output of NAND gate 220 to a NAND gate 224. The output of NAND gate 224 generates the ROM SELECTsignal.

The outputs of NAND gates 212,214,216 and 218 are also applied to inverters 226,228,230 and 232 whose outputs are applied to a NAND gate 234. NAND gate 234 also receives as an input the RFSH- signal. The output of NAND gate 234 is applied through inverters 236 and 238 to multiplexers 160 and 162 and through inverters 240 and 242 to multiplexer 162. Inverters 236,238,240 and 242 are hex inverters and may comprise, for example, a 74L04 I/C.

The output of inverters 226, 228, 230 and 232 are also applied to a NAND gate 244 whose output is applied to a NAND gate 246. NAND gate 246 also receives as an input the RD- signal and generates the RAM STROBE signal applied to drivers 180 and 182. The RAM STROBE signal enables drivers 180 and 182 to apply the contents of RAM cell array 164 to the data bus 96. The RAM STROBE signal is a combination of the RD- signal and the output of NAND gate 244 which indicates a valid RAM address is present. The outputs of inverters 238 and 242 applied to multiplexers 160 and 162 determine the portion of the cycle which multiplexers 160 and 162 are to select the high order and low order address bits to be strobed into RAM cell array 164.

Inverters 236, 238, 240 and 242 function to provide a propagation delay to generate two strobe pulses for application to multiplexers 160 and 162.

Figure 6 illustrates the schematic circuitry corresponding to the ROM, block 70 of Figure 1. Address bits AB1 1, AB12 and AB13 are applied to a decoder 260 which is a one-of-eight decoder and may comprise, for example, an LS1 38 I/C. Decoder 260 functions to select one of eight ROM cells contained within a ROM cell array 262 along signal lines CS0-CS7. Decoder 260 is enabled by the ROM SELECT- signal applied to decoder 260 from the output of NAND gate 224 (Figure 4). In operation, when the ROM SELECT- signal is at a logic low, decoder 260 accepts data from address signals AB11, AB12 and AB13 to derive a valid address to select from one of eight outputs along CS0-CS7 output lines.Astrapping arrangement 264 accommodates three boundaries of ROM cell array 262 and includes one-half K, K, or a 2K memory boundaries.

Address bits AB0-AB1 0 are applied to ROM cell array 262. A strapping arrangement 268 interconnects address bit 10 to ROM cell array 262 to accommodate various versions of ROM cell array 262. The output of ROM cell array 262 is applied to the data bus 96.

Figure 7 illustrates the configuration of the ROM cell array 262 as including eight ROMs 270, 272,274, 276, 278, 280, 282, and 284. ROMs 270-284 may comprise, for example, 2716 liCs. As shown in Figure 6, address bus signals AB0-AB10 are applied to ROMs 270-284. Each ROM 270-284 also receives a select signal along signal lines CS-0 - CS-7 generated by decoder 260. When one of ROMs 270-284 is selected by the CS-0 - CS-7 signals, this provides an enable for ROM cell array 262 to output its data to the data bus 96. A strapping arrangement 286 is provided to supply various power requirements to accommodate different types of ROMs for ROM cell array 262 (Figure 6).

Referring to Figure 8, the schematic circuitry corresponding to the serial 110 (SIO), block 62 of Figure 1, is illustrated. Data bus 96 is supplied to an SIO 300. SIO 300 may comprise, for example, a Z80-SIO manufactured and sold by Zilog, Inc. of Cupertino, California. The SIO features, operation and programming for a Z80-SlO are described in a publication entitled "Z80-SlO Product Specification Preliminary" March, 1978, published by Zilog, Inc. SIO 300 is a programmable, dual-channel device which provides formatting of the data applied on data bus 96 for serial data communication. The various logic signals applied to SIO 300 and generated by SIO 300 have been previously described in the section identified as InputiOutput Logic Signai Mnemonics.

In operation, SIO 300 is enabled by the GP4-signal which is the chip enable signal to SIO 300. The inputs along signals AB1 and ABO are then sampled. The AB0 signal determines which channel, channel A or channel B, of SIO 300 will be utilized. The signal AB1 determines whether SIO 300 will be in the control mode or data select mode. The RD- signal will determine whether SIO 300 is in the input or output mode of operation. The MRST-signal is the master reset and indicates to SIO 300 to begin searching for new data on the data bus 96.

Figure 8 also illustrates the interconnection of a switch 302 to drivers 304 and 306. Switch 302 is a eight position dual in-line package switch. Drivers 304 and 3p6 are Tri-state hex buffer drivers and may comprise, for example, LS367 I/Cs. The outputs of drivers 304 and 306 are applied to data bus 96 for application to SIO 300. Drivers 304 and 306 under operator control through inputs to teleprinter 52 (Figure 1) sample the contents of switch 302 in order to establish a baud rate for application to SIO 300. Upon actuation of the initialization routine of the software of the present system, to be subsequently described, CPU 64 generates the necessary signals to sample switch 302 to arrive at a baud rate.Depending upon the contents of switch 302, a control term is applied to the CTC 66 for proper dividing of the specified frequency to generate the specific baud rate selected.

The GP7- signal and SG1- signal are applied to an OR gate 308 whose output is applied to an OR gate 310.

The IORO- signal is also applied as an input to OR gate 310 whose output is applied to drivers 304 and 306.

The output of OR gate 310 generates a Tri-state strobe for drivers 304 and 306 to sample the contents of switch 302 and to output this content to the data bus 96.

Switch 302 is permanently strapped depending upon the configuration of the system in which the present communications processor 50 is utilized. The present communications processor 50 is capable of operating at a 50 baud rate for Telex communication, a 0-300 baud rate for TWX and DDD communications and a 0-19.2 KB and a 20-60 MA baud rate asynchronous and synchronous mode private line communications. The strapping of switch 302 established bit patterns for the determination of the various baud rates depending upon the configuration of the system in which the present communications processor 50 is utilized.

Referring to Figure 9, the schematic circuitry corresponding to the parallel I/O (PIO), block 72 of Figure 1 is illustrated. A PIO 350 is a programmable, two port device which provides an interface between peripheral devices and CPU 64 (Figure 1). PIO 350 may comprise, for example, a Z80-PIO manufactured and sold by Zilog, Inc. of Cupertino, California. The architecture and programming for the Z80-PIO is contained in a publication entitled "Z80-PIO, Technical Manual" copyright 1976, published by Zilog, Inc. PIO 350 receives an input from data bus 96 and also receives the G PG-signal as an enable signal, the ABO, AB1, PIO IEl, IZI, M1-, IORO- and RD- input signals previously described.

PIO 350 also receives PIO A2 address line the RI signal supplied by a TWX molex 352. PIO 350 also receives along the address line PIO A3 the CCT signal from TWX molex 352. The RI signal, ring in, indicates to CPU 64 (Figure 1) that there is a ring present on the TWX line. The CCT signal, coupler cut through, indicates to CPU 64 that a dial tone has been achieved and that the system is capable of receiving dialing information. An output of PIO 350 is applied along address line PIO B1 to the base of a transistor 354 which generates the OH and DA output signals to TWX molex. The OH signal, off hook, indicates to the TWX terminal that a user of the system has placed the TWX line in an off hook configuration. In operation, PIO 350 generates the off hook signal and when cut through is achieved, the CCT signal is applied from TWX molex 352 to PIO 350.The receipt of the cut through signal by PlO 350 signals CPU 64 (Figure 1) to begin the transmission of dialing information. The transmission of dialing information is begun by pushing the off hook and data access, DA, inputs to TWX molex 352.

PIO 350 is similarly interconnected to a DDD molex 356. The CCT signal is applied from DDD molex 356 to the PIO Al address line and the RI signal is applied to the PIO A0 address line. An output along PIO B0 address line is applied to the base of a transistor 356 for generating the DA and OH signals applied to DDD molex 356.

Referring to Figure 10, the circuitry corresponding to the line decode, block 74 of Figure 1, is illustrated.

Line decode block 74 includes interfacing for private line 54 (Figure 1) which comprises operational amplifiers 380 and 382. The TXDA signal from SIO 300 (Figure 8) is applied to operational amplifier 380 which is a quad line driver and may comprise, for example, an MC1488 I/C. The output of driver 380 is applied to private line 54. A signal from private line 54 is applied to a quad line driver 382 which may comprise, for example, an MC1489 I/C for generating the RXDA signal for application to SIO 300 (Figure 8).

Line receiver 380 functions to convert the signal level of the TXDA signal to that compatible with private line 54, while receiver 382 functions to convert the private line signal level to a TTL signal level for use by SIO 300.

Drivers 382 and 380 with respect to the DCDB- and DTRA- signals. Driver 384 may comprise, for example, an MC1489 I/C and driver 386 may comprise, for example, an MC1488 I/C.

The RTSB- signal from SIO 300 (Figure 8) is applied to an AND gate 400 that also receives an input from PIO 350 along the PIO A6 address line indicating that valid Telex data from line 58 (Figure 1) is being received.

The output of AND gate 400 is applied to a NOR gate 402 whose output is applied to a multiplexer 404.

Multiplexer 404 is a dual four-line to one-line data selector/multiplexer and may comprise, for example a 741531/C. Multiplexer 404 also receives an input of the receive modem data signal from modem 76 (Figure 1) and through a line receiver 406 receives as an input signal the private line receive data signal from the private line 54 (Figure 1). Line receiver 406 may comprise, for example, an MC1489 I/C. The PIO B4 address line is applied to the Select A input of multiplexer 404 and the PIO B3 address line is applied to the Select B input of multiplexer 404. Depending upon whether the Select A or Select B portion of multiplexer 404 is selected by PIO B4 or PIO B3, the input of the receive modem data or the receive private line data will be output as the RXDB signal from multiplexer 404.

The PIO B4 address signal is also applied to an AND gate 408 which also receives the TXDB signal to generate the transmit modem data output signal applied to modem 76 (Figure 1). The PlO B4 address signal is also applied through an inverter 410 to an AND gate 412 which also receives the PIO B3 address signal. The output of AND gate 412 is applied to an AND gate 414 which also receives as an input the TXDB signal. The output of AND gate 414 is applied to a line drivber 416 to generate the private line transmit data signal applied to private line 54 (Figure 1).

The PIO B3 address signal is also applied through an inverter 418 to an AND gate 420 which also receives the output of inverter 410. The output of AND gate 420 is applied to an AND gate 422. AND gate 422 receives as a further input the TXDB signal applied thorugh an inverter 424. The output of AND gate 422 is applied to an OR gate 426 which also receives the PIO B2 address signal to generate the Telex transmit data signal. The TXDB signal determines whether data will be transmitted to the private line 54, the Telex line 58 or the modem 76 for application to the DDD line 56 or TWX line 60.

Figure 11 illustrates a portion of the schematic circuitry included within the line decode, block 74 Figure 1, which comprises the Telex line 58 interface. incoming Telex data is applied on the send line to a diode bridge circuit 450. An output of diode bridge circuit 450 is applied to an optical isolator 452. Optical isolator 452 may comprise, for example, a 4N36 device. Current flowing through optical isolator 452 will cause a diode 452a to be actuated which in turn will turn on a transistor 452b which is part of optical isolator 452. The output of transistor 452b is applied to a transistor 454 whose output generates the Telex receive data signal on the PIO A6 address line.

Current flows from diode 452a through a resistor 456 and through diode bridge circuit 450 to a diode 458.

The output of diode 458 is applied through a resistor 460 to a relay generally identified by the numeral 462.

Current flows through relay 462 through relay contact 462a to a relay generally identified by the numeral 464.

Current flows through relay contact 464a and returns to the Telex line 58 (Figure 1) via the REC signal line.

A reverse polarity in the signal flowing on the REC signal line is detected by an optical isolator 466. Current flows along the REC signal line through relay 464, relay 462, resistor 460 and into a diode 466a associated with optical isolator 466. Optical isolator 466 may comprise, for example, a 4N36 device. Current flowing through diode 466a forward biases diode 466a to actuate diode 466a which in turn actuates a transistor 466b.

The output of transistor 466b is applied to a transistor 468 which generates a signal applied to the PIO A5 address line.

The PIO B7 address line is applied to a transistor 480 which functions as relay driver for relay 462.

Conduction of transistor 480 causes relay 462 to conduct through relay contact 462b to bypass resistor 460 which in turn causes optical isolators 452 and 466 to conduct to generate outputs on the PIO A6 and PIO A5 address lines.

The Telex transmit data signal is applied to a transistor 484. Conduction of transistor 484 causes relay 464 to break the circuit between the REC signal line and relay terminal 464a to interrupt the current loop previously described. Interruption of the current loop permits data to be transmitted to the Telex line 58 (Figure 1). Data is received from the Telex line 58 through transistor 454 and is output to the Telex line 58 through transistor 484.

Referring to Figure 12, the schematic circuitry corresponding to the modem, block 76 of Figure l,is illustrated. Modem 76 includes a receive-transmitter modem circuit 500. Modem circuit 500 functions to encode and decode standard tones and may comprise, for example, an MC14412 liC. A crystal oscillator 502 provides an input to modem 500 in the form of a 1 M Hz signal which is transformed by modem circuit 500 to achieve different frequencies for use in the present system. The PIO B6 address signal is applied to the mode input of modem circuit 500 and is used to indicate whether modem circuit 500 will be operating in either the answer or originate mode. The answer mode of operation represents a band of frequencies between 1070 Hz and 1272 Hz.The originate mode represents a band of frequencies between 2025 Hz and 2225 Hz. The PIO B5 address signal is applied to modem circuit 500 and is an enable to modem circuit 500.

Upon being enabled, modem circuit 500 will transmit data from the TX CAR output to a line amplifier 504.

Line amplifier 504 may comprise, for example, an MC1458 I/C. The output of line amplifier 504 is applied to a transformer 506 output is applied to relays 510 and 512. Operation relays 510 and 512 applies the output from line amplifier 504 either to the TWX molex terminals DT and DR through the relay contacts 510a and 512a orto the DDD molex via the DT and DR terminals through relay contacts 510b and 512b. The operation of relays 510 and 512 is controlled by the signal on PIO B3 address line which is applied to a transistor 514.

Data entering modem 76 (Figure 1) through the DDD line 56 or TWX line 60 through DDD molex 356 (Figure 9) or TWX molex 352 (Figure 9) is applied to relays 510 and 512. The outputs of relays 510 and 512 applied through relay contacts 51 Ob and 51 2a are applied to transformer 506. The output of transformer 506 is applied to a line driver 516 whose output is applied to an input of filter 520. Filter 520 may comprise, for example, a Model 207C400 manufactured and sold by Sprague Electric Company of North Adams, Massachusetts and described in Sprague Engineering Bulletin 22113. The output of filter 520 limiter out, is applied to the RX CAR input of modem 500. Filter 500 demodulates this input signal and applied it to the RX data terminal for output via the RX modem data signal line. The actual audio content of the amplified signal from line receiver 516 applied to filter 520 is output via the RX filter output terminal 522. The output of line receiver 522 is rectified through operation of diodes 524 and is applied to a line receiver 526 to generate the carrier detect, CAR. DET., signal applied to the PIO A4 address line. The presence of the carrier detect signal is sensed by a light emitting diode 528.

Processor operation Figures 13-30 illustrate flow diagrams of the operation of the present communications processor 50 (Figure 1). Figure 13 illustrates the flow diagram for the initialization monitor subroutine. The start of initialization is begun at 600 upon application of power to communications processor 50 or upon actuation ot a master reset switch included within communications processor 50. After start of the system at 600 the PlO A and B ports are initialized at 602 and 604. The SIO 62 B and A ports are initialized at 606 and 608. The switch setting of switch 302 (Figure 8) which are prestrapped are then read by the system software at 610. After the baud rate is set at 612, the clock timer circuitry 140 (Figure 3) is initialized at the CT0, CT2 and CT3 inputs at 614,616 and 618.The control word for the telephone number is initialized by placing zeros into this storage location at 620. The time and date clock is then initialized to zero at 622. The initialization monitor subroutine then enters the command initialization subroutine at the "Start 1" 624 (Figure 14).

Referring to Figure 14, after start of a command initialization at 626, the command monitor then prints out a message at 628 to the teleprinter 52 (Figure 1). A carriage return and a line feed of the teleprinter 52 is then performed at 630 by the CRLF subroutine. A character string is then output to the teleprinter 52 and 632 by the call TTYWR subroutine. The command routine then waits at 634 for data to be keyed in through teleprinter 52. The routines 630, 532 and 634 are utility subroutines for standard input/output processing of data. An edit command or a reset command of the DDD, Telex, TWX or private line is then checked through the command table at 636. A decision is made at 638 and if the command is valid, an entry point to the command subroutines is made at 640.The command subroutines include the edit routine 642, dial routine 644, DDD routine 646, Telex routine 648, TWX routine 650, private line routine 652, secure line routine 650, private line routine 652, secure line routine 654, full duplex routine 656, clear routine 658, status routine 660, phone routine 662, data routine 664, time routine 666 and half duplex routine 668. At the completion of each command routine 642-668, the system returns to the "Start 0" entry point at 670.

If the decision at 638 was that command was invalid, an error message is output to teleprinter 52 at 672 and the command subroutine is reexecuted at 624, Start 1.

Referring to Figure 1 5a, a portion of the edit routine flow diagram is illustrated. After the start of the edit subroutine at 700 an output message is sent to teleprinter 52 (Figure 1) at 702. The system waits for data to be input through teleprinter 52 at 704 and at 706 a decision is made whether the input data was for Telex communication. If the decision was yes, the Telex routine is called at 708 and the phone routine is called at 710. The program then proceeds at the entry point A, 712. If the decision at 706 is no, a decision is made at 714 to determine whether the input communication was TWX. If the decision is yes, the TWX routine is called at 716, and the phone routine is called at 718. The program then proceeds to entry point A, 712.If the decision at 714 was no, the decision is made at 720 whether the input communication is DDD. If a yes determination is made, the DDD routine is called at 722 and the phone routine is called at 724. The program then proceeds at the entry point A at 712. If the decision at 720 is no, a decision at 726 is made as to whether the input is a private line. If this decision is yes, the private line routine is called at 728 and the phone routine is called at 730. The program then proceeds at the entry point, A at 712.

If the decision at 726 is no, the program is set to count the letter at 732 and the input lines from the modem are disabled at 734. The character count is then set at 736 and an output message is sent to the teleprinter 52 and 738. At 740 the line sequence is tested if the first three characters of the last line output is a ":"the program proceeds to entry point 742. If a no decision is made at 740, the line number pointer is reset at 744 and the program continues at 742. The determination that a colon exists in the editor monitor means that the next character to be received is a command in the form of a letter.

Referring to Figure 15b, the decision from 740 (Figure 15a) at 742 prompts an output message at 746 and the first input byte is received at 748. If the first character of the A byte is a colon determined at decision 750 then the various commands are tested at decision block 752 to determine if the second byte is a "D" to call the delete program, 753; 754 to determine if the second byte is a "E" to call the enable program, 755; 756 to determine if the second byte is an "F" to call the find program, 757; 758 to determine if the second byte is a "I" to call the insert program, 759; 760 to determine if the second byte is an "L" to call the list program, 761; 762 to determine if the second byte is an "M" to call the modify program, 763; and 764 to determine if the second byte is an "R" to call the read program 765.

The testing of the commands further proceeds in Figure 1 sic at the entry point 766 (Figure 15b). The decision is made at 768 to determine whether the second byte is an "S" to call the scratch program, 769; the decision is made at 770 to determine whether the second byte is a "W" to call the write program, 771; the decision is made at 772 to determine if the second byte is a "+" to call for forward routine, 773; the decision is made at 774 to determine if the second byte is a "into call the backward routine, 773; the decision is made at 776 to determine if the second byte is an "&commat;" to call the Posit program, 777; the decision is made at 778 to determine if the second byte is an "*" to call the show here program, 779; the decision is made at 780 to determine if the second byte is a "P" to call the list NL program 781 and the decision is made at 782 to determine if the second byte is an "X" to call the dial program 783. If the command fails to be any one of the commands tested for at decisions 752-782, an output error message is sent to teleprinter 52 at 784 and the system returns via the get line exit point 786.

The delete program 753 functions to delete a line being pointed at. The enable program 755 functions to exit from the edit routine and to enable all output and input lines coming from the modem to receive and send transmissions. The final program 757 functions to locate a character string. The insert program 759 functions to insert a character string directly after the line being pointed at. The list function 761 functions to list the entire editor memory. The modify program 763 functions to modify a line on which the character string was located using the fine program 757. The read program 765 functions to read a line. The scratch program 769 functions to erase memory and to reset the line pointer to one. The write program 771 functions to write or punch a tape. The forward program 773 functions to move the line pointer forward.The backward program 775 functions to move the line pointer backward. The posit program functions to position the line member. The show here program 779 functions to indicate the line the position pointer is pointing at. The list NL program 781 functions to list a new line, to be subsequently described in connection with Figure 16. The dial program 783 functions to dial a telephone number, to be subsequently described in connection with Figure 29.

At the conclusion of examining for each of the command letters of the second byte the program recycles through the get line point of entry 786 to the output from prompt message at 746 (Figure 1 5b). Again referring to Figure 1 sub, if byte A is not a ":" at decision block 750, the byte A is not":" at decision block 750, the byte count is incremented at 788. A decision is made at 790 as to whether the byte count does not equal the character count. If this decision is yes, an output bell message is indicated at 792 and the decision is then made at 794 as to whether the byte A is a carriage return. If the byte count does not equal the character count, the decision block 790 flows directly into the decision block 794.If the byte A is a carriage return, the flow from decision block 794 is applied through point of entry 796 to increment the line count at 798. If the byte A does not equal a carriage return, a decision is made at 800 as to whether the byte count equals the character count. If the decision is yes, the program reenters at entry point 796. If the decision is no, the character count is decremented at 802 and is input as the A byte at 804 for input through the point of entry 806 to decision block 750.

Referring to Figure 16, the list NL subroutine flow diagram is illustrated. The current line of text is saved at 820 and the line pointer is reset at 822. After the line number is masked off at 824 the line is listed at 826. The line pointer is then incremented at 828 and a decision is made at 830 as to whether the current line is overrun. If the decision at 830 indicates that the current line is not overrun, the flow returns to 824. If the current line is overrun, four carriage returns and four line feeds are performed at 832 and the line pointer is reset at 834. The flow then continues at the get line 786 entry point to the output message 746 block (Figure 15b).

Figure 17 illustrates the full duplex 56 (Figure 14) command flow diagram. After the mode word is set to one at 840, the load pointer is set to a full message at 842. The output message is then pointed to at 628 (Figure 14) at the Start 0 entry point, 670.

Figure 18 illustrates the flow diagram for the DDD command at entry point 646 (Figure 14). The CTC2 line to counter,timer 140 (Figure 3) is enabled at 850 and the SIO B port is enabled at 852. The baud rate is input from the PIO at 854 and any new baud if necessary is output at 856. The load point of the DDD message is then output at 858 to the Start 0 entry point, 670 (Figure 14).

Referring to Figure 19, the software flow diagram for the TWX command is illustrated and is similar to the DDD command flow diagram of Figure 18. The counteritimer 140 is set for the TWX rate at 860 and the SIO B port is enabled for the TWX mode of operation at 862. The baud rate is input from the PIO at 864 and is output to the PIO at 866. The load point is loaded for the TWX message at 870 and the flow returns to the point of entry 670 (Figure 14).

Figure 20 illustrates the flow diagram for the Telex command 648 (Figure 14) and is similar to the DDD and TWX command flow diagrams of Figures 18 and 19. The counter timer 140 is enabled for the Telex mode of operation at 872 and at 874 the SIO B port is enabled for the Telex mode of operation. The baud rate is input from the PIO port B at 876 and is output to the PIO B port at 878 for the Telex rate. The load point is loaded for Telex at 880 and the flow returns to the entry point, 670 (Figure 14).

Figure 21 illustrates the clear command 658 (Figure 14) flow diagram. The clear command functions to clear security at 882 and to clear the modem at 884. The load point is loaded for a clear message at 886 and the flow is returned to entry point at 670 (Figure 14).

Figure 22 illustrates the private line command 652 (Figure 14) flow diagram. The data transmission speed is input at 890 and the new speed is set at 892. The counter timer 140 is then enabled for private line communication at 894 and the SIO B port is enabled for the private line mode of operation at 896. The input baud rate is selected from the PIO at 898 and is output to the PIO at 900. The load printer is loaded at 902 for a private message and the flow returns to the entry point 670 (Figure 14).

Referring to Figure 23, the half duplex command 668 (Figure 14) flow diagram is illustrated. In contradistinction to the setting of the mode word at one for full duplex operation (Figure 17) the mode word is set to zero for half duplex at 904 and the load point for a half message operation is loaded at 906. The flow returns to entry point 670 (Figure 14).

Figure 24 illustrates the status command 660 (Figure 14) flow diagram. This command inquiries from the CPU 64 (Figure 1 ) the curent status of the system and obtains a load word from the PIO B port at 920. A decision is made at 922 as to whether the data is Telex and if so, the load point is loaded for a Telex message at 924. If the data is not Telex, a decision is made at 926 to determine if the data is private line. If the data is private line, the load point is loaded at 928 for a private line message. If the data at decision 926 is not private line, a decision is made at 930 to determine whether the data is DDD. If the data is DDD, the load point for a DDD message is loaded at 932. Finally, if the data is TWX, the load point for a TWX message is loaded at 934.

The messages are loaded in memory through load points 924,928,932 and 934 and are output from these memory locations at 936. The phone number is then loaded into memory at 938 and is output at 940. The time and data are output at 942 and 944. The status command then loads a mode word at 946. A decision is made at 950 as to whether the mode word equals zero. If the decision is no, an output of a full message is made at 952 and if the decision is yes, an output of half duplex is made at 954. A decision is then made at 966 as to whether the security word is set. If the decision is yes, the security message is output at 960 and if the decision is no, the flow returns to the entry point 624 (Figure 14).

Figure 25 illustrates the time command 666 (Figure 14) flow diagram. The time command is used to reset internal clocks. The time is output at 962 and is reset at 964. The program then returns to the start one entry point 624 (Figure 14).

Figure 26 illustrates the date command 664 (Figure 14). The date is received at 966 and is reset at 968. The program then returns to the start one entry point 624 (Figure 14).

Figure 27 illustrates the phone command 662 (Figure 14). After initialization, the phone number was set to zero and is output at 980. A new phone number is input at 982. A decision is made at 984 to determine whether the input phone number consists of any character other than a number, a "-" or an "*". If the string does consist of an illegal character, an error message is output at 986. If the character string does contain all proper characters, the phone number is replaced with the new character string at 988 and the program returns to the Start 1 entry point at 624 (Figure 14).

Figure 28 illustrates the secure command 654 (Figure 14) flow diagram. The program loads a security word in RAM 68 (Figure 1) with a one at 990 and the numbers 1-5 are loaded in a random order into RAM 68 at 992.

A carriage return and line feed message is output at 994 and the security set message is output at 996. The program then returns to the start one entry point 624 (Figure 14).

Figure 29 illustrates the flow diagram of the dial command 644 (Figure 14). The dial command enables the software to dial a telephone number by operation of the software itself. The phone number stored in memory is recalled at 1000 and a decision is made at 1002 as to whether the phone number is a zero or an actual phone number present in memory. If the phone number is zero, the program returns to the start zero entry point 670 (Figure 14). If a number is other than zero, the incoming message lines are disabled at 1004 and the phone line is enabled to the modem at 1006. A decision is made at 1008 as to whether the modem is in error. If the modem lacks power, a clear is sent to the disabled line at 1010 and an error message is output at 1012. The program then returns to the start zero entry point 670 (Figure 14).

If the modem is not in error, the number is dialed at 1014. A decision is made at 1016 to determine if the line is busy and if not, the transmit/receive command program is enabled at 1018. If the line is busy, a retry counter is incremented at 1020 and a decision is made at 1022 as to whether the retry counter is overrun. If the retry counter is overrun, a busy message is output at 1024 and the program enters the enable point of entry at 755. If the counter is not overrun, the program returns to dial the number after a predetermined delay at 1014.

Figure 30 illustrates the transmit receive command 1018 software flow diagram. The message line is pointed to at 1030 and if the system is in the secure mode of operation, the message is scrambled at 1032. A decision is then made at 1034 to determine if there is an input from the port in the form of an answer back (ANSBACK), an end of text (EOT) or whether the input is transmit If the input is an answer back, an output is generated at 1036 and the program returns to the check message line pointed to at 1030. If the input is an EOT, the line in use is disconnected at 1038 and the program returns to the enable command point of entry 755. If the input is a transmit, the line is output to the port at 1040 and to the teleprinter at 1042. The line counter is incremented at 1044 and a decision is made at 1046 to determine whether the line count has been overrun.If the line count is overrun, the program returns to the scramble message entry point at 1032. If the line count is not overrun, the program returns to output the line to the port at 1040.

It therefore can be seen that the present communications processor automatically and selectively controls the interconnection of telecommunication systems via Telex, TWX, DDD and private line networks, in addition to providing accessory features such as data storage and editing capabilities. The present communications processor can be utilized in conjunction with a conventional input/output terminal to enable transmission of digital messages over a wide variety of communications channels.

Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Claims (37)

1. A system for selectively coupling an input terminal to any of a plurality of transmission lines each having different transmission speeds and characteristics comprising: means for being connected between the input terminal and said plurality of transmission lines and including decode means operable to selectively couple said input terminal to any one of said transmission lines, and an electronic digital processing means responsive to input address signals generated from said input terminal for being operated under the control of stored application programs for causing said decode means to couple said input terminal with an addressed one of said transmission lines for transmission of data thereover at the transmission speed associated with said addressed transmission line.

2. The system of Claim 1 wherein one of said transmission lines comprises a telephone line and further comprising: modem means for being connected between said terminal and said telephone line.

3. The system of Claim 1 wherein one of said transmission lines comprises a private transmission line.

4. The system of Claim 1 wherein one of said transmission lines comprises a digital data transmission line.

5. The system of Claim 4 wherein said digital data transmission line comprises a Telex line.

6. The system of Claim 4 wherein said digital data transmission line comprises a TWX line.

7. The system of Claim 1 wherein said terminal includes a keyboard operable to generate said input address signals.

8. The system of Claim 1 and further including data storage means for storing input data generated from said input terminal, and said electronic digital processing means responsive to input edit signals generated from said input terminal for operating under the control of stored application programs for modifying data stored within said storage means in order to allow selective editing of said stored data.

9. The system of Claim 8 wherein said terminal includes a keyboard operable to generate said input data and input address signals.

10. A system for selectively coupling an input/output terminal having a keyboard and an output display to any of a plurality of transmission lines each having different transmission speeds and characteristics comprising: means for being connected to the in put/output terminal for receiving transmission line selection signals input through the terminal keyboard, storage means for storing a plurality of application programs, each of said application programs corresponding to a different one of the transmission lines, a microprocessor responsive to said selection signals for addressing a selected application program in said storage means, line decode means operable to couple any designated one of the transmission lines to said terminal, said selected application program controlling the operation of said microprocessor to cause said line decode means to couple the selected transmission line to said terminal to enable the transmission of data thereover.

11. The system for selectively coupling an input/output terminal defined in Claim 10 and further comprising: said microprocessor being responsive to dialing signals input through the terminal keyboard for storing said dialing signals in said storage means, and said microprocessor operable under the control of said selected application program to transmit said dialing signals from said storage means over the selected transmission line.

12. The system for selectively coupling an input/output terminal defined in Claim 11 and further comprising: filter means for receiving dialing signals from the selected transmission line, and means interconnected to said filter means for coding said received dialing signals for application to said microprocessor.

13. The system for selectively coupling an input/output terminal defined in Claim 12 wherein said means interconnected to said filter means receives coded dialing signals from said microprocessor for decoding and for application to said filler means, and said filter means applies said decoded dialing signals to the selected transmission line.

14. The system for selectively coupling an inputloutput terminal defined in Claim 10 wherein said selected application program controls the operation of said microprocessor to cause an acknowledge indication to be displayed on the output display of the terminal to indicate the selection of the desired transmission line.

15. The system of Claim 10 wherein one of said transmission lines comprises a telephone line and further comprising: modem means for being connected between said terminal and said telephone line.

16. The system of Claim 10 wherein one of said transmission lines comprises a private transmission line.

17. The system of Claim 10 wherein one of said transmission lines comprises a digital data transmission line.

18. The system of Claim 10 wherein said digital data transmission line comprises a Telex line.

19. The system of Claim 10 wherein said digital data transmission line comprises aTWX line.

20. The system of Claim 10 and further comprising: means for receiving and storing data transmitted via the selected transmission line to the terminal, and means for transferring said stored data to the output display of the terminal.

21. The system of Claim 10 wherein said selected application program controls the baud rate of data transmission from said terminal, said application programs enabling data transmission over different ones of the transmission lines at different baud rates.

22. The system of Claim 10 and further including data storage means for storing input data generated from said input terminal, and said electronic digital processing means responsive to input edit signals generated from said input terminal for operating under the control of stored application programs for modifying data stored within said storage means in order to allow selective editing of said stored data.

23. The system of Claim 22 wherein said terminal includes a keyboard operable to generate said input data and input address signals.

24. A system for selectively coupling a teleprinter having an input keyboard and an output printer to any of a plurality of transmission lines each having different transmission speeds and characteristics comprising: serial l/O means for being connected to said teleprinter for receiving transmission line selection signals input through the keyboard, a digital microprocessor connected to said I/O means, storage means associated with said microprocessor for storing a plurality of application programs, each of said application programs corresponding to a different one of said transmission lines, said microprocessor responsive to said transmission line selection signals for addressing one of said application program line decode means connected between said microprocessor and the plurality of transmission lines, said line decode means operable under the control of said microprocessor and said addressed application program for coupling the selected transmission line for communicating data with the teleprinter, said storage means receiving and storing dialing data from the teleprinter keyboard, and said microprocessor, under the control of said addressed application program, causing said dialing data to be transmitted from said storage means and through said line decode means to the selected transmission line.

25. The system of Claim 24 wherein said transmission lines comprise: at least one telephone line and at least one digital data transmission line.

26. The system of Claim 25 wherein said telephone line comprises a DDD telephone line.

27. The system of Claim 25 wherein said digital data transmission line comprises a Telex line.

28. The system of Claim 24 wherein said storage means comprises a read only memory for storing said application programs.

29. The system of Claim 24 wherein said storage means comprises a random access memory for storing said dialing data.

30. The system of Claim 24 and further comprising: means for receiving and storing data transmitted via the selected transmission line to the teleprinter, and means for transferring said data to the output display of the teleprinter.

31. The system of Claim 24 and further including data storage means for storing input data generated from said input terminal, and said electronic digital processing means responsive to input edit signals generated from said input terminal for operating under the control of stored application programs for modifying data stored within said storage means in order to allow selective editing of said stored data.

32. The system of Claim 31 wherein said terminal includes a keyboard operable to generate said input data and input address signals.

33. A method for selectively coupling a teleprinter to any of a plurality of transmission lines each having different transmission speeds and characteristics comprising: receiving input address signals from the teleprinter, in response to said input address signals, operating a digital processor in accordance with a stored application program for coupling said teleprinter with an addressed one of said transmission lines, and transmitting data from the teleprinter over the addressed one of said transmission lines at the transmission speed and with the characteristics associated with said addressed transmission line.

34. A method for selectively coupling an input/output terminal having a keyboard and an output display to any of a plurality of transmission lines each having different transmission speeds and characteristics comprising: receiving transmission line selection signals from the terminal input through the terminal keyboard, storing a plurality of application programs, each of said application programs corresponding to a different one of the transmission lines, addressing a selected stored application program in response to said selection signals, and coupling under the control of the selected application program the selected transmission line to said terminal to enable the transmission of data thereover.

35. The method of Claim 34 and further comprising: storing dialing signals input through the terminal keyboard, and transmitting said dialing signals over the selected transmission line.

36. The method of Claim 34 wherein said selected application program controls the operation of said microprocessor to cause an acknowledge indication to be displayed on said output display.

37. The method of Claim 34 and further comprising: transmitting data from said terminal over any selected one of a Telex line, TWX line, DDD telephone line or a private line. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~