GB2027567A - Electronic generation of an analogue clock face on a television - Google Patents

Abstract

A circuit generates signals representing an analogue clock face having a circular dial with minutes markers and at least one rotating hand. The hand is produced by mixing line and field rate ramps in differing proportions in a mixer 202 and applying the mixed ramps to Exclusive - OR gates E - OR having differently thresholded pairs of inputs. The output of each gate (Figure 2a) is selected by circuit 208 at a rate of one per second, and a blanking circuit 209 ensures that a line appears in only one quadrant at a time. The circular dial is generated by integrating the line and field rate ramps in circuits LP, FP and mixing them in mixer 212. The mixed parabolic signals are applied to a circle generating circuit comprising two voltage comparators having thresholds modulated by signals LIM, LOM, and SIM.FQ derived from the outputs of the gates E-OR whereby markers are produced. Blanking circuits to blank part of the dial and to define the length of the hand are provided. <IMAGE>

Description

SPECIFICATION Electronic generation of an analogue clock display on television The present invention relates to the electronic generation of an analogue clock display on television.

The display of an analogue clock face on television has, until now, required a mechanical clock, lighting, and a television camera. This arrangement is expensive and bulky.

A VTR leader clock, usually consists either of a portable mechanism held in front of a camera, or of a unit, comprising a camera and a mechanical clock, housed with the studio electronics.

These mechanical analogue clocks tend to be cumbersome and unreliable.

It is an object of the present invention to provide apparatus for electronically generating an analogue clock face.

According to one aspect of the invention, there is provided: a circuit for use in an apparatus for synthetically generating an analogue clock face on the screen of a television, the circuit comprising means for generating signals for causing the production on the screen of transitions between light and dark regions at respective ones of a plurality of angles, means for selecting the signals at a predetermined rate, and blanking means for producing signals to cause blanking of selected regions of the screen.

According to another aspect, there is provided apparatus for electronically generating an analogue clock face on a television, including: means for generating line and field rate ramp signals, means for mixing the said line and field rate ramp signals in varying proportions, means for deriving from the mixed ramp signals a plurality of further signals for causing the production on the television of transitions between light and dark regions at respective angles defined by the said proportions, and means for selecting the said further signals at a predetermined rate.

In an embodiment of the apparatus, the deriving means comprises: means for comparing the mixed ramp signal produced in response to each of the various proportions with two differing threshold levels and for producing a said further signal when that mixed ramp signal has a level between the two threshold levels.

These means allow the generation of hands of width dependent on the difference between the thresholds. The hands are selected by means to produce the appearance of a rotating hand.

Another embodiment of the apparatus comprises: means for generating parabolic waveforms from the said ramp signals, and means for mixing the parabolic waveforms.

These means allow the generation of a circular scale.

According to another aspect of the invention, there is provided a reference circuit comprising an input for receiving an input signal of varying peak voitage, an output, means for detecting the peak voltage of the input signal, means for deriving from the detected peak voltage a further voltage which is greater than the peak voltage buy a predetermined amount, and for maintaining one side of the output at the further voltage, and means for maintaining the other side of the output at a predetermined potential difference relative to the said one side.

For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which: Figure 1 illustrates an exemplary clock face generated on a TV screen by exemplary apparatus in accordance with the invention;; Figure 2 is a block diagram of a circuit for producing signals indicating which of four quadrants of the screen is being scanned at any instant in time, and for producing signals for generating the clock hands, Figure 2a illustrates the output of part of the circuit of Figure 2, Figure 3 is a block diagram of a quadrant blanking circuit and of a circuit for producing address signals for the clock hand generating circuit, Figure 4 is a block diagram of a circuit for producing signals for generating the clock scale, and for blanking the scale, Figures 4a to h illustrate the outputs of various parts of the circuit of Figure 4, FigureS is a block diagram of a circuit for presetting the indicated time, Figure 6 shows in detail the circuit of Figure 2 for producing signals indicating which of the four quadrants is being scanned, Figure 7shows in detail another portion of Figure 2, Figure 8a to e are timing diagrams, Figure 9 shows in detail the voltage reference circuit of Figure 4, and Figure 10 shows in detail the 1 of 4 selector of Figure 2.

In the Figures, some of the circuit blocks contain numbers beiginning 74. These numbers are the numbers used by Texas Instruments to identify that circuit as made by them.

The circuits shown in Figures 2 to 9 are arranged to electronically generate on a television screen a clock face as shown in Figure 1. This particular clock face is designed to indicate time in seconds before the start of a programme recorded or to be recorded on a video tape recorder.

The clock comprises a single hand displayed on the screen which rotates in the usual way between an inner ring 2 and a circular scale 3. The scale comprises, in addition to a sector of the circle, large outer markers, LOM, larger inner markers LIM, and small inner markers SIM. A portion 4 of the scale 3 comprises only segments of the sector of the circle.

The screen itself is notionally divided into four quadrants LQ, FQ LQ FQ, LQ.FQ and LQ.FQ.

The scale 3, the inner ring 2 and the hand -1 are displayed in this example as white on a black background, although they could be displayed as black on a white background. Furthermore, in practice, numerals e.g. 40,30,20, 15,10 and 5 and other information e.g. FADE IDENT, would normally be displayed on the screen with the clock face; however this may be done in a known manner and thus will not be described herein.

In operation before the start of a programme to be recorded, the clock hand is set to a time, e.g. - 40 seconds. The hand then rotates in discreet 1 second increments. As is conventional in recording programmes, between 20 and 15 seconds (portion 4 IDENT) the programme may be identified by recording on a sound track the title of the programme. At 10 seconds the whole screen flashes white and tone bursts are produced on an audio channel for use in synchronising the audio and video recordings and at 3 seconds (FADE) the whole screen is made black (this flashing, fading and tone burst production is not part of the present invention and will not be described herein).

Production ofa rotating hand The principle of production of a hand in a single fixed position on the screen is as follows: Line and field rate ramps LRR and FRR are additively mixed together and presented to an Exclusive - OR gate having different threshold levels at its two inputs. The gate will produce an output of one state only when the input levels are different and of the other state only when the input levels are the same. If the output of the gate is displayed on a TV screen, with the mixed line and field rate ramps synchronous with the line and field rate ramps of the TV, a diagonal line is produced on the screen and the width of the line is dependent on the difference between the threshold levels at the inputs on the gates.The line covers two diagonally opposite quadrants e.g. LQ.FO and LQFQ, of the screen, and the angle of the line is dependent on the relative proportions of the line and field rate ramps.~~~ In order to cover the other two quadrants LQ.FQ, LQ.FQ the phase of the line or of the field rate ramp must be inverted, and in order to rotate the line, the proportions of the line and field rate ramps must be varied.

The circuit of Figure 2 uses this principle in the following way: Mixed blanking signals from a sync. pulse generator SPG are fed to an L, Fseparatorto produce line clock signals Land field clock signals F having the form shown in Figure 8d. The line clock signals Land the field clock signals F (which signals F are derived from an inverter 201) are fed to line and field ramp generators LR and FR to produce the line and field rate ramps LRR and FRR.

The line rate ramp LRR is fed to one side of a mixing circuit 202 via a phase inverting circuit 203.

The circuit 203 comprises an inverter 205, and an electronic line ramp switch 204 (illustrated as a mechanical switch) having two inputs, one of which is connected to receive the line rate ramp via the inverter and the other of which is connected to receive the line rate ramp directly. The switching means 204 is controlled by a line rate ramp switch control signal LRS so that the line rate ramp has one phase (relative to the field rate ramp) when a hand is to be displayed in the quadrants LQ.FQ and LQ.FQ, and the opposite phase when a hand is to be displayed in the other two quadrants.

The field and line rate ramps are additively mixed in different proportions in fourteen potential dividers 206 (only two shown in Figure 2) which form the mixing circuit 202, and the fourteen mixed ramps are applied to respective clipping amplifiers 207 (shown in detail in Figure 7). The outputs of the amplifiers 207 are connected to respective two-input. Exclusive - OR gates E-OR. Each gate E-OR has a diode connected to one input so that the threshold levels at its two inputs are different.

If the output of one of the Exclusive-OR gates E-OR was displayed on a TV, one field of the resulting picture would appear as shown in inset Figure 2a.

The X-shape, comprising four hands, arises because of the phase inversion of the line rate ramp as different quadrants are scanned. Different gates E-OR would produce X-shapes with the diagonals at different angles due to the different proportions of mixing of the ramps. This gives a total of 56 hand positions, and the remaining four hand positions, those in the horizontal and vertical directions, are produced by two further Exclusive - OR gates E-OR L and E-OR F are provided. E-OR L is connected to receive the line rate ramp alone, and E-OR F is connected to receive the field rate ramp alone.

If the outputs of these gates were displayed the output of the gate E-OR L would produce a vertical line (two hand positions), and the output of the other gate E-OR F would produce a horizontal line.

If the outputs of the fourteen gates E-OR and the two gates E-OR L F were all displayed together they would cause the production on the screen of a vertical and a horizontal line between the quadrants and fourteen pairs of diagonal lines (i.e. 14 Xs) with neighbours spaced by 6" (corresponding to a time increment of 1 second) in each field and so would all appear to be simultaneously present on the screen.

Cleariy, to simulate the moving hand of the clock, only one hand should appear in only one quadrant of the screen in each second oftime.

Therefore the outputs of the gates E-OR and E-OR are fed in parallel to a 1 in 16 selector 208 which selects those outputs according to addresses fed to it. Each selected outputwould, if displayed, cause the production of an X (four hands) on the screen (i.e. hands in all four quadrants) so the portions of the selected output which would cause the display of hands in quadrants inappropriate to the time to be displayed are inhibited, (This process is referred to herein as quadrant blanking).

Address Generation The circuit for producing the addresses for the selector 208 is shown in Figure 3. The field clock signai F, which occurs 50 times per second, is fed to a divide-by-fifty divider 301 to produce clock signals at a rate of one per second. The clock signals are fed to the clock input CK of an up/down counter 302, having a maximum count of 15, which produces the addresses. Assuming the counter is initially counting up, when it reaches its maximum count it produces a signal at its MAX/MIN output which changes the state of a bistable F1 which thus produces a signal which is fed to the DOWN/UP input of the counter causing the counter to reverse its counting direction and count down. The bistable F1 holds its state for 15 seconds until the minimum count is reached whereupon it changes state and causes the counter to count up again.The counting proceeds upwards when hands are to be displayed in the quadrant LQ.FQ and downwards in the quadrant LQ.FQ. The state of F1 for a succession of fifteen second counting periods is shown in Figure 8a.

In this way the outputs of the gates E-OR and E-OR1 are selected at a rate of one per second and in a pattern which causes, together with quadrant blanking, a simgne hand to apparently retate clockwise around the clock face.

Before decribing the quadrant blanking, it is necessary to describe how the quadrants are indicated.

Quadrant Indication Referring to Figures 2 and 6, the line and field clock signals L and F produced by the L, Fseparatorare fed to a quadrant indicator 209 together with the mixed blanking signal SPG. Referring to Figure 6, the indicator 209 comprises two monostable multivibrators 601, 602 connected to receive the signals F and L respectively and a D-type edge triggered bistable 603 connected to receive the output of the monostable 601 and the blanking signal SPG via an inverter 604. Monostable 601 is edge-triggered and monostable 602 is level-triggered. The monostable circuits 601 and 602 have external circuits 605 and 606 for defining the duty cycle of the signals they produce in response to the signals F and L. The D-type bistable synchronizes the output of 601 with the blanking signal SPG.

Referring to Figure 8e, the line clock signal L has a certain state for the whole of a line time across the display screen DS. The monostable 602 produces in response to La signal LQ which has one state for one half of the line time and the opposite state for the other half. That monostable also produces a signal LQ which is the reverse of LQ.

Similarly, the monostable 601 and the bistable 603 together produce in response to the frame clock signal F, a signal FQ having one state for one half of the frame time and the opposite state for the opposite half, and its inverse FQ.

Thus, because they will be synchronized with the scanning of the screen DS as shown in Figure 8e, the signals FQ, FQ, LQ, LQ together indicate at any time the quadrant of the display screen DS which is being scanned at that time. FQ and FQ denote the top and bottom halves of the screen and LQ and LQ the left and right halves. The signal LQ is fed to a delay circuit 210 which, as shown in Figure 6, comprises a delay network 606 and two inverters 607 and 608 in series. The delay circuit produces delayed signal LQ(D) and LQ(D). These delayed signals are required because the selection of the quadrants must be synchronized with the switching of the phase of the line rate ramps, and this synchronisation is affected by delay in the circuit.

The signals FQ, FQ, LQ(G),LQ(D), LO and LQ are used throughout the circuits shown in Figures 2,3,4 and 6. One example oftheir use is in the-production of the line ramp switch control signal LRS.

Line Ramp Switch Control The line ramp switch control signal is produced by a line ramp switch control 211 (figure 2) which as shown in Figure 6 comprises two AND gates 609 and 610 connected to a NOR gate 611. The AND gate 610 is connected to receive FO and LO and the AND gate 611 is connected to receive FQ and LQ. The NOR gate outputs the signal LRS which has one state for quadrants LQ.FQ and LQ.FQ and the-other state for quadrants LQ.FQ and LQ.FQ, corresponding to the phase switching ofthe line rate ramp LRR.

Quadrant Blanking The output of the selector 208, if displayed would cause the display of a sequence of X-shapes rotating clockwise whereas, as previously mentioned, only a single hand is required, in a single one of the quadrants, at any one time.

Thus, the three portions of the output of the selector 208 inappropriate to the quadrant in which the desired single hand is to be displayed at any time are inhibited at that time. This inhibiting process is called blanking hereinafter. In other words at any time, the blanking circuit blanks 3 of the four limbs of each X-shape which would otherwise be displayed and blanks the unwanted halves of the vertical and horizontal lines which would be displayed in response to the outputs of the gates E-OR1.

The quadrant blanking circuit is shown in Figure 3.

It allows only selected portions of the output (HANDS) of the selector 208 to pass to the output of a NAND gate 303 at anytime.

The other portions are blanked. In addition to the NAND gate 303, the blanking circuit comprises the bistable F1,two further bistables F2 and F3, a quadrant selection circuit 304, a blanking inhibit circuit 305, and an inhibit control circuit 306.

The bistables F2 and F3 are clocked by the Q(F 1) andQ(T1) outputs respectively of the bistable F1 to product outputs F2,F2 and F3,F3. The relationships of these outputs F1, F2, F3 to each other is shown in Figures 8a, b, and c.

The outputs F2, F2 and F3,F3 are applied to the quadrant selection circuit 304 together with the quadrant indicating signals FQ, FQ, LQ and LQ. The outputs F2, and2 cause the circuit 304 to select LQ and LQ respectively and the outputs F3 and F3 cause the circuit to select FQ and FQ respectively. Ignoring for present the action of the AND gates 306 and 307 of the circuit 305, the selected quadrant indicating signals are combined by the NOR gate 308 of the circuit 305 and applied to the QUADRANT BLANK ING input of the NAND gate 303.

The bistables F2, F3 and the circuits 304 and 305.

act so that during the period of time when a sequence of hands is to be displayed in a particular quadrant, e.g. FQ.LQ the quadrant indicating signals appropriate to that quadrant e.g. FQ and LQ are selected (by F3 and F2) and combined and applied to the NAND gate 303. The combined quadrant indicating signals (FQ. allow only those portions of the output (HANDS) of the selector 208 appropriate to the selected quadrant to pass (inverted) to the output of the NAND gate. All other portions (appropriate to the unselected quadrants) are inhibited or blanked.

It is undesirable to selectquadrantsto blankthe output of the gates E-OR'F and L (which if displayed would cause the display of vertical and horizontal lines between the quadrants), because half the width of each of these lines would then be blanked.

Therefore the blanking inhibit circuit 305 and the inhibit control circuit 306 are provided.

The control circuit 306 comprises a bistable 310 which produces a state Ofor 1 second in response to the receipt of a signal from the counter 302 indicating maximum or minimum count (i.e. selection of the output of one of the gates E3OR) and a clock signal from the divider 301. In other words it detects when a hand is to be displayed in a vertical or horizontal position. The state 0 enables the NAND gates 311 and 312 to inhibit one of the AND gates 306 and 307 selected according to the state of bistable F1 and so the NOR gate 308 merely inverts whichever one of FO, FO, LQ orWis passed by the AND gate 306 or 307 which is not inhibited.

Thus, for a vertical hand, only those portions of the output of the selector 308 appropriate to the top FO, or bottom FQ half of the screen are blanked, and for a horizontal hand only these portions of that output appropriate to the left LO or right LQ half of the screen are blanked.

Generation of Circular Scale The principle of generating a circle is to integrate the line and field rate ramps LRR and FRR to form parabolic waveforms, additively combine them, and present the combined waveforms to two voltage comparators having different thresholds. By combining the outputs of the comparators and displaying the combined outputs a circular line is produced, the width of line being dependent on the difference between the thresholds.

In order to implement this principle, referring to Figure 2, the line and field rate ramps LRR and FRR are applied to integrators LP and FP to form line and field rate parabolic waveforms. These parabolic waveforms are additively mixed in a mixer 212.

Referring to Figure 4, the mixed parabolas are fed to two voltage comparators 401 and 402 having different thresholds derived by threshold setting resistors 403 and 404 from a voltage applied to them by a voltage reference circuit 405 (which will be described in detail hereinafter). The outputs of the comparators are combined by a wired - OR gate 406 comprising two open-collector inverters 407 and 408.

In order to produce the inner and outer markers on the circular scale, the thresholds of the comparators are modulated, thus varying the width of the circular line.

This modulation is achieved in the following way.

Referring to Figure 2, a wired - OR gate 213 comprising open-collector inverters 214 is connected to receive the outputs of the gates E-OR Land F and of two of the gates E-OR to provide output signals corresponding to hands in the 0,5, 10 and 15 positions (and thus also to the corresponding positions in all the quadrants). These outputs are used to produce the large inner markers LIM which occur at the corresponding positions on the circular scale. All the other gates E-OR (producing signals correspond ingto handsinthel,2,3,4,6,7,8,9, 11,12,13, and 14 and corresponding positions in other quadrants) are connected to another wired - OR gate 214 comprising open-collector inverters 215 (only one shown in Figure 2). The output of the OR-gate 214 is used to produce the small inner markers SIM.

The signals for producing the large outer markers LOM are produced by selecting circuit 216 connected to receive the outputs of the gates E-OR'Fand L(0 and 15 positions) and the outputs of the two gates E OR producing signals corresponding to hands in the 3 and 10 (and other corresponding) positions.The circuit 216, which is shown in detail in Figure 10, selects the signals for producing large outer markers according to address signals comprising LQ and FO, in the following manner:- FO (corresponding to the top half of the screen) selects the large outer marker signals corresponding to the 0 and 3 positions in the quadrants LQ.FQ and LQ.FQ; LQ (the left half of the screen) selects the large outer marker corresponding to the 15 position; and FQ (the bottom half of the screen) selects the large outer marker signal corresponding to the 20 and 40 second positions in the quadrants LQ, FQ, and LQ.FQ in the bottom half of the screen.

The small inner markers SIM are required in only the top half of the screen. They are thus applied, in the inverted form SIM, to a NOR gate (Figure 4)409 together with the signal FO. This gate 409 produces signals SIM.FQ corresponding to the small inner markers SIM in the top half (FQ) of the screen: If the output of the wired - OR gate 406 were displayed on a TV screen it would appear as shown in the inset Figure 4c (and also in Figure 1), Accordingly, the unwanted portions of the scale are blanked.

Scale Blanking The scale blanking circuit is denoted in Figure 4 by reference numeral 410. It comprises four OR gates 411,412,413and414,2 NAND gates 415 and 416, an open-collector inverter 417, a NOR gate 418 and a NAND gate 419.

The NOR gates are connected to receive signals as shown in Figure 4. Of these signals, 0 is the output of the gate E-OR L (Figure 2) and 15 is the output of the gate E-OR'F.10X is a signal derived from between the diode and that input connected thereto of the gate E-OR for producing the signal for producing a hand in the 10 (and other corresponding) positions.

If the signal 10X were displayed on a TV screen it would produce a pattern as shown in inset Figure 4d, where the cross-hatching denotes black.

The circuit 410 would, if its output were displayed, produce a blanking pattern as shown in inset Figure 4b, where the cross-hatching denotes black, and the lines 420 represent white, and are produced in response to the signal SIM. The NAND gate 419 combines the blanking pattern with the scale so that if its output were to be displayed it would produce a blanked scale as shown in Figure 4c.

The circuits as so far described produce the required scale 3 and a hand 1 which rotates.

However, as shown in Figure 1, an inner ring 2 is required and the hand 1 must be of the shown length in relation to the scale 3 and the ring 2.

Hand Length Blanking The outer extent of the hand is defined by a hand length blanking circuit 420 shown in Figure 4. It comprises a voltage comparator connected to compare the mixed parabolas signal with a threshold voltage. Its output signal HB is applied to the NAND gate 303 (Figure 3) to allow only those portions of the HANDS signal appropriate to the required length of hand to pass (inverted) to the output of the gate 303. If displayed on a TV screen the hand blanking circuit would produce a display as shown in inset Figure 4, where the cross-hatching denotes black.

The circuit 420 only blanks the radially outer portion of the hand. In order to blank the portion of the hand within the inner ring 2, a.hand centre blanking 421 is provided.

Hand Centre Blanking The hand centre blanking circuit 421 comprises a voltage comparator connected to compare the mixed parabolas signal with a threshold voltage. Its output is also applied to the NAND gate 303 (in Figure 3). If its output were displayed it would appear as shown in Figure 49, where, again, the cross-hatching denotes black.

Inner Ring In order to generate the inner ring the mixed parabolas signal is applied to a voltage comparator 422 where it is compared with a threshold different to that applied to the comparator 421.

The outputs of the comparators 421 and 428 are applied to an OR gate 423. If the output of the OR gate were displayed it would appear as a white ring on a black background as shown in Figure 4h. The output IR is applied together with the BLANKED SCALE output of NAND gate 419 and the output of NAND gate 303 to a NAND gate 311 (Figure 30 which combines them. The output of gate 311, when displayed, produces the clock face shown in Figure 1 (apart from the letters and numbers).

Time Presetting The clock can be preset to start at a selected time of 20,40 or 60 seconds.

The circuit for performing this function is shown for completeness in Figure 5. It comprises the arrangement of AND gates, a NAND gate and an inverter shown in Figure 5.

The presetting is controlled by applying time setting signals -40, -60-20, from a keyboard to the inputs -40, -60, -20 of the circuit of Figure 5.

The circuit presets the state of the counter 302 (Figure 3) via data inputs B and D and the LOAD input to produce the address for selecting the hand for indicating the desired time setting, sets the states of the bistables F1, F2 and F3 to select the quadrant appropriate to that time setting, and also actuates a startistop circuit to start the clock.

The StartlStop Circuit The start/stop circuit is shown in Figure 3 and comprises bistable SS, and a NAND gate 312. The bistable SS receives at its input CL a start signal from the start output ST6 of the time setting circuit when anyone of the time presetting signals *40, -60, -20 is Tois produced. This sets the state of the bistable, which then starts the counter via its start input Q (SS).

It is necessary to stop the clock once the hand reaches zero. Referring to Figures 8a, b, c, when the hand is in the zero position F1, F2 and F3 are all low.

The gate 312 senses this and changes the state of the bistable SS via input CK, thus stopping the counter 302.

The Voltage Reference Circuit The voltage reference circuit 405 of Figure 4 is the source of the threshold voltages for the scale generating circuit, the hand blanking circuit 420, the hand centre blanking circuit 421, and the inner ring generator 421 and 422. This circuit is shown in Figure 9. It provides a reference voltage which is fixed in relation to the peak voltage of the mixed parabolas signal. Although that signal can be stabilised to a certain extent its peak nevertheless varies both in amplitude and in its d.c. bias. This circuit is important in that it allows the whole clockface generator to be made economically.

The circuit operates in the following manner: The mixed parabolas signal is a signal of negative voltage. A transistor the base of which is connected to receive the signal, is conductive whilst the voltage of the signal becomes increasingly-negative, and the voltage on a capacitor C1 follows the signal voltage. Once the peak (negative) voltage -Vp occurs and the signal voltage begins to become less negative, the transistor T1 is rendered non-conductive leaving the peak voltage -Vp on the capacitor C1.

A transistor T2 acts as a high impedance buffer sensing the voltage on the capacitor C1 without drawing a substantial current from it. The voltage at point C is therefore substantially equal to-VP. A zener diode Z1 sets a fixed voltage difference between VZ between a point B and the point C so that the voltage at point B is -(Vp + VZ1) (i.e. more negative than Vp).

A transistor T3 acts as a further buffer so the voltage at point A is substantially equal to that at B and sets the voltage of the negative rail RN of the output O/P of the circuit. A zener diode Z2 fixes the voltage of the positive rail RP Df the output in relation to the negative rail.

Thus the circuit provides a fixed potential difference between the rails RP and RN of its output, which potential difference is applied as shown in Figure 4 to the threshold setting resistors (such as 404) of the scale generating circuits, and the circuits 420, 421 and 422. This fixed potential difference is fixed relative to the varying peak voltage of the mixed parabolas signal.

Although the foregoing describes an example of the invention which generates a clock face having only one hand for giving the time in seconds, the invention is not limited to that.

As will be clearto those skilled in the art the time in minutes or hours could be displayed by the single hand simply by altering the rate at which addresses are fed to the selector 308.

Furthermore, two hands could be simultaneously displayed to indicate the time in hours and minutes.

Afurther hand could be displayed to indicate the time in seconds.

Alternatively, a circular scale could be successively blanked to display a "disappearing" clock in which the displayed angular sector of the scale reduces with time. This would be achieved using signals generated by the hand generating circuit in a similar way to the scale blanking circuit. Such a clock would have no hands.

As another alternative a clock face having a hand or hands but no scale could be displayed.

Although the invention has been described in relation to a VTR leader clock, the invention could be used to generate an analogue clock for displaying the time on a television in public places such as railway stations or airports, or even on televisions in homes.

Furthermore, as will be apparent to those skilled in the art, the clock could be displayed in colour, different parts being of different colours.

Claims (10)

1. A circuit for electronically generating signals representing an analogue clock face for display on a television screen, comprising means for producing first signals representing regions of different appearance on the screen with linear boundaries between the regions, the boundaries being at respective ones of a plurality of different angles, means for selecting the first signals at a predetermined rate, and in a predetermined order, means for producing second signals representing regions of different appearance on the screen with a closed boundary therebetween means for producing third signals indicating respective quadrants of the screen, blanking means responsive to the third signals and responsive to the first signals and/or the second signals to produce blanking signals for inhibiting the display of the first and second signals at predetermined times, and means for combining the third, and blanking signals with the first and/or second signals.

2. A circuit according to claim 1, wherein the means for producing first signals includes means for producing a line rate ramp signal means for producing a field rate ramp signal, and a plurality of means for adding the line and field rate ramp signals in different proportions.

3. A circuit according to claim 2, further comprising a plurality of Exclusive - OR gates each having a pair of inputs with different thresholds thereat, the pairs of inputs being connected to respective ones of the adding means.

4. A circuit according to claim 3, wherein the selecting means selects the outputs of the Exclusive - OR gates.

5. A circuit according to claim 2, or 3, wherein the blanking means includes at least one means having inputs coupled to the means for producing third signals and to the output of at ieast one of the adding means of the first signal producing means, to derive a blanking signal therefrom.

6. A circuit according to claim 1,2,3,4, or 5, wherein the means for producing the second signal includes means for integrating the line rate ramp signal to produce a line rate parabolic signal, means for integrating the field rate ramp signal to produce a field rate parabolic signal, means for adding the parabolic signals, first means for comparing the added parabolic signals with a first threshold, second means for comparing the added parabolic signals with a second threshold, and means for combining the outputs of the first and second comparing means.

7. A circuit according to claim 6 when appended to claim 3 or 4, wherein the first and second comparing means each include a first input for receiving the added parabolic signals, and a second input for receiving the threshold, and wherein there is further provided means for producing fixed thresholds for the respective inputs, and means for producing further thresholds derived from the outputs of the Exclusive - OR gates for application to the inputs.

8. A circuit according to claim 6 or 7 wherein the blanking means includes means for comparing the added parabolic signals with a threshold.

9. A circuit according to claim 7 or 8, wherein there is provided a reference circuit for providing the or each threshold, the circuit comprising an input for receiving an input signal of varying peak voltage, an output, means for detecting the peak voltage of the input signal, means for deriving from the detected peak voltage a further voltage which is greater than the peak voltage by a predetermined amount, and for maintaining one side of the output at the further voltage, and means for maintaining the other side of the output at a predetermined potential difference relative to the said one side.

10. A circuit for electronically generating signals representing an analogue clock face for display on a television screen substantiaily as hereinbefore described with reference to the accompanying drawings.