GB2027314A - Video recording time-error correction circuit - Google Patents

Abstract

A circuit for correcting timing errors when reproducing video signals comprises an analogue shift register for passing the video signals, the delay time of which is varied by varying the frequency of a control oscillator, which frequency is regulated by a phase comparator 12, 20 comparing the line pulses 7, separated out at the register output, with reference pulses 9. In order to achieve stabilisation quicker after any disturbance, the error voltage is averaged over several lines by RC network 15, 16, 18, so that the error signal resulting from any disturbance, and appearing on a capacitor 21, reduces towards the average error voltage, through resistor 22, during each line period. <IMAGE>

Description

SPECIFICATION Video recording time-error correction circuit This invention relates to a circuit for the correction of time errors such as occur in connection with video recording.

During the reproduction of video signals recorded magnetically or otherwise, time errors generally occur which originate from minor inaccuracies or alterations both in the individual instruments and in the recording medium itself and as such are inevitable.

Machines for the reproduction of video recordings are therefore equipped with separate circuits for the correction of time errors, which, despite their very great differences in construction, ultimately all have to contain a buffer network, that is to say a store, in which the time errors are collected and compensated for. Such buffer networks may consist of controllable delay-line networks or of analogue shift registers, of which the latter are acquiring even more importance for reasons of cost.

Analogue shift registers, for example in the form of the so-called bucket brigade circuit or in the form of charge-coupled devices (CCD) allow the signals fed in the pass to a speed which is proportional to an applied timing frequency. Consequently time-error correctors with analogue shift registers work so that the line synchronizing pulses separated out of the scanned video signals are compared in phase with a reference frequency and that the timing-frequency oscillator for the shift register is controlled by the resulting error signal. In this case, however, very specific difficulties arise, according to whether the phase comparison is effected before or after the shift register.

If the line pulses are compared in phase with the reference pulses before the shift register, that is to say a forward control is used, then admittedly the time error can be completely eliminated with a precise adjustment, nevertheless since for example if a line duration is found to be too long, it is not the frequency but the period duration, that is to say the reciprocal value of the frequency of the timing oscillator, which has to be reduced in proportion, non-linear harmonic generators have to be provided between the output of the phase comparator and the control input of the timing oscillator (see the published specification of German application 2 329 357).In addition, the requirements regarding the constancy and reproducibility of these harmonic generators, as well as of the phase comparator, the amplifier and the timing oscillator, must be high, because it is a question of a fixed programmed control and not a closed control loop.

These difficulties are absent if the line pulses are compared in phase with the reference pulses after the shift register because now there is a closed control loop. On the other hand, however, a residual time error remains because the control steepness of the control loop cannot be made infinitely great.

Since a phase comparison takes place in rhythm with the line frequency, that is to say only every 64 ys, with a low control steepness several scanning periods are necessary after a disturbance in order to achieve coincidence again between time deviation and register timing, while with a high control steepness, the circuit tends to oscillate and only slowly becomes steady. This is illustrated in Fig. 1: if a single disturbance occurs at the moment t,, then the phase comparator recognizes an almost equally great disturbance with the reverse sign at the moment to + 64 ys, although perhaps the original disturbance has already disappeared again; the consequence is the oscillation illustrated in Fig. 1, which only dies away gradually to a residual error oscillation.

In accordance with this invention, there is provided a circuit for the correction of time errors in the reproduction of video signals, comprising a control oscillator, at least one analogue shift register through which the video signals pass and the delay time of which is variable by the timing frequency of the control oscillator, and a phase comparator for comparing the line synchronizing pulses separated at the output of the shift register with reference pulses and having its output connected to regulate the timing frequency of the control oscillator in the sense of reducing the time error, wherein means are provided whereby the difference between an error signal delivered by the phase comparator and a predetermined average value controls the timing frequency of the control oscillator and whereby this difference is reduced already within a line period.The time-errors are therefore corrected by means of an analogue shift register controlled backwards, that is to say by means of a closed control loop, the closed control loop may have a high control steepness with the control oscillations nevertheless being reduced to a minimum.

In accordance with this invention, it is realised that once a time error has been detected, it must admittedly be controlled quickly but only after the dead time of 64 ys inherent in the television signal can it be measured again at to what extent the time error has in fact been compensated. The error signal delivered by the phase comparator must therefore be converted in its course in time so that it follows the presumed but not yet measured control behaviour during the dead time.

Since, after proper correction of a disturbing quantity, the signal appearing at the control input of the timing oscillator must be identically like the signal present before the appearance of the disturbing quantity, the error signal delivered by the phase comparator must be reduced already during the dead time and tend towards a specific end value. In an embodiment of the invention to be described herein, the average value which is formed from a plurality of preceding measurements is used as the end value. In particular, the approach to this average value may be effected in accordance with an exponential function, because then the approach must be effected the more quickly, the more a detected time error deviates from the average value.There then results a course in time of the control voltage as shown in Fig. 2 with the decisive advantage that a time-error correction may be achieved with very little expenditure, the residual time error in which is only insignificantly greater than with expensive and particularly digital solutions.

An embodiment of this invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 shows the variation with time of the control voltage for the timing frequency oscillator of a prior art time-error correction circuit; Figure 2 shows the variation of the control voltage in a circuit in accordance with this invention; Figure 3 is a block diagram of a time-error correction circuit in accordance with this invention; and Figure 4 is a circuit diagram of part of Fig.

4.

Fig. 3 shows the general circuit diagram: a colour signal supplied at a terminal 1 and the corresponding luminance signal supplied at a terminal 2 are supplied to output terminals 5 and 6 via analogue shift registers 3 and 4. At the output of the register 4, the line synchronizing pulses are separated in a synchronizing separator 7, compared with reference pulses supplied at 9 in a phase comparator 8 and are supplied via a timing network 10 to the control input of a timing oscillator 11.

In Fig. 4, the details of phase comparator 8 and timing network 10 are shown. Transistor 1 2 and capacitor 1 3 represent the usual scanning and holding circuit, the output of which is amplified in an amplifier 14 and averaged, by means comprising resistors 1 5 and 1 6 and a capacitor 18, over 4-6 scannings or television lines. The falling edge of the line synchronizing pulses triggers a monostable multivibrator 1 9 at the same time, the output of which actuates a further scanning and holding circuit, comprising a transistor 20 and a capacitor 21 at the output of the amplifier 14.Thus the voltage corresponding to the time error measured for each television line appears on the capacitor 21, which voltage approaches exponentially with time through a variable resistor 22, the average value at the output of an amplifier 23, and, after amplification by an amplifier 24, is returned to the voltage-controiled timing oscillator 11. The speed at which a detected time error approaches the average value can be adjusted with the resistor 22. If the resistance is too great, a lengthy transient oscillation occurs after a disturbance; if the resistance is too low, the disturbance is not corrected and the residual time error is too great. Since it is desirable for the approach to the average value to be effected the more quickly the greater the deviation of a detected time error from this average value, it is a particular advantage to make this resistor 22 dependent on voltage.

Claims (5)

1. A circuit for the correction of time errors in the reproduction of video signals, comprising a control oscillator, at least one analogue shift register through which the video signals pass and the delay time of which is variable by the timing frequency of the control oscillator, and a phase comparator for comparing the line synchronizing pulses separated at the output of the shift register with reference pulses and having its output connected to regulate the timing frequency of the control oscillator in the sense of reducing the time error, wherein means are provided whereby the difference between an error signal delivered by the phase comparator and a predetermined average value controls the timing frequency of the control oscillator and whereby this difference is reduced already within a line period.

2. A circuit as claimed in claim 1, in which the comparator comprises a scanning and holding circuit, the holding voltages appearing at the output of the scanning and holding circuit being averaged over a plurality of measurements in an RC network.

3. A circuit as claimed in claim 2, in which the holding voltages from the scanning and holding circuit are fed into a further scanning and holding circuit holding capacitor of which is connected through a resistor to a point in the RC network at which the averaged voltage appears.

4. A circuit as claimed in claim 3, in which the resistor is dependent on voltage.

5. A time-error correction circuit substantially as herein described with reference to Figs.

2-4 of the accompanying drawings.