GB201603411D0 - Memory unit - Google Patents

Memory unit

Info

Publication number
GB201603411D0
GB201603411D0 GBGB1603411.8A GB201603411A GB201603411D0 GB 201603411 D0 GB201603411 D0 GB 201603411D0 GB 201603411 A GB201603411 A GB 201603411A GB 201603411 D0 GB201603411 D0 GB 201603411D0
Authority
GB
United Kingdom
Prior art keywords
memory unit
memory
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB1603411.8A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Surecore Ltd
Original Assignee
Surecore Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Surecore Ltd filed Critical Surecore Ltd
Priority to GBGB1603411.8A priority Critical patent/GB201603411D0/en
Publication of GB201603411D0 publication Critical patent/GB201603411D0/en
Priority to PCT/GB2017/050475 priority patent/WO2017144887A1/en
Priority to TW106106423A priority patent/TW201737255A/en
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
GBGB1603411.8A 2016-02-26 2016-02-26 Memory unit Ceased GB201603411D0 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GBGB1603411.8A GB201603411D0 (en) 2016-02-26 2016-02-26 Memory unit
PCT/GB2017/050475 WO2017144887A1 (en) 2016-02-26 2017-02-23 Sram memory unit
TW106106423A TW201737255A (en) 2016-02-26 2017-02-24 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB1603411.8A GB201603411D0 (en) 2016-02-26 2016-02-26 Memory unit

Publications (1)

Publication Number Publication Date
GB201603411D0 true GB201603411D0 (en) 2016-04-13

Family

ID=55807010

Family Applications (1)

Application Number Title Priority Date Filing Date
GBGB1603411.8A Ceased GB201603411D0 (en) 2016-02-26 2016-02-26 Memory unit

Country Status (3)

Country Link
GB (1) GB201603411D0 (en)
TW (1) TW201737255A (en)
WO (1) WO2017144887A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5100035B2 (en) * 2005-08-02 2012-12-19 ルネサスエレクトロニクス株式会社 Semiconductor memory device
US8339838B2 (en) * 2011-01-31 2012-12-25 Freescale Semiconductor, Inc. In-line register file bitcell
US9542992B2 (en) * 2013-04-18 2017-01-10 Nvidia Corporation SRAM core cell design with write assist
US8971096B2 (en) * 2013-07-29 2015-03-03 Qualcomm Incorporated Wide range multiport bitcell
US9263122B2 (en) * 2013-10-21 2016-02-16 Taiwan Semiconductor Manufacturing Company Ltd. Data-controlled auxiliary branches for SRAM cell

Also Published As

Publication number Publication date
WO2017144887A1 (en) 2017-08-31
TW201737255A (en) 2017-10-16

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)