GB1602201A - Pcm telecommunications system - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO A P.C.M. TELECOMMUNICATIONS SYSTEM (71) We, THE GENERAL ELECTRIC COM PANY LIMITED, of 1 Stanhope Gate, London W1A lEH., a British Company, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement:- This invention relates to a P.C.M. telecommunications system using a two-wire line for duplex transmission. A suitable application for such a system is a telephone subscribers connection to an exchange or concentrator.

One method, known as burst-mode transmission, of achieving a duplex P.C.M.

system with a two-wire line is to generate and transmit a block of information in one direction and then to generate and transmit a similar block in the reverse direction. this cycle being repeated. The time available for the emission of the burst (the block of digital information) and ;ts transmission along the line is clearly half of the periodic time of the bursts if an equal time is to be allowed for the return burst.

The greater the bit rate of the block the shorter its duration and the more time is available for line transmission, i.e. the greater is the possible line length. The greater is the number of bits in a burst the greater is the amount of storage needed but again the available line transmission time will be increased. Clearly, however, a burst length of substantial duration, containing a large number of speech samplers, would simulate a correspondingly large loop delay and would be unacceptable to the connected parties.

A suitable burst length has been found to be one P.C.M. word of, say, eight bits, with perhaps one or two further bits for signalling and synchronisation. This means that for speech transmission, and sampling at the standard rate of 8 kllz the period available for the emission and transmission of the burst is half of the frame period, i.e. 62.5 uS.

A 14 difficulty in the operation of a 2-wire duplex P.C.M. system such as described above is that it is desirable to mark the presence and/or absence of a burst since, unlike a junction P.C.M. link the line is not fully occupied.

One object of the present invention is to overcome this difficulty.

According to the present invention in a P.C.M. telecommunications system comprising a two-wire line between first and second stations, blocks of intelligence information are transmitted in opposite directions on said line alternately, and the line code employed is a ternary code, one state of which is representative of zero intelligence inform an tion.

Each of the blocks of intelligence information preferably comprises one P.C.M.

word.

In a local telephone system in accord- ance with the invention, the first station is an exchange or a subscribers concentrator and the second station is a subscribers terminal.

Each block of information is preferably preceded by a predetermined non-zero digit-state.

The equipment at the first station preferably includes a pulse generator for producing a first pulse train having a repetition rate. equal to a multiple of the line bitrate, dividing means for Producing a second pulse train at the line bit-rate by selecting, in effect, periodic pulses from the first pulse train, gate means controlling the supply of the first pulse train to the dividing means, said gate means being arranged to be opened on reception of said block of intelligence information so that the phase of said second pulse train is determined by the first pulse of said first pulse train that is passed to said dividing means, and the arrangement being such that said second pulse train is suitably Dhased for processing the received block of intelligence information irrespective of the time- of its reception.

One embodiment of a local telephone svstem employing pulse-code modulation (P.C.M.) on a two-wire line will now be described, by way of example. with refer ence to the accompanying drawings, of which: Figures 1 and 2 are block diagrams of the terminal circuitry at the exchange and subscribers station respectively; Figure 3 is a diagram of a driver circuit feeding the line; and Figure t is a diagram of unmodulated and modulated Wal-2 waveforms.

Referring to Figure 1, clock signals of 8 kHz and 1024 kHz are derived from the exchange timing circuitry, not shown.

A gate circuit 6 passes the 1024 kHz pulse train under the control of the 8 kHz signal.

Ihe pulse thus passed by the burst gate 6 are divided by four by a counter circuit 7 which in effect distributes the input pulses over four outputs cyclically, each output producing a train of 1:1 marklspace pulses.

The pulses from one of these outputs, designated e),, are counted by a burst counter 8 which closes the gate 6 after ten pulses have been counted. The division by four provides a pulse rate of 256 kHz which is to provide the line bit-rate during bursts.

The four outputs of divider 7 therefore provide pulse trains all at the line bit-rate but staggered in phase by a quarter bitperiod. The second output, 02, gives the so called Wal-2 or top-hat carrier signal shown in Figure 4(a).

It may be seen that if a 10-bit word is produced at the standard 8 kHz sampling rate, the average bit-rate over a number of cycles would be 80 kHz. A line bit-rate of 256 kHz therefore provides a word compression of 3.2 to 1 and thus the necessary time to accept a return word without conflict.

The 8-bit P.C.M. word to be transmitted is applied to a shift register 11 together with a permanent '1' bit and signal bit, the latter two being first and second respectively in order of transmission. The register 11 is loaded at the end of the ten-bit count of the burst counter 8 and is thus loaded with a new word immediately the preceding one is clocked out by the l output of divider 7.

A Wal-2 modulator 12, which is in fact simply an exclusive-or gate, is supplied with the 10-bit output of register 11 and the Wal-2 carrier from divider 7. The resulting modulated signal, such as shown in Figure 4(b), is applied to a driver circuit 13 which, together with a transformer 14 is shown in more detail in Figure 3.

In this driver circuit the data modulated signal is applied to two totem-pole buffer circuits 15 and 16 one giving a normal output and the other an inverted output.

The two buffer circuits each have three output levels corresponding to positive, negative, and zero levels of the data signal.

They effectively work in push-pull, putting opposite or zero levels on the ends of the transformer primary winding 17. Each digit of the Wal-2 coded signal produces both polarities, balanced about zero. A typical signal imposed on the line 18 is shown in Figure 4(c).

The transformer 14 by which the driver circuit is coupled to the line 18 permits the D.C. level of the line to be determined independently of the receiver circuitry which is coupled by a further winding 19. The line winding 20 is split and a D.C. source is connected in series.

Since the average signal level over any digit period on the line has been balanced at zero, the D.C. power feed can be distinguished readily.

The burst gate 6 (Figure 1) is open for the duration of a 10-bit word and thus provides a control signal for the driver circuit enabling it for the word transmission.

When disabled its output level is zero thus being clearly distinguishable from both data levels during a burst.

The exchange receiver is connected to the transformer winding 19 and has to distinguish between zero data, i.e. an idle line, and the two data states. A comparator 23 comprises an operational amplifier which is biased to one output level which is reversed when the data level overcomes the bias. Although by this method only one polarity of the data is effective, the shifting of the critical level of zero makes the receiver relatively insensitive to noise. The intelligence information is of course contained equally in both polarities of the data signal with balanced Walsh coding.

Thus, at an appropriate phase of its output, i.e. at a particular fixed point within the bit period, the comparator gives a '1' or a '0' for each bit of data. It remains to select the appropriate phase, or fixed point, which cannot be predetermined since the onset of transmission by the subscriber ;s arbitrary.

Since the bit-phase of a received burst is arbitrary it is necessary to provide each burst with a marker having a fixed phase relation with the bits of the burst and from which, therefore, the bit-phase of the burst can be detected. This marker could be the first bit of the data word except that its level would be uncertain according to whether it was a '0' or a '1'. This can be overcome in several ways, for example, by full wave rectifying the received signal and detecting the first bit. In the present embodiment it is preferred to provide a prefix digit, a '1', before each burst and in sync with the bits of the burst Detection of this '1' bit therefore identifies the bit-phase of the rest of the burst. Recognition of this '1' by the comparator 23 causes a second burst gate 24 to open so passing the high frequency exchange clock pulses.Those pulses are at four times the line bit-rate, i.e. 1024 kHz, and thus, on dividing by four in divider 25, four phases of line bitrate pulses are available. The divider 25 is a four stage counter so that state changes are provided four times for each bit period.

The burst gate 24 is opened by the first positive-going edge output from the comparator 23 so that the output from the counter 25 consists of the next state change and every fourth one from it. This 'clock' signal is thus locked to the exchange clock frequency and has a phase which is within a quarter bit period of a predetermined phase relation with the received burst.

The clock signal so derived is applied to a retiming circuit 26 as a reference phase throughout the burst. The retimed signal then proceeds through the exchange.

A subsequent phase of the divider 25 is applied to a counter 27 which counts to ten to provide a closing pulse for the burst gate 24.

The comparator 23 is controlled by a bistable which is triggered to an 'enable' state by the trailing edge of the line driver enable pulse and triggered to a 'disable' state by the end of the ten-bit count from burst counter 27.

The subscribers equipment is shown in Figure 2. It employs a voltage controlled oscillator 31 in a phase-locked-loop which includes a low-pass filter 47. Because of the integrating effect of this filter, the oscillator 31 remains closely in sync, even between bursts, once it has acquired synchronisation after a short initial period.

The line 18 is connected to the terminal equipment by way of a transformer 32 similar to that at the exchange end. One secondary winding feeds a comparator 33 similar to that, 23, in the exchange unit, whose output is clocked into a shift-register 34. From the register 34 the word is clocked into a digitallanalogue decoder 35 and passed to the telephone.

In transmission, the analogue signal is sampled and P.C.M. coded by circuitry 36.

The resulting 8-bit word is clocked into a 10-bit shift register 37 where the prefix bit and signalling bit are added. The 10bit word is then passed to a modulator 38 for conversion to Wal-2 coded form, the modulator being an exclusive-OR gate as in the exchange unit. The modulated signal is fed to the line-driver circuit 39 for output to line.

Timing of the operation is achieved as follows. On reception, the first positive going edge of the comparator output, that is, of the '1' prefix bit, triggers a monostable 42 for a period which exceeds the burst period and may annroach but not exceed the frame period. The single leading edge of the monostable pulse is applied to a phase locked loop where it is compared by a phase comparator 43 with the divided output of the voltage controlled oscillator 31. The division factor is 128 in stages of four and thirty-two so as to provide line bit-rate pulse trains at four different phases as before.

The oscillator is thus synchronised in both frequency and phase with the received word as marked by its prefix '1'.

The 0, output of divider 44 provides the Wal-2 carrier which is applied to the modulator 38, while the QI, output is passed to a burst gate 45 which is opened by the leading edge of the monostable output pulse and closed by a twenty-count output of a counter 46. The first ten clock pulses passed by the burst gate clock the received burst through the shift-register 34 while the second ten clock pulses clock out from the register 37 the coded speech sample for transmission. The comparator 33 is disabled during the 10-bit transmission period, i.e.

the latter half of the twenty-count, by a pulse from the counter 46. This same pulse is used to enable the driver circuit 39 during the transmission burst. The receiver is thus enabled for the whole of the frame period except the transmission burst.

When there is transmission by the subscriber but no reception the oscillator 31 runs at an un-synchronised rate and with arbitrary phase. With both reception and transmission the phase of the clock pulse train is dictated by the received burst and the clock pulses in turn dictate the transmission phase.

It may be seen that becaues the Wal-2 coding provides, in effect, a ternary coded signal when it is employed with burst-mode transmission it greatly simplifies the timing problems, providing a way of distinguishing zero signal from both binary digits and thus detecting the onset of a burst.

Experience has shown that when an arrangement such as described above is subject to interference from adjacent pairs in telephone cable connected to electromechanical telephone equipment, a considerable error rate may result, in some cases amounting to loss of synchronisation ~ of the subscriber's unit. In such a case, the number of errors can be considerably reduced by reducing to a minimum the period during which the receiver is enabled, and in particular by ensuring that the start of the enable pulse occurs as short a time as possible before the expected time of arrival of the signal.This is made possible by the cyclic nature of the bursts together with the phase-locking of the oscillator; once the subscriber's oscillator is locked, the expected time of arrival of the signal is determined, being at intervals of 125 ,uS. For example, by allowing the counter 46 to run continuously, resetting itself after each full frame of 32 pulses, a point can be picked in the cycle at, say, 1 ,uS before the burst is expected. This point can be obtained by gating the thirty-first pulse with a particular phase output of the divider 44. The comparator 33 is then enabled at this point and disabled at a count of ten. The driver circuit 39 is then enabled at the count of ten and disabled at a count of twenty. The monostable 42 output then provides an overriding reset input to the counter 46.Such an arrangement minimizes the time during which noise can get through the comparator and monostable and affect the PLL.

A further improvement is possible in reducing the noise affecting the signal itself. Since it can be shown that the spectral distribution of the signal has very little energy below about 100 kHz (approximately half the line rate) whereas much of the noise energy lies in this range, a high-pass filter cutting off at such a frequency will reduce to a large extent the effect of the noise on the signal itself. Such a filter can in the simplest case, consist of the characteristic impedance of the line and the terminating impedance, forming in parallel a series element; the shunt inductance of the line transformer, much reduced below the value normally considered necessary, form a shunt element, the two producing a simple H.P. filter with 6 dB roll-off.By taking into account also the circuit impedance between each half of the line winding, which represents the d.c. power load, either a more rapid roll-off is possible, or the total impedance terminating the line can be made to have, within limits, such desirable characteristics as to minimize reflections back to the exchange unit, which might otherwise cause incorrect operation there.

WHAT WE CLAIM,IS:-- 1. A P.C.M. telecommunications system comprising a two-wire line between first and second stations, wherein blocks of intelligence information are transmitted in opposite directions on said line alternately, and wherein the line code employed is a ternary code, one state of which is representative of zero intelligence information.

2. A system according to Claim 1, wherein each of said blocks of intelligence information comprises one P.C.M. word.

3. A local telephone system in accordance with Claim 1 or Claim 2 wherein said first station is an exchange or a subscribers concentrator and said second station is a subscribers terminal.

4. A system according to any preceding claim, wherein each block of information is preceded by a predetermined non-zero digit-state.

5. A telephone system in accordance with any preceding claim, wherein equipment at said first station includes a pulse generator for producing a first pulse train having a repetition rate equal to a multiple of the line bit-rate, dividing means for producing a second pulse train at the line bitrate by selecting, in effect, periodic pulses from the first pulse train gate means controlling the supply of the first pulse train to the dividing means, said gate means being arranged to be opened on reception of said block of intelligence information so that the phase of said second pulse train is determined by the first pulse of said first pulse train that is passed to said dividing means, and the arrangement being such that said second pulse train is suitably phased for processing the received block of intelligence information irrespective of the time of its reception.

6. A system according to any preceding claim wherein equipment at said second station includes a phase-locked loop for which the leading portion of each received block of information provides a reference input pulse, means for deriving from said phase-locked loop a clock pulse signal of frequency equal to the line-bit rate and of phase determined by said reference input pulse, and cyclic counting means to which said clock pulse signal is applied to provide enabling and disabling signals to the receiving and transmitting circuitry appropriately so that the receiving circuitry is active for a limited time including the duration of a received block of informption and a short period immediately preceding such duration, said Dhase-locked loop maintaining the generation of said clock pulse signal in the absence of any reception and said counting means bering reset on the occurrence of each said reference input pulse.

7. A duplex P.C.M. two-wire telephone system substantially as hereinbefore described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. example, by allowing the counter 46 to run continuously, resetting itself after each full frame of 32 pulses, a point can be picked in the cycle at, say, 1 ,uS before the burst is expected. This point can be obtained by gating the thirty-first pulse with a particular phase output of the divider 44. The comparator 33 is then enabled at this point and disabled at a count of ten. The driver circuit 39 is then enabled at the count of ten and disabled at a count of twenty. The monostable 42 output then provides an overriding reset input to the counter 46. Such an arrangement minimizes the time during which noise can get through the comparator and monostable and affect the PLL. A further improvement is possible in reducing the noise affecting the signal itself. Since it can be shown that the spectral distribution of the signal has very little energy below about 100 kHz (approximately half the line rate) whereas much of the noise energy lies in this range, a high-pass filter cutting off at such a frequency will reduce to a large extent the effect of the noise on the signal itself. Such a filter can in the simplest case, consist of the characteristic impedance of the line and the terminating impedance, forming in parallel a series element; the shunt inductance of the line transformer, much reduced below the value normally considered necessary, form a shunt element, the two producing a simple H.P. filter with 6 dB roll-off.By taking into account also the circuit impedance between each half of the line winding, which represents the d.c. power load, either a more rapid roll-off is possible, or the total impedance terminating the line can be made to have, within limits, such desirable characteristics as to minimize reflections back to the exchange unit, which might otherwise cause incorrect operation there. WHAT WE CLAIM,IS:--

1. A P.C.M. telecommunications system comprising a two-wire line between first and second stations, wherein blocks of intelligence information are transmitted in opposite directions on said line alternately, and wherein the line code employed is a ternary code, one state of which is representative of zero intelligence information.

2. A system according to Claim 1, wherein each of said blocks of intelligence information comprises one P.C.M. word.

3. A local telephone system in accordance with Claim 1 or Claim 2 wherein said first station is an exchange or a subscribers concentrator and said second station is a subscribers terminal.

4. A system according to any preceding claim, wherein each block of information is preceded by a predetermined non-zero digit-state.

5. A telephone system in accordance with any preceding claim, wherein equipment at said first station includes a pulse generator for producing a first pulse train having a repetition rate equal to a multiple of the line bit-rate, dividing means for producing a second pulse train at the line bitrate by selecting, in effect, periodic pulses from the first pulse train gate means controlling the supply of the first pulse train to the dividing means, said gate means being arranged to be opened on reception of said block of intelligence information so that the phase of said second pulse train is determined by the first pulse of said first pulse train that is passed to said dividing means, and the arrangement being such that said second pulse train is suitably phased for processing the received block of intelligence information irrespective of the time of its reception.

6. A system according to any preceding claim wherein equipment at said second station includes a phase-locked loop for which the leading portion of each received block of information provides a reference input pulse, means for deriving from said phase-locked loop a clock pulse signal of frequency equal to the line-bit rate and of phase determined by said reference input pulse, and cyclic counting means to which said clock pulse signal is applied to provide enabling and disabling signals to the receiving and transmitting circuitry appropriately so that the receiving circuitry is active for a limited time including the duration of a received block of informption and a short period immediately preceding such duration, said Dhase-locked loop maintaining the generation of said clock pulse signal in the absence of any reception and said counting means bering reset on the occurrence of each said reference input pulse.

7. A duplex P.C.M. two-wire telephone system substantially as hereinbefore described with reference to the accompanying drawings.