GB1601863A - Portable electronic device and input circuit therefor - Google Patents

Description

PATENT SPECIFICATION

( 11) ( 21) Application No 12428/78 ( 22) Filed 30 March 1978 ( 19) ( 31) Convention Application No 52/039125 U ( 32) Filed 30 March 1977 52/040818 8 April 1977 in ( 33) Japan (JP) ( 44) Complete Specification published 4 Nov 1981 ( 51) INT CL 3 G 06 F 3/00 G 06 G 1/00 5/00 ( 52) Index at acceptance G 4 H 13 D 14 D KS G 3 T 101 401 407 AAA KC ( 54) A PORTABLE ELECTRONIC DEVICE AND INPUT CIRCUIT THEREFOR ( 71) We, CITIZEN WATCH COMPANY LIMITED, a corporation organized under the laws of Japan, of No 1-1, 2-chome, Nishishinjuku, Shinjuku-ku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the

following statement:-

This invention relates to portable electronic devices and input circuits therefor An example of a portable electronic device is a device which can be utilized both as a calculator and as a timepiece, and which incorporates a keyboard and control switches.

In recent years, portable electronic devices have been introduced which can perform the functions of both a calculator and a timepiece, some of these devices being designed to be worn on the wrist Due to the small size of such devices, it it only possible to utilize a battery of relatively small size and capacity as a power source It is therefore necessary to ensure that the power dissipation of the device shall be as low as possible.

Until now, the input circuit of the keyboard of such a portable electronic device, ised to produce electrical signals to indicate tht a key has been depressed and to identify the particular key, have been of similar design to the keyboard input circuits used in electronic calculators of conventional design.

Such a type of circuit dissipates a relatively high level of power, and is not suitable for a device in which power consumption must be reduced to the lowest practicable degree The above remarks are also applicable to the input circuits of external actuation members such as control switches, utilized to select the display of time information or calculation information, for example Such input circuits must suppress spurious switch bounce pulses generated when switch contacts are closed.

According to a first aspect of the present invention there is provided an input circuit for a circuit for a portable electronic device, the input circuit comprising: a keyboard provided with numeric keys and function keys to provide numeric signals and function 50 signals, respectively; a frequency standard providing a standard frequency signal; a key contact matrix comprising a plurality of key contacts and responsive to actuation of said numeric keys and said functions keys; a 55 plurality of matrix columns of said key contact matrix comprising electrical conductors connected to respective columns of said key contacts; a plurality of matrix rows of said key contact matrix comprising electrical 60 conductors connected to respective rows of said key contacts; a plurality of indedance elements connected between respective members of said plurality of matrix columns and a first potential of a power source; a 65 plurality of electronic switching elements connected between respective members of said matrix rows and a second potential of the power source, each electronic switching element having a control electrode; timing 70 signal generating means responsive to said standard frequency signal for providing a plurality of timing signals; control signal generation circuit means for generating a control signal when said portable electronic 75 device is set in a predetermined operating mode, said control signal having a duty cycle lower than one half; and a control circuit responsive to said control signal and said plurality of timing signals to generate a 80 plurality of scanning signals which are applied to the control electrodes of said plurality of electronic switching elements, respectively, for thereby sequentially causing each of said plurality of electronic switching 85 elements to enter an electrically conductive state for a limited period of time.

According to a second aspect of the present invention there is provided an input circuit for a portable electronic device, the 90 1601863 1.601,863 input circuit comprising: a keyboard provided with numeric keys and function keys to provide numeric signals and function signals, respectively; a frequency standard providing a standard frequency signal; a key contact matrix comprising a plurality of key contacts and responsive to actuation of said numeric keys and said function keys; a plurality of matrix columns of said key contact matrix comprising electrical conductors connected to respective columns of said key contacts; a plurality of matrix rows of said key contact matrix comprising electrical conductors connected to respective rows of said key contacts; a plurality of impedance elements connected between respective members of said plurality of matrix columns and a first potential of a power source; a plurality of electronic switching elements connected between respective members of said matrix rows and a second potential of the power source, each electronic switching element having a control electrode; timing signal generating means responsive to said standard frequency signal for providing a plurality of timing signals; first control signal generation circuit means for generating a first control signal when said portable electronic device is set in a predetermined operating mode; a control circuit responsive to said first control signal and said plurality of timing signals to generate a plurality of scanning signals; second control signal generation circuit means for generating a second control signal in the absence of said plurality or timing signals; and gate circuit means responsive to said scanning signals; and gate circuit means responsive to said scanning signals for thereby sequentially causing each of said plurality of electronic switching elements to enter an electrically conductive state for a limited period of time; said gate circuit means being responsive to said second control signal to cause all of said plurality of electronic switching elements to enter an electrically conductive state continuously in the absence of said timing signals being applied to said control circuit.

The present invention permits a reduction in the power dissipation of the input circuits of the keyboard and the external control members of a portable electronic device In the preferred embodiment, matrix columns of a key contact matrix actuated by the keyboard keys are normally held at a low potential by being connected to the low potential terminal of the battery of the device, through impedance elements Matrix rows of the key contact matrix are connected at one end to switching elements, so that the matrix rows are normally in a floating condition, electrically speaking, but are periodically connected to the high potential terminal of the device battery by the switching elements being periodically set in the conducting condition The switching elements are set in the conducting condition by periodic scanning signals, which can have a very small duty cycle, 1/4000 for example.

Thus, if a key is depressed, current flows 70 from the high potential of the battery through a switch device and through matrix contacts into an impedance device However, due to the low duty cycle of the signal which controls the switching element, the average 75 current flowing while a key is depressed is extremely low Memory circuits are provided into which information on the state of the matrix rows is read in synchronism with the switching elements being set into the con 80 ducting condition Other memory circuits are used to store information on the condition of the matrix columns The above two sets of information are encoded and output as DC signals in the case of the function keys, and 85 as tim serial data in the case of the numeric keys of the keyboard, referred to herein as the ten keys.

In the case of the input circuits of external actuating members such as switches, one side 90 of each pair of switch contacts is connected to the high potential of the battery, while the other side is periodically set to the low potential of the battery by a reset signal of low duty cycle, applied through a logic gate 95 The condition of the contact connected to the logic gate output is periodically registered in a flip-flop, so that the output of the flip-flop is normally at the low potential, but goes to the high potential if the corresponding switch 100 contacts are closed As in the case of the keyboard input circuit described above, the low duty cycle of the reset signal used serves to ensure very low average current being drawn from the device battery Also, the 105 relatively long period between each of the pulses of the reset signal ensures that switch bounce pulses have no effect The output of memory circuits, previously mentioned, are periodically registered in another set of 110 memory circuits, to provide steady-state control signals which are synchronized with the internal circuit operation of the device.

Embodiments of the present invention will now be described by way of example only 115 and with reference to the accompanying drawings, in which:

Fig 1 is an external view of a portable electronic device; Fig 2 shows a keyboard input circuit, 120 Fig 3 is a waveform diagram showing the waveforms of signals used in the circuit of Fig 2; Fig 4 is a block diagram showing a frequency standard, frequency dividers, flip 125 flops, gates and a timing generator used to produce timing signals used in the circuit of Fig 2.

Fig 5 is a waveform diagram showing the waveforms of signals generated by the circuit 130 1,601,863 shown in Fig 4; Fig 6 is a waveform diagram further illustrating the waveforms of signals generated by the circuit of Fig 4; Fig 7 is a simplified circuit diagram of an input circuit for external control members.

Referring to the drawings, Fig 1 is an external view showing a portable electronic device equipped with input circuits The device shown in Fig 1 can be attached to the wrist by means of a wristband, 12 Numeral 6 indicates a mode switch, adapted for switching between the calculation and the timepiece modes of operation of the device, and between the "hours, minutes, seconds" mode and the "year, month, date" mode while in the timepiece mode of operation Numeral 4 denotes a display device adapted to display the mode selected by means of switch 6.

Switch 8 is provided to perform a time setting lock function When this switch is pulled outward from the device body it becomes possible to set the time information displayed on 4 Time setting is performed by inputting correction information from a keyboard, 14, which is normally utilized to input calculation mode of operation, and is used to reset the seconds of the time information to zero during time correction in the timepiece mode of operation.

Fig 2 shows a keyboard contact matrix and inputs circuits for that keyboard matrix Rows of interconnected key contacts, referred to hereinafter as matrix rows, 23, 25, 27 and 29, are connected to switching elements 14, 16, 18 and 20 respectively When these switching elements are set in to a conducting condition (referred to hereinafter as the on state) by output signals from NOR gates 22, 24, 26 and 28 respectively, (referred to herein as scanning signals) the corresponding matrix rows are connected to the high potential of the battery of the device, hereinafter referred to as the H level Columns of interconnected key contacts, referred to hereinafter as matrix columns, are connected to the low potential of the battery of the device (referred to hereinafter as the L level) through resistance elements Matrix olumns 15, 17, 19 and 21 are connected to resistance elements 78, 80, 82 and 84 respectively For the illustrative embodiment described herein, the resitive elements 78, 80, 82 and 84 consist of MOS devices The matrix columns are also connected to the data input of data type flip-flop (referred to hereinafter as DFF) 96, and to the data inputs of DF Fs 98, 100 and 102 through a combination of AND gates 90, 103 and 106, OR gates 88 and 94, and inverters 86, 92 and 104 This combination serves to establish priorities for the matrix columns, so that if more than one key is depressed simultaneously, only the key in the lowest order column is effective DF Fs 96, 98, 100 and 102 serve to register matrix column state information, and constitute second memory circu its DF Fs 64, 66, 68 and 70 serve as first memory circuits, and correspond to matrix rows 23, 25, 27 and 29 respectively 70 Timing signals tl, t 2, t 4 and t 8 are applied to inputs of AND gates 40, 42, 44 and 46 respectively, and have the timing relationships shown in Fig 3.

The method of generating timing signals 75 tl, t 2, t 4 and t 8, which are utilized to control the sequence of operations when the portable electronic device is in the calculation mode of operation, will now be described referring to Fig 4 In Fig 4, an oscillator 120 serving 80 as a frequency standard generates an output signal of 32 k Hz frequency which is applied to frequency divider 121 Output signal O from frequency divider 121, which has a frequency of 16 k Hz, is applied to frequency 85 divider 122 and to an input of AND gate 127.

Since the division ratio of frequency divider 122 is 1/512, an output signal of 32 Hz frequency is produced, which is applied to the data terminal of DFF 128, and to the 90 input of frequency divider 124 Since the division ratio of divider 124 is 1/32, an output signal of frequency 1 Hz is produced.

This signal is utilized as the time unit signal for timekeeping by the device When resett 95 ing of the seconds of the time information to zero is performed in the time correction mode, the various stages in divider 124 are reset to the zero count state by application of a SECONDS ZERO RESET signal to the R 100 terminal.

The output signals from timing generator 126 are mainly used in the calculation mode of operation, to control the sequence of calculation operations The relationships be 105 tween these signals, tl, t 2, t 4 and t 8, and Dl to D 9, are shown in the waveform diagrams of Fig 6 and Fig 3 Signal o is applied to timing pulse generator 126 through AND gate 127 A TIMING OUTPUT signal ap 110 plied to the other input of AND gate 127 controls the transfer of O pulses to timing generator 126, transfer of 0 pulses being inhibited when TIMING OUTPUT is at the L level, and enabled when it is at the H level 115 When the TIMING OUTPUT signal is at the low level, the operation of timing generator 126 is stopped.

The 32 Hz output signal from frequency divider 122 is read into DFF 128 by signal 120 D 1, as shown in the waveform diagram of Fig 5, so that output QI of DFF 128 goes to the H level Output QI is read into DFF 130 by the next leading edge of a tl pulse to occur after the D 1 pulse which caused Q 1 to go to 125 the H level Output I Qof DFF 130 thereby goes to the L level, as shown in Fig 5 Signals Q 1 and Q 2 are applied to AND gate 132, which outputs signal 32 Hz' This signal has a waveform which rises to the H level with the 130 1,601,863 D l signal, but does not go to the L level until after the training edge of the Dl pulse has already gone to the L level.

While the 32 Hz' signal is at the H level, one pulse of each of signals ti, t 2, t 4 and t 8 occurs, consecutively The duty cycle of the 32 Hz' signal depends upon the frequency of the signal applied to the data terminal of DFF 128 For example, if the frequency of the signal applied to this data terminal were 1 Hz, then the duty cycle of the output signals from AND gate 132 would be 1/4000 approximately.

Referring again to Fig 2, output of pulses ti, t 2, t 4 and t 8 to produce scanning pulses from AND gates 40, 42, 44 and 46 is controlled by the output from AND gate 36.

The CALCULATION signal applied to an input of OR gate 34 goes to the H level when the device is in the calculation mode of operation The SET signal applied to the other input of gate 34 goes to the H level when the time setting mode is selected.

Signal c, applied through inverter 38 to an input of AND gate 36, goes to the H level only when clearing is performed during the calcualtion mode or when the seconds are reset to zero in the time setting mode.

From the above, it is clear that in either the calculation or the time setting modes, the output of AND gate 36 goes to the H level each time the 32 Hz' signal goes to the H level, but is held at the L level while clearing or seconds resetting to zero is performed.

Thus, other than in the latter cases, each time a 32 Hz' pulse occurs, one each of the t 1, t 2, t 4 and t 8 pulses is output from AND gates 40, 42, 44 and 46 respectively, in the sequence shown in Fig 3 Pulses tl to t 8 are applied to the control terminals of impedance elements 14, 16, 18 and 20 respectively, through NOR gates 22, 24, 26 and 28, thereby sequentially setting these control elements into the conductive condition.

Thus, when the 32 Hz' signal goes to the H level, matrix row 23 goes to the H level during a tl pulse, due to the action of switching element 14.

When signal 32 Hz' goes to the L level, all of switching elements 14, 16, 18 and 20 go to the off state, and the matrix rows remain in a floating condition until the 32 Hz' signal again goes to the H level.

If a key is depressed, for example the 7 key, then matrix row 23 and matrix column will be conected together In this condition, when the 32 Hz' signal and the tl signal both go to the H level, switching element 14 is set to the on state Current therefore flows from the H potential to the L potential terminals of the battery via switching element 14, matrix rows 23, matrix column 15, and impedance element 208 for the duration of the tl pulse If the repetition frequency of the tl signals is 4 k Hz, then, the probability of a tl pulse occurring during a 32 Hz' pulse is approximately 1/500 On the average, therefore, current will only flow through the matrix row and column for 1/500th of the time that the key is depressed Thus, the 70 power dissipated in order to detect depression of a key is significantly reduced as compared with conventional circuits for keyboard input.

Matrix column 15 is connected to the data 75 terminal of DFF 96, while columns 17, 19 and 21 are connected to inputs of AND gates 90, 103 and 106, whose outputs are applied to the data terminals of DF Fs 96, 98, 100 and 102 are connected to the inputs of OR gate 80 108, whose output is connected to the data terminals of DFF 64, 66, 68 and 70.

The clock terminals of DF Fs 64, 66, 68 and 70, which correspond to rows 23, 25, 27 and 29, are connected to the outputs of gates 85 56, 58, 60 and 62 The Q output of each of DF Fs 64, 66, 68 and 70 is connected to the inputs of the three AND gates of 56, 58, 60 and 62 which are connected to the other three DF Fs Thus, once one of these DF Fs 90 has been set to the on state, so that its Q output is at the L level, clock signals to the other three DF Fs are inhibited The AND product of the 32 Hz' signal, (output from AND gate 36 as described above), with 95 signals tl, t 2, t 4 and t 8 respectively, is output from AND gate 40,42,44 and 46 and applied to AND gates 48, 50, 52 and 54 together with signal O Thus, pulses with the same timing relationships as those applied to the control 100 terminals of switching elements 14, 16, 18 and 20, but with pulse width equal to the O pulses, are applied as clock signals to DF Fs 64, 66, 68 and 70 through AND gates 56, 58, and 62 105 Accordingly, when a key is depressed in matrix row 23, for example, the next output pulse for NOR gate 22 causes row 23 to go to the H level by the action of switching element 14 As a result, the matrix column 110 corresponding to the key which is depressed will go to the H level at this time A short time later, the H level output produced by OR gate 108 as a result of the column going to the H level will be read into DFF 64 by the 115 clock pulse output from AND gate 56.

The Q outputs from DF Fs 64, 66, 68 and are applied to the inputs of OR gate 76.

Thus, when a key is depressed, the output of OR gate 74, and hence of OR gate 76, will 120 rise to the H level Since the output of OR gate 76 is connected to the clock terminals of DF Fs 96, 98, 100 and 102, these DF Fs register the H level of the column containing the key which has been depressed, on the 125 rising edge of the output from OR gate 76.

The Q output of DFF 71 is normally at the L level, due to the L level applied to its data terminal being read in by successive 32 Hz' pulses When a key is depressed, causing the 130 1,601,863 output of OR gate 74 to go to the H level, the application of this Or gate 74 output to the S terminal of DFF 71 causes its Q output to be forcibly set to the H level The trailing edge of the 32 Hz' pulse during which key depression was detected, inverted in inverter 73, is applied to the clock terminal of DFF 75, causing its Q output to go to the H level.

This output, signal Key ON, is applied to an input of OR gate 76 thereby ensuring that this gate produces only one pulse (applied to the clock terminals of DF Fs 96, 98, 100 and 102) each time a key is depressed.

The outputs from matrix columns DF Fs 96, 98, 100 and 102, and from matrix row DF Fs 64, 66, 68 and 70, are combined in a set of AND gates shown in block 112 in Fig 2.

When a key is depressed, the corresponding AND gate output in block 112 goes to the H level, with the exception of the 0 key, for which no AND gate is required In addition, when one of the ten keys is depressed, a TEN signal is produced from OR gate 116 The outputs of AND gates in block 112 which correspond to the ten keys are encoded by OR gates 81, 83, 85 and 87 The outputs of these gates represent the value of a key which is depressed, expressed in parallel binary form, and are sequentially scanned by signals, tl, t 2, t 4 and t 8 applied to AND gates 91, 93, 95 and 97 As a result, the numeric value of a key which is depressed is output from OR gate 114, in serial binary form, as data signal Z.

There is a time interval of about 30 ms between each of the 32 Hz' pulses, during which time the effects of switch bounce will disappear Thus, it is unnecessary to provide additional circuitry for switch bounce suppression, with the keyboard input circuit described.

When a key is released, the corresponding matrix row DFF will have an L level signal aplied to its data terminal, and its Q output is therefore reset to the L level The output of OR gate 74 goes to the low level, releasing the set condition of FF 71 so that outputs of F Fs 71, 75, 77 sequentially goes to a low level In the case of the matrix column DFF k 96 98, 100 or 102), the trailing edge of the Key ON signal, applied to an input of AND gate 72 through inverter 77 causes an H level output from AND gate 72, which resets all of the matrix column DFF Q outputs to L level when a key is released.

When power is switched on, an INITIAL RESET signal is applied to the reset terminals of the matrix row DF Fs, thereby resetting their Q outputs to the L level.

Timing pulse generator 126 is actuated by the TIMING OUTPUT signal only when the timing pulses are actually required, in the calculation mode or the time setting mode.

When TIMING OUTPUT is a the L level, so that the timing signals and the 32 Hz' signal are not being produced, the SET or CALCULATION signal applied to AND gate 32 through OR gate 34, and the TIMING OUTPUT signal applied through inverter 30, together cause the output of AND gate 32 to 70 go to the H level Since this output is applied to NOR gates 22, 24, 26 and 28, L level signals are applied to the control terminals of switching elements 14, 16, 18 and 20 Therefore, switching elements 14, 16, 18 and 20 are 75 turned ON and rows 23, 25, 27 and 29 goes to the high level If a key is depressed, in this condition, then the output of OR gates 108 goes to the H level This output is used to cause the TIMING OUTPUT signal to go to 80 the H level, so that the timing pulse generator 126 begins to generate the timing signals and the 32 Hz' signals Thereafter, the operation is as previously described.

Fig 7 shows a preferred embodiment of an 85 input circuits for external control members.

Numerals 6, 8 and 10 represent the switch contacts of the mode selection, time setting lock and clear control members respectively whose functions have been described above 90 When member 6, 8 or 10 is actuated, an H level signal is applied to the data terminal of the corresponding DFF 138, 140 or 142 The output of AND gate 156 consists of reset pulses with a frequency of 32 Hz and pulse 95 width equal to the period of the 0 pulses The leading edge of each of the output pulses from AND gate 156 occurs just after the leading edge of a corresponding 32 Hz pulse.

These output pulses are inverted and applied 100 to the clock terminals of DFF 138, 140, 142 through NAND gate 144 These DF Fs serve as a first stage memory circuit.

Timing pulses Dl are applied to the clock terminals of DF Fs 148, 150 and 152, which 105 serve as a second stage memory circuit.

The output pulses from AND gate 156 are also applied through NOR gates 148, 149 and 151 to the data terminals of the first stage memory circuit DF Fs, to set these to the L 110 level so long as the corresponding external actuating member is not actuated Inverters 137, 139 and 141 serve to latch the said data terminals at the L level between output pulses from AND gate 156 115 If, for example, the contacts of member 6 are closed, the potential of line 136 is forcible raised to the H level, irrespective of the pulses applied to NOR gate 148 The clock pulses to DFF 138 therefore cause its Q 120 output to go to the H level Since there is a period of the order of 30 ms between each of these clock pulses, the effects of any switch bounce resulting from the contacts being closed will have disappeared by the time the 125 next clock pulse is aplied to DFF 138 Thus, suppression of switch bounce is simply and effectively achieved.

If the device is in the course of a calculation operation, the signal BUSY is at the H 130 1,601,863 level Output of clock pulses from NAND gate 144 is therefore inhibited, and actuation of external control members 6, 8 or 10 will have no effect, The H level of the output of DFF 138 resulting for actuation of 6, is registered in DFF 148 on the leading edge of the next Dl pulse to occur after detection of actuation by DFF 138 Thus, actuation of 6 results in an H level output from DFF 148 which is synchronized with the timing signals, and which is free from the effects of switch bounce.

With the circuit arrangement shown, it is apparent that output CG or OR gate 154 will go to the H level following actuation of 6, 8 or 10, and will remain at that level until the output from DFF 138, 140 or 142 has been registered in the corresponding DFF 148, 150 and 152 Signal CG serves as a command signal which causes timing pulse generator 126 to begin generating timing pulses This is necessary since the timing pulse generator is only activated when these timing pulses are actually required, in order to minimize power consumption When the timing pulse generator is activated by signal CG, a Dl pulse is subsequently produced, causing the Q output of DFF 148, 150 or 152 corresponding to the actuated control member to go to the H level on the leading edge of that Dl pulse Signal CG thereby returns to the L level.

From the above description, it may be understood that the input circuits for keyboard and for external members as illustrated by the preferred embodiment, enable a significant reduction of battery power consumption in a portable electronic device with combined calculator and timepiece functions to be achieved This is in part due to the fact that the condition of the keyboard contact matrix is periodically examined by means of pulses which can have an extremely low duty cycle In the intervals between these pulses, if MOS type circuit elements are utilized, thesteady-state current drawn from the device battery will be very small indeed In addition, since the timing pulse generator which produces the said pulses is only activated as a result of a key being depressed (other than during a calculation or time setting operation), the average power required by the timing pulse generator is also very small The low duty cycle of the same pulses also allows the effects of switch bounce to disappear between the time that key depression is first detected and the occurrance of the next timing pulse Thus, switch bounce is effectively eliminated without the need to provide additional elements specifically for this purpose.

In the case of the input circuit for external control member, the above remarks are also true In this case, the provision of first stage and second stage memory circuits enables switch bounce to be suppressed in the first stage, while synchronization with internal timing signals is achieved by means of the second stage circuits.

Although in the above described embodiments the power source has been referred to as a battery other forms of power source may be used.

Claims (6)

WHAT WE CLAIM IS: 75

1 An input circuit for a portable electronic device, the input circuit comprising:

a keyboard provided with numeric keys and function keys to provide numeric signals and functions signals, respectively; 80 a frequency standard providing a standard frequency signal; a key contact matrix comprising a plurality of key contacts and responsive to actuation of said numeric keys and said function keys; 85 a plurality of matrix columns of said key contact matrix comprising electrical conductors connected to respective columns of said key contacts; a plurality of matrix rows of said key 90 contact matrix comprising electrical conductors connected to respective rows of said key contacts; a plurality of impedance elements connected between respective members of said 95 plurality of matrix columns and a first potential of a power source; a plurality of electronic switching elements connected between respective members of said matrix rows and a second potential of 100 the power source, each electronic switching element having a control electrode; timing signal generating means responsive to said standard frequency signal for providing a plurality of timing signals;

105 control signal generation circuit means for generating a control signal when said portable electronc device is set in a predetermined operating mode, said control signal having a duty cycle lower than one half, and 110 a control circuit responsive to said control signal and said plurality of timing signals to generate a plurality of scanning signals which are applied to the control electrodes of said plurality of electronic switching ele 115 ments, respectively, for thereby sequentially causing each of said plurality of electronic switching elements to enter an electrically conductive state for a limited period of time.

2 An input circuit as claimed in claim 1, 120 further comprising a first memory circuit to receive said scanning signals and responsive to said scanning signals to generate a row output signal indicative of a matrix row in which one of said keys has been actuated, 125 and a second memory circuit coupled to said matrix columns to generate a column output signal indicative of a matrix column containing said key which has been actuated.

3 An input circuit as claimed in claim 1 130 1,601,863 or 2, wherein each of said scanning signals comprises a train of electrical pulses having a repetition period that is longer than the duration of a switch bounce condition of intermittent electrical contact of said key contacts occurring following actuation of said keys.

4 An input circuit as claimed in claim 2, further comprising first inhibiting gate means to said row output signal for inhibiting more than one of said scanning signals from being concurrently applied to said first memory circuit when said numeric keys and said function keys are concurrently actuated, and second inhibiting gate means for inhibiting output signals of said matrix column from being concurrently applied to said second memory circuit when said numeric keys and said function keys are concurrently actuated.

5 An input circuit for a portable electronic device, the input circuit comprising:

a keyboard provided with numeric keys and function keys to provide numeric signals and function signals, respectively; a frequency standard providing a standard frequency signals; a key contact matrix comprising a plurality of key contacts and responsive to actuation of said numeric keys and said function keys; a plurality of matrix columns of said key contact comprising electrical conductors connected to respective columns of said key contacts; a plurality of matrix rows of said key contact matrix comprising electrical conductors connected to respective rows of said key contacts; a plurality of impedance elements connected between respective members of said plurality of matrix columns and a first potential of a power source; a plurality of electronic switching elements connected between respective members of said matrix rows and a second potential of the power source, each electronic switching element having a control electrode; timing signal generating means responsive to said standard frequency signal for providing a plurality of timing signals; first control signal generation circuit means for generating a first control signal when said portable electronic device is set in a predetermined operating mode; a control circuit responsive to said first control signal and said plurality of timing signals to generate a plurality of scanning signals; second control signal generation circuit means for generating a second control signal in the absence of said plurality of timing signals; and gate circuit means responsive to said scanning signals for thereby sequentially causing each of said plurality of electronic switching elements to enter an electrically conductive state for a limited period of time; said gate circuit means being responsive to said second control signal to cause all of said plurality of electronic switching elements to enter an electrically conductive state continuously in the absence of said timing signals being applied to said control circuit.

6 An input circuit for a portable electronic device substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

MARKS & CLERK, Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd -1981 Published at The Patent Office, Southampton Buildings, London, WC 2 A IAY, from which copies may be obtained.