GB1585080A - Circuit for producing synchronisation pulses - Google Patents

Description

(54) CIRCUIT FOR PRODUCING SYNCHRONISATION PULSES (71) We, THE MARCONI COMPANY LIMITED, a British Company, of Marconi House, New Street, Chelmsford, Essex CMl 1PL, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a circuit for producing pulses synchronised with incoming data pulses.

Such a circuit is required, for example, at the receiving end of a telephone line where incoming data lacks the necessary synchronising clock pulses. To enable the received incoming pulses to be converted from serial to parallel form by insertion into a clocked shift register, it is necessary to establish clock synchronisation pulses.

The present invention seeks to provide a circuit for performing the above mentioned function and in accordance with this invention a circuit for producing pulses synchronised with incoming data pulses includes a read-only memory for comparing the phase difference between a first and a second counter and arranged to increment the count of the second counter in steps in response to said data pulses until a predetermined phase difference is established between the counters, the first counter being arranged to perform a counting cycle during the period of a bit cell of the incoming data pulses and the second counter having the count therein set until reviewed by the read-only memory in response to an incoming data pulse and wherein the read-only memory is arranged to produce a synchronising pulse during each bit cell when the count of the first counter is equal to the count of the second counter plus a predetermined count of integers of the first counter.

The term "bit cell" used herein, is intended to mean the period of one bit of serial data whether or not serial data is present.

Preferably, a locally generated series of preclock pulses independent of the incoming pulse data is appled to the first counter and a synchroniser has the output thereof connected to a respective first input of a pair of AND gates, the second input of each of the gates being connected to output terminals of the read-only memory such that the second input of one of the gates is energised when the first counter has a count greater than that of the second counter and the second input of the other of the gates is energised when the first counter has a count less than the second counter, and wherein said synchroniser is arranged to receive the incoming data pulses and energise the first input of the gates in synchronism with pulses from the read-only memory on the required second input of the gates.

In a preferred embodiment, the first counter produces a staircase waveform having sixteen pulse steps prior to re-cycling and in such an embodiment, the synchronising pulses may be produced when the count of the first counter is equal to the count of the second counter plus eight pulse steps of the first counter.

The invention will now be described, by way of example, with reference to the drawings accompanying the Provisional specification in which; Figure 1 is a block schematic diagram of a circuit in accordance with this invention; and Figures 2a, b, c, d and e are graphical timing waveforms produced at various parts of the circuit shown in Figure 1.

The circuit shown in Figure 1 has an input terminal 1 to which is applied locally generated pre-clock pulses at a frequency sixteen times that of the incoming serial data applied at a terminal 2. The pre-clock pulses shown in Figure 2a are applied to a counter 3 which may be formed from Texas Instruments Type No.

74161 to produce a re-cycling staircase waveform of sixteen incremental steps in synchronism with the pre-clock pulses (Figure 2b). The counter 3 is connected via a four bit address highway to a read-only memory 4, which may comprise a Monolithic Memories Inc. integrated circuit Type No. 6301-1. A further counter 5 formed from Texas Instruments Type No.

74193 is also connected by a four bit address highway to the read-only memory 4, the arrangement of the counters 3 and 5 and the read-only memory 4 being such that the readonly memory 4 is pre-programmed to act as a comparator to the counts registered by the counters 3, 5.

The read-only memory 4 has two dutput terminals 6, 7, the terminal 6 receiving a signal when the count of counter 3 is greater than that of counter 5 and the terminal 7 receiving a signal when the count of counter 3 is smaller than that of counter 5. The terminals 6 and 7 are each connected to a respective input of AND gates 8, 9, both of the AND gates being comprised by Texas Instruments Type No.

7400. The pre-clock pulses are also applied to a synchroniser 10 which is arranged to receive incoming data pulses from the terminal 2. The synchroniser 10 utilises the pre-clock pulses to produce pulses at each transition of the incoming data pulses in synchronism with pulses at either one of the terminals 6, 7 of the readonly memory 4 to energise a further input of each of the AND gates 8; 9. Output from the AND gate 8 is applied as a count-up input of the counter 5 and output from the AND gate 9 is applied as a count-down input to the counter 5. The read-only memory 4 has a further output terminal 11 at which is provided the required pulses synchronised with the incoming data pulses. The read-only memory 4 is preprogrammed such that the synchronised pulses at terminal 11 occur when the count of counter 3 is eight more pulse steps than the count of counter 5.

In operation, at the start of the first incoming data bit which causes a first pulse output of the synchroniser 10 (shown in Figure 2d), suppose that the count of counter 3 is five (Figure 2b) and that the count of counter 5 (shown in Figure 2c) is seven. Because the count of counter 3 is less than that of counter 5 the read-only memory produces an output at terminal 7 so that the AND gate 9 is enabled since a pulse is also present from the synchronier 10. The counter 5 is thus, staticised at a lower count of six. Because the read-only memory 4 is programmed to produce an output at terminal 11 when the count of counter 3 is equal to the count of counter 5 plus eight, a clock synchronising pulse (shown in Figure 2e) isprovided at terminal 11 in synchronism with the fourteenth step of the staircase waveform of counter 3 (Figure 2b).At the next tran sition of the incoming data bits, the synchroniser 10 again applies a pulse to energise one of the terminals of both the AND gates 8, 9 and the counter 3 again has a count of five. The previously staticised count of counter 5 is still greater than that of the counter 3 and so an output is again derived at terminal 7 of the read-only memory 4 to enable AND gate 9 to step down the count of the counter 5 to five.

The synchronisation pulse provided at terminal 11 is produced when the count of counter 3 is thirteen, i.e. the count of counter 5 which is five, plus'eight. At the next transition, i.e. the third pulse shown in Figure 2d, the counts in the two counters 3 and 5 are equal and so no re-alignment of the counter 5 is necessary.

It will now be realised that if the phase of the incoming data bits vary more than one sixteenth of a cycle, with respect to the count in counter 3, then the count in counter 5 is incremented or decremented by one and the position of the synchronising pulse readjusted by one sixteenth of a cycle of the counter 3.

This feature has the additonal advantage that if a noise spike should occur between the transition pulses of Figure 2d at the output of the synchroniser 10, then the count of counter 5 will be varied, either up or down, in dependence upon the counts of the counters 3 and 5 so that the phase of the synchronising pulse at the terminal 11 (Figure 2e) will be adjusted by only one sixteenth of a cycle of the count of counter 3.

WHAT WE CLAIM IS: 1. A circuit for producing pulses synchronised with incoming data pulses including a readonly memory for comparing the phase difference between a first and a second counter and arranged to increment the count of the second counter in steps in response to said data pulses until a predetermined phase difference is established between the counters, the first counter being arranged to perform a counting cycle during the period of a bit cell of the incoming data pulses and the second counter having the count therein set until reviewed by the read-only memory in response to an incoming data pulse and wherein the read-only memory is arranged to produce a synchronising pulse during each bit cell when the count of the first counter is equal to the count of the second counter plus a predetermined count of integers of the first counter.

2. A circuit as claimed in claim 1 and wherein a locally generated series of pre-clock pulses independent of the incoming pulse data is applied to the first counter and synchroniser has the output thereof connected to a respective first input of a pair of AND gates, the second input of each of the gates being connected to output terminals of the read-only memory such that the second input of one of the gates is energised when the first counter has a count greater that that of the second counter and the second input of the other of the gates is energised when the first counter has a count less than the second counter, and wherein said synchroniser is arranged to receive the incoming data pulses and energise the first input of the gates in synchronism with pulses from the read-only memory on the required second input of the gates.

3. A circuit as claimed in claim 2 and wherein the first counter produces a staircase waveform having sixteen pulse steps prior to recycling.

4 A circuit as claimed in claim 3 and wherein the synchronising pulses are produced when the count of the first counter is equal to the count of the second counter plus eight pulse steps of the first counter.

5. A circuit for producing pulses synchronised with incoming data pulses substantially as

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. when the count of counter 3 is greater than that of counter 5 and the terminal 7 receiving a signal when the count of counter 3 is smaller than that of counter 5. The terminals 6 and 7 are each connected to a respective input of AND gates 8, 9, both of the AND gates being comprised by Texas Instruments Type No. 7400. The pre-clock pulses are also applied to a synchroniser 10 which is arranged to receive incoming data pulses from the terminal 2. The synchroniser 10 utilises the pre-clock pulses to produce pulses at each transition of the incoming data pulses in synchronism with pulses at either one of the terminals 6, 7 of the readonly memory 4 to energise a further input of each of the AND gates 8; 9. Output from the AND gate 8 is applied as a count-up input of the counter 5 and output from the AND gate 9 is applied as a count-down input to the counter 5. The read-only memory 4 has a further output terminal 11 at which is provided the required pulses synchronised with the incoming data pulses. The read-only memory 4 is preprogrammed such that the synchronised pulses at terminal 11 occur when the count of counter 3 is eight more pulse steps than the count of counter 5. In operation, at the start of the first incoming data bit which causes a first pulse output of the synchroniser 10 (shown in Figure 2d), suppose that the count of counter 3 is five (Figure 2b) and that the count of counter 5 (shown in Figure 2c) is seven. Because the count of counter 3 is less than that of counter 5 the read-only memory produces an output at terminal 7 so that the AND gate 9 is enabled since a pulse is also present from the synchronier 10. The counter 5 is thus, staticised at a lower count of six. Because the read-only memory 4 is programmed to produce an output at terminal 11 when the count of counter 3 is equal to the count of counter 5 plus eight, a clock synchronising pulse (shown in Figure 2e) isprovided at terminal 11 in synchronism with the fourteenth step of the staircase waveform of counter 3 (Figure 2b).At the next tran sition of the incoming data bits, the synchroniser 10 again applies a pulse to energise one of the terminals of both the AND gates 8, 9 and the counter 3 again has a count of five. The previously staticised count of counter 5 is still greater than that of the counter 3 and so an output is again derived at terminal 7 of the read-only memory 4 to enable AND gate 9 to step down the count of the counter 5 to five. The synchronisation pulse provided at terminal 11 is produced when the count of counter 3 is thirteen, i.e. the count of counter 5 which is five, plus'eight. At the next transition, i.e. the third pulse shown in Figure 2d, the counts in the two counters 3 and 5 are equal and so no re-alignment of the counter 5 is necessary. It will now be realised that if the phase of the incoming data bits vary more than one sixteenth of a cycle, with respect to the count in counter 3, then the count in counter 5 is incremented or decremented by one and the position of the synchronising pulse readjusted by one sixteenth of a cycle of the counter 3. This feature has the additonal advantage that if a noise spike should occur between the transition pulses of Figure 2d at the output of the synchroniser 10, then the count of counter 5 will be varied, either up or down, in dependence upon the counts of the counters 3 and 5 so that the phase of the synchronising pulse at the terminal 11 (Figure 2e) will be adjusted by only one sixteenth of a cycle of the count of counter 3. WHAT WE CLAIM IS:

1. A circuit for producing pulses synchronised with incoming data pulses including a readonly memory for comparing the phase difference between a first and a second counter and arranged to increment the count of the second counter in steps in response to said data pulses until a predetermined phase difference is established between the counters, the first counter being arranged to perform a counting cycle during the period of a bit cell of the incoming data pulses and the second counter having the count therein set until reviewed by the read-only memory in response to an incoming data pulse and wherein the read-only memory is arranged to produce a synchronising pulse during each bit cell when the count of the first counter is equal to the count of the second counter plus a predetermined count of integers of the first counter.

2. A circuit as claimed in claim 1 and wherein a locally generated series of pre-clock pulses independent of the incoming pulse data is applied to the first counter and synchroniser has the output thereof connected to a respective first input of a pair of AND gates, the second input of each of the gates being connected to output terminals of the read-only memory such that the second input of one of the gates is energised when the first counter has a count greater that that of the second counter and the second input of the other of the gates is energised when the first counter has a count less than the second counter, and wherein said synchroniser is arranged to receive the incoming data pulses and energise the first input of the gates in synchronism with pulses from the read-only memory on the required second input of the gates.

3. A circuit as claimed in claim 2 and wherein the first counter produces a staircase waveform having sixteen pulse steps prior to recycling.

4 A circuit as claimed in claim 3 and wherein the synchronising pulses are produced when the count of the first counter is equal to the count of the second counter plus eight pulse steps of the first counter.

5. A circuit for producing pulses synchronised with incoming data pulses substantially as

illustrated in and described with reference to Figure 1 of the drawings accompanying the Provisional specification.