GB1560698A - Receiving apparatus - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO RECEIVING APPARATUS (71) We, THE MARCONI COMPANY LIMITED, of Marconi House, New Street, Chelmsford CMI 1PL, Essex, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to receiving apparatus and more particularly to apparatus for receiving and reconstituting digital signals.

Digital signals are transmitted by for example frequency modulation of a carrier wave which is subsequently propagated by radio transmission to a receiving aerial. The signal is then demodulated and presented to digital decoding apparatus to reconstitute the original message. Unfortunately, as is well known, the received signal is often subject to interference, transmission losses etc. and is received in a distorted or diminished form.

Where it is desired to transmit a very long message a series of synchronising signals can be transmitted followed by a start signal and then by the message. This enables the digital decoder in the receiver to be synchronised so that it is clocked only for example at the certain instants of time corresponding to the centre part of each expected digital pulse. The presence of a pulse thus being easily detected by the received signal being above a predetermined threshold at those instants of time.

For short transmissions, however, it is not possible to send out a synchronising signal and a start signal since these would not leave sufficient transmission time for the message. It is therefore an object of the present invention to provide a method and apparatus for reconstituting transmitted data which method and apparatus are particularly advantageous in respect of short transmissions.

According to the present invention there is provided a method of receiving and decoding a digital message from a received signal in which the signal is fed to n parallel integrate and dump circuits the output of each of said integrate and dump circuits being fed to a respective one of n shift registers under the control of n trains of clock pulses the phases of which are staggered sequentially throughout the period of one such train so as to divide each period into n portions, in which values stored in the integrate and dump circuits are compared after N periods and in which the signal stored in the shift register corresponding to the integrate and dump circuit having the highest modulus value is the signal which is selected for decoding.

The present invention also provides apparatus for receiving and decoding a digitally coded signal including n integrate and dump circuits connected for receiving an incoming digitally coded signal, n shift registers each associated with a respective one of the n integrate and dump circuits and connected for receiving an input signal from its respective integrate and dump circuit, clock pulse generating means for the production of n trains of clock pulses the phases of which are staggered sequentially throughout the peiod of one such train so as to divide each period into n portions, in which each clock pulse train is associated with a respective integrate and dump circuit and its respective shift register for clocking the incoming digitally coded signal into the respective integrate and dump circuit and shift register, ann input signal comparison circuit for comparing the outputs of the n integrate and dump circuits after N clock pulse train periods and for producing an output signal indicative of the integrate and dump circuit with the maximum modulus integration value, and gating means for gating one of the signals stored in then shift registers through to decoding circuitry, the gating means being responsive to the output signal from the signal comparison means for the selection of the signal stored in the shift register associated with the integrate and dump circuit having the maximum modulus integration value at the end of the N clock pulse train periods.

The apparatus for receiving and decoding digitally coded signals preferably includes a signal present detector for the detection of an incoming signal. The signal present detector is operable for enabling the n input signal comparison circuit only when a signal of predetermined strength has been received.

The period of the clock pulse train is normally equal to the anticipated bit period of the incoming digitally coded signal.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows diagrammatically apparatus for synchronising and reconstituting a received digital signal; Figure 2 shows in block diagrammatic form apparatus according to the present invention for reconstituting a received digital signal; and Figure 3 shows an algorithm according to the present invention for use in reconstituting a received digital signal.

In a general sense the maximum timing information which may be extracted from a message has not been transmitted until the end of the message, so that the optimum strategy involves delaying any decisions on synchronisation of the signal until the end of the message.

On the basis that the standard deviation of the timing information varies inversely as the square root of the number of timing events, for a 16-bit di-phase word the use of all 24 (average) transitions would result in 7 dB reduction in timing variance compared with the use of a single transition.

To obtain the maximum timing information it is therefore necessary for a receiving system to incorporate some form of signal delay apparatus. A basic facility then offered is simultaneous access to signal samples from temporally separate instants. In terms for example of a delay-line structure with a determinate signal velocity v, the sample value t seconds ago is still available vt length units along the delay line. A pattern in time of signal samples may then be tested instantaneously by parallel-testing a spaced set of tapping points along the delay line.

The nature of the test applied to the sample values, and the spacing of the tapping points, provides the recognition facility for the required pattern.

As a simple example consider a pattern recogniser for a short full-baud binary NRZ word.

It is assumed that the bit rate is known with some precision, but the instant of starting is not known. Referring to Figure 1 the incoming message is clocked at say 5 times the bit rate down a shift register 100. By means of the equivalence gates 101,102,103 etc., the stored pattern is tested for the condition when small sections of the message at bit spacings are simultaneously free of transitions. When this occurs the AND gate 104 enables the display of the word stored at that instant in the shift register.

The equivalence gates function is given in the following truth table: Inputs Output All 1 AllO 1 Different 0 When the AND gate 104 produces an output the gate 105 is enabled which allows the selected pattern stored in the pattern recognition circuit 106 to be presented to the display or further processing means (not shown).

It will be seen that the detection is self synchronising in that it determines a timing within the bit period at which to evaluate the message. The restriction to short words may be overcome by successive recognition of short sections of a long stream. A more serious snag, however, is the poor noise performance, which is connected with the requirement both to decide whether a signal is present and to decide if it is a '0' or a '1'.

Some improvement may be made by majority vote schemes on the delay-line tappings.

However, a three-state output is required to obviate the interpretation of a new message every clock pulse, and it is found that a large number of tapping points are required.

For best noise performance, an optimum strategy for detecting 'square' Non Return to Zero (NRZ) digits is to integrate and dump the analogue received wave form, and to decide the polarity of the bit on the basis of the sign of the integrated signal at the end of the integration time. In the case of diphase signalling the sign of the integration should be reversed at mid-bit time. If the resultant be sliced to digital levels the 'message' may now be conveniently delayed in a shift register while a decision is made on whether a signal was present or not. The time available for this decision may be limited by implementation problems or the length of the message.In the latter case there is no more information available to be gained about the message timing except in so far as hardware limitations may prevent processing in real time, so that a record/replay technique may be advantageous in practice rather than principal.

An outline diagram which incorporates all these optimum features is given in Figure 2 to which reference is now made. A clock pulse generator 200 generates a clock pulse CP which has a pulse repetition frequency of substantially s2 times the anticipated bit rate of the received signal R. The clock is divided down by a divide by S circuit 201 to give S outputs each having a pulse repetition frequency of S times the anticipated bit rate of the received signal R.

The clock pulse generating means therefore generates S trains of clock pulses, each train appearing at a separate output of the divider 201. Thus each clock pulse train is at a pulse repetition rate of S times the anticipated bit rate.

Each clock pulse train is used to control a circuit 202 there thus being S circuits similar to 202 each circuit being connected in parallel to receive the input signal R via a filter 203 and a limiter/discriminator 204.

Each circuit 202 comprises an integrate and dump circuit 205, clocked by one of the clock pulse trains the input of which is the output signal from the limiter/discriminator circuit 204.

The output of the integrate and dump circuits 205 is connected to a signal slicer 206, the output of which is connected to a shift register 207 which has a storage capacity of S.N.

samples. The output of shift register 207 is connected to a gate 208.

The output of filter 203 is fed as input to an envelope detector 209 the output of which detector is fed to a further integrate and dump circuit 210 which is clocked by a clock pulse train derived by dividing down in a divide by N divider 211 the clock pulse train which controls the integrate and dump circuit 205. The output of the integrate and dump circuit 210 is connected to a threshold circuit 212, the output of which is connected to one input of an AND gate 213. The output of AND gate 213 is fed to the inhibit inputs of two inhibit gates 208, 214, gate 214 being a clock gate which allows the clock pulse train through AND gate 208 being a message gate which allows the data through when these gates are not inhibited.

The integrate and dump circuit 205 produces an output, at each clock pulse, to the slicer 206 and also to an output terminal W1. This latter output is used as an input to a maximum likelihood detector circuit 215. Circuit 215 has a number of output terminals connected to respective inputs to the S gates 213 and produces a single output on one of these tenninals to enable a particular gate 213 in one of the S circuits 202, the circuit 202 chosen being the circuit from which the largest pulse weighting has been obtained over the chosen clock pulse period.

The system as shown in Figure 2 operates as follows: The analogue waveform from the discriminator 204 is integrated, sampled and dumped at the known system-standard bit rate, with mid-bit-time sign reversals if diphase coding is used.

To achieve the correct sub-bit timing phase' there are a number, S which may in a practical embodiment be 8, of these circuits working in 'polyphase' so that one of them must be within one sixteenth of a bit of the correct time position.

The sample values thus obtained are sliced in slicer 206 to digital levels and clocked at the bit rate down the shift register 207 which is capable of storing all the bits in the expected message. The delayed message, and the relevant clock 'phase' are passed via a message gate 208 and a clock gate 214 to the message recognition and display circuits (not shown).

Selection of the appropriate integrate and dump time 'phase' is controlled by measuring the sum of the moduli of the message signal integrals which have been dumped during the expected message time. The best time 'phase' is the one which has managed to integrate up the most signal modulus, and an analogue measure is made available from each integrate and dump circuit 205. This measure, shown as WEIGHT W1 in Figure 2, is passed to the eight input maximum likelihood detector 215, which outputs an ENABLE gate waveform to the channel giving the largest weight signal. This is used to enable the message and clock gates 208, 214, allowing the best copy of the message, and its clock phase' to pass to the recognition/display circuits.

In order to squelch messages in the absence of signal, a "signal present" detector is provided, operating via the envelope detector 209 on the wide-band IF signals. A postdetector filter, voltage threshold and time threshold are used to detect the presence of a signal within the IF bandwidth but with an integration time approaching the whole message time.

The combination of a voltage and time threshold (i.e. the integrated signal level must exceed the voltage threshold level V for a minimum (threshold) time Z), and the long integration time available (e.g. 16 bits), should result in a squelch' action which is more sensitive in signal-to-noise ratio than the more usual arrangements. The squelch output is used to enable the maximum likelihood channel selector when a "signal present" indication is received.

The method of signal detection and pattern recognition as described with reference to Figure 2 is based on the use of simple analogue circuits to perform mathematical operations on the received time waveform. Thus integration is performed by passing a current into a caDacitor and noting the voltage achieved, while selecting the large signal is achieved by the maximum likelihood detector 215 which is in the form of a multi-input non-linear amplifier.

The integrate and dump circuit 205 represents an optimum filter for 'square' digits, but since a typical transmitter normally uses pre-modulation filtering to control the occupied bandwidth, the optimum receiver filter is in principle different but so complex that normally the simple integrate and dump circuit is used as a practical near-optimum arrangement.

A technique which offers extreme flexibility in signal processing is numerical analysis. The incoming signal is sampled at a rate say several times as fast as the Nyquist rate and the samples are digitised into binary members representing the signal level at the sampling instant. These sample values are processed in a microprocessor according to any chosen mathematical algorithm representing some optimal processing technique. Signal integration may be performed by summing samples, and differentiation by taking differences. Cross correlation with a standard waveform can be achieved by numerical multiplication of signal samples and samples stored in a RAM, followed by an averaging process on the results.

A current technology microcomputer system of interest is the MCS4. The CPU is a 16 lead DIP package consuming about 0.7 watts, and the minimum number of peripherals for computer operation is one ROM. The instruction-execute routine takes 11-22 microseconds, so that additions might be implemented in around 30,u sec., and multiplications of 4-bit words might be achieved in a similar time by the use of stored tables. At, say, 250 bits/second of input information in diphase form, and taking eight samples per symbol, the sample rate would be 4000 per second. Thus up to eight mathematical operations might be performed in real time on the incoming data.

A simple algorithm for integrate and dump processing by numerical analysis is described hereinafter including the cquivalent of a 'signal present' signal squelch based on integration over as many diphase bits as can be stored, or as many as are available in the shortest word to be recognised. This requires six additions, or five additions and a multiply-by-two. so that quite realistic signal processing in real time by numerical analysis appears feasible in few-chip microprocessor systems.

The received message is assumed to be in diphase form with known bit rate, but of unknown timing ('phase'). It is sampled at n equispaced points per bit, where n is chosen to be large enough to reduce the numerical analysis errors, but small enough to simplify the hardware implementation problems. For simplicity it is assumed that n = 8 i.e. 4 samples per symbol.

The sample values are digitised to give a numerical measure of the signal voltage at the sampling instant. Let the sample values be AN, N = 1 to 'infinity'. It is required to process these numerical measures and produce a best estimate of the received signal.

The output of an integrate and dump circuit may be calculated as follows: The integral is replaced by the sum of products of strip width and height. Since the strip width is fixed by the sampling rate, the integral may be replaced by the sum of the sample values over the integration time, except that the sign of integration must be reversed at mid-'bit' time to account for the diphase transition. Since the bit start time is unknown, 8 trial sums must be formed.

Let these sums be BN, N = 1 to 8, so that B1= -A1 - A2 - A3 - A4+ A5+ A6 + A7 + A8 B2= - A2 - A3 - A4 - A5 +A6+A7 + A8 + A9 etc. to B8 = etc.

Continuing this process indefinitely, the sample streams Bl,B9,B17.............

or B2, B10, B18 ...........

or B8, B16, B24 ............

are 8 candidate messages, corresponding to the 8 sub-bit timing positions ('phases') of the reconstitution.

Assuming that the noise level does not increase too fast as the signal decreases, the message most likely to correspond to the transmitted message is the one whose bit-time integrations have yielded the greatest (modulus) resultants.

A further set of samples CN, N = 1 to 8 is formed: Cl = B1 + B9 + B17 + ............

C2= B2 + B10 + B18 + .............

C8 = B8 + Bl6 + B24 + .............

taking as many samples as possible, limited by either hardware problems, or the time delay involved, or the length of the shortest message to be recognised. These samples CN are a measure of the total signal integrated over as many bits as were used in their formation, and the largest CN, say CM, implies that the sample stream beginning BM, B(M + 8) etc. is the one most likely to be correct.

The concept of the algorithm is shown in Figure 3. The amount of calculation involved is much less than might be expected from the above description, and the simplifications are obtained as follows: By examing the defining equations for the BN, N = 1 to 8, it is seen that B2 = B1 + Al -2A5 + A9 etc.

so that the complete matrix of the BN values may be serially formed by the running sum:- plus the latest A value, minus twice the A value 4 samples ago, and plus the A value 8 samples ago.

This is either additions', or 3 'additions' and a multiply-by-two, which is easily performed in a practical binary system.

Similarly the CN values are formed by the 8 running sums of the modulus of the latest B value and minus the modulus of the B value 8L samples ago, where L is the number of bits over which the time-phase determination is to be performed. This requires only 2 'additions' per sample value.

The reconstituted data stream is now available in serial form as the sign bit of the most-delayed BM value, where M is the value of N which maximises CN. The parallel form of the data, for the last L bits, is in principle available as the sign bits of all the B values in that time phase.

WHAT WE CLAIM IS: 1. A method of receiving and decoding a digital message from a received signal in which the signal is fed to n parallel integrate and dump circuits the output of eqch of said integrate and drop circuits being fed to a respective one of n shift registers under the control of n trains of clock pulses the phases of which are staggered sequentially throughout the period of one such train so as to divide each period into n portions, in which values stored in the integrate and dump circuits are compared after N periods and in which the signal stored in the shift register corresponding to the integrate and dump circuit having the highest modulus value is the signal which is selected for decoding.

2. A method as claimed in Claim I , wherein the period of the clock pulse train is equal to the anticipated bit period of the incoming digitally coded signal.

3. A method as claimed in Claim l or Claim 2, wherein the received signal is in diphase form and the sign of the integration is reversed at mid-bit-time.

4. A method as claimed in any preceding claim, wherein n is eight.

Apparatus for receiving and decoding a digitally coded signal comprising n integrate and dump circuits connected for receiving an incoming digitally coded signal, n shift registers each associated with a respective one of then integrate and dump circuits and connected for receiving an input signal from its respective integrate and dump circuit, clock pulse generating means for the production of n trains of clock pulses the phases of which are staggered sequentially throughout the period of one such train so as to divide each period into n portions, in which each clock pulse train is associated with a respective integrate and dump circuit and its respective shift register for clocking the incoming digitally coded signal into the respective integrate and dump circuit and shift register, an n input signal comparison circuit for comparing the outputs of the n integrate and dump circuits after N clock pulse train

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (12)

**WARNING** start of CLMS field may overlap end of DESC **. are 8 candidate messages, corresponding to the 8 sub-bit timing positions ('phases') of the reconstitution. Assuming that the noise level does not increase too fast as the signal decreases, the message most likely to correspond to the transmitted message is the one whose bit-time integrations have yielded the greatest (modulus) resultants. A further set of samples CN, N = 1 to 8 is formed: Cl = B1 + B9 + B17 + ............ C2= B2 + B10 + B18 + ............. C8 = B8 + Bl6 + B24 + ............. taking as many samples as possible, limited by either hardware problems, or the time delay involved, or the length of the shortest message to be recognised. These samples CN are a measure of the total signal integrated over as many bits as were used in their formation, and the largest CN, say CM, implies that the sample stream beginning BM, B(M + 8) etc. is the one most likely to be correct. The concept of the algorithm is shown in Figure 3. The amount of calculation involved is much less than might be expected from the above description, and the simplifications are obtained as follows: By examing the defining equations for the BN, N = 1 to 8, it is seen that B2 = B1 + Al -2A5 + A9 etc. so that the complete matrix of the BN values may be serially formed by the running sum:- plus the latest A value, minus twice the A value 4 samples ago, and plus the A value 8 samples ago. This is either additions', or 3 'additions' and a multiply-by-two, which is easily performed in a practical binary system. Similarly the CN values are formed by the 8 running sums of the modulus of the latest B value and minus the modulus of the B value 8L samples ago, where L is the number of bits over which the time-phase determination is to be performed. This requires only 2 'additions' per sample value. The reconstituted data stream is now available in serial form as the sign bit of the most-delayed BM value, where M is the value of N which maximises CN. The parallel form of the data, for the last L bits, is in principle available as the sign bits of all the B values in that time phase. WHAT WE CLAIM IS:

1. A method of receiving and decoding a digital message from a received signal in which the signal is fed to n parallel integrate and dump circuits the output of eqch of said integrate and drop circuits being fed to a respective one of n shift registers under the control of n trains of clock pulses the phases of which are staggered sequentially throughout the period of one such train so as to divide each period into n portions, in which values stored in the integrate and dump circuits are compared after N periods and in which the signal stored in the shift register corresponding to the integrate and dump circuit having the highest modulus value is the signal which is selected for decoding.

2. A method as claimed in Claim I , wherein the period of the clock pulse train is equal to the anticipated bit period of the incoming digitally coded signal.

3. A method as claimed in Claim l or Claim 2, wherein the received signal is in diphase form and the sign of the integration is reversed at mid-bit-time.

4. A method as claimed in any preceding claim, wherein n is eight.

Apparatus for receiving and decoding a digitally coded signal comprising n integrate and dump circuits connected for receiving an incoming digitally coded signal, n shift registers each associated with a respective one of then integrate and dump circuits and connected for receiving an input signal from its respective integrate and dump circuit, clock pulse generating means for the production of n trains of clock pulses the phases of which are staggered sequentially throughout the period of one such train so as to divide each period into n portions, in which each clock pulse train is associated with a respective integrate and dump circuit and its respective shift register for clocking the incoming digitally coded signal into the respective integrate and dump circuit and shift register, an n input signal comparison circuit for comparing the outputs of the n integrate and dump circuits after N clock pulse train

periods and for producing an output signal indicative of the integrate and dump circuit with the maximum modulus integration value, and gating means for gating one of the signals stored in the n shift registers through to decoding circuitry, the gating means being responsive to the output signal from the signal comparison means for the selection of the signal stored in the shift register associated with the integrate and dump circuit having the maximum modulus integration value at the end of the N clock pulse train periods.

6. Apparatus as claimed in Claim 5, including a signal present detector for the detection of an incoming signal.

7. Apparatus as claimed in Claim 6, wherein the signal present detector is operable for enabling the n input signal comparison circuit only when a signal of predetermined strength has been received.

8. Apparatus as claimed in any one of Claims 5 to 7, wherein the period of the clock pulse train is equal to the anticipated bit period of the incoming digitally coded signal.

9. A method of receiving and decoding a digital message from a received signal substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.

10. A method as claimed in Claim 9, using an algorithm substantially as hereinbefore described with reference to Figure 3 of the accompanying drawings.

11. Apparatus for receiving and decoding a digitally coded signal substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.

12. Apparatus as claimed in Claim 11, arranged to operate substantially in accordance with the algorithm described with reference to Figure 3 of the accompanying drawings.