GB1533768A - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
GB1533768A
GB1533768A GB42463/76A GB4246376A GB1533768A GB 1533768 A GB1533768 A GB 1533768A GB 42463/76 A GB42463/76 A GB 42463/76A GB 4246376 A GB4246376 A GB 4246376A GB 1533768 A GB1533768 A GB 1533768A
Authority
GB
United Kingdom
Prior art keywords
sub
data
store
copy back
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB42463/76A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/642,035 external-priority patent/US4077059A/en
Priority claimed from US05/642,034 external-priority patent/US4084231A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1533768A publication Critical patent/GB1533768A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Abstract

1533768 Data processing systems INTERNATIONAL BUSINESS MACHINES CORP 13 Oct 1976 [18 Dec 1975 (2)] 42463/76 Heading G4A Two independently powered sub-systems A, B each including a data store 14 and an auxiliary store 18, the latter being arranged to hold representations of changes made to the data in the data store 14 of the other sub-system during operation, are so arranged that in the event of a failure in one sub-system data can be copied back to bulk storage via the other sub-system. For simplicity Fig. 1 shows the level L 1 auxiliary store 18a associated with the L1 store 14a and processors 10a of sub-system A, but in practice store 18a and an associated journal 20a, which records the order in which changes are made to the data in store 14a, would be packaged with sub-system B and store 18b and journal 20b would be packaged with sub-system A. Similarly the copy back BSM 34 for sub-system B at levels L2, L3 is packaged with the data storage BSM's for sub-system A and vice versa. At level L4 which comprises a plurality of disc units 38 each having a plurality of actuators for accessing dedicated groups of cylinders, the copy back area of each sub-system is on a different spindle 38 to that on which its data is stored. The lowest level L5 of storage is formed by a magnetic tape cartridge unit 40. Two stations are provided on each of units 38, 40 for connecting them in two independently powered loops 42, 44. Associated with level L4 in each subsystem is a pair of buffers, each buffer having a capacity equal to that of one disc unit track, copy back of a complete track being initiated when a buffer is filled, and further copy back data being loaded into the other buffer of the pair while copy back on to the disc unit is taking place. With each new modification of a page a new copy back space on disc is allocated and a bit map associated with L4 is updated to invalidate any existing previous modification in L4 so that it will not be copied back to L5. Each directory and store has SEC-DED facilities to initiate the appropriate non-connectible error recovery according to whether the error occurred in a data store, directory or journal and whether or not any change has been made to the data since it was paged up from the next lower level. The disclosure is identical with that of Specification 1,533,767.
GB42463/76A 1975-12-18 1976-10-13 Data processing apparatus Expired GB1533768A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/642,035 US4077059A (en) 1975-12-18 1975-12-18 Multi-processing system with a hierarchial memory having journaling and copyback
US05/642,034 US4084231A (en) 1975-12-18 1975-12-18 System for facilitating the copying back of data in disc and tape units of a memory hierarchial system

Publications (1)

Publication Number Publication Date
GB1533768A true GB1533768A (en) 1978-11-29

Family

ID=27093913

Family Applications (1)

Application Number Title Priority Date Filing Date
GB42463/76A Expired GB1533768A (en) 1975-12-18 1976-10-13 Data processing apparatus

Country Status (2)

Country Link
DE (1) DE2655829A1 (en)
GB (1) GB1533768A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3068498D1 (en) * 1979-05-09 1984-08-16 Int Computers Ltd Hierarchical data storage system

Also Published As

Publication number Publication date
DE2655829A1 (en) 1977-07-07

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee