GB1480208A - Digital computers - Google Patents

Abstract

1480208 Data processing system DATALOOP Ltd 3 July 1974 [6 April 1973] 16684/73 Heading G4A In a data processing system comprising a data processing unit and a plurality of other units all interconnected for data exchange by a common bus, each unit, when it wishes to transmit data to another unit tests a "busy line" in the bus for the presence of a set signal, on detecting such a signal periodically repeats the test until no such signal is detected, the absence of a set signal on the busy line causing the unit to apply a set signal to the busy line and its own unique address, having a number of digits inversely proportional to its own priority, to a set of address lines in the bus, the unit then tests that the address on the address lines in respect of the number of digits in its own address is correct, each address of lower priority differing from an address of higher priority only in respect of digits additional to those of the address of higher priority, an incorrect address causing the unit to revert to testing the busy line and a correct address causing the unit to replace its own address by the address of the unit which is to receive the data and to transmit the data to the bus while maintaining the set signal on the busy line until the transmission is complete, each unit responding to its own address on the bus to receive data from the bus. Each unit is assigned a priority and its address is given by a single "1" bit at a distance from one end of the address word corresponding to its priority; thus in Fig. 4 unit A has the highest priority, unit B the next highest priority, and unit C the lowest priority. Thus if two units simultaneously sieze the bus the lower priority unit will detect the "1" bit of the high priority unit, conclude that its address is incorrectly applied, and drop out thus leaving the bus to the higher priority unit.