GB1456643A - Decoding a coded signal - Google Patents

Abstract

1456643 Selective signalling COLUMBIA PICTURES INDUSTRIES Inc 15 Nov 1973 [15 Nov 1972 (2)] 53038/73 Heading G4H [Also in Division H4] An address portion of a bit serial coded signal is compared with a serial reference address from one output of a read-only memory which (assuming agreement) also produces at least one enabling signal to enable decoding of a command portion of the serial coded signal. Fig. 1 shows a converter-tuner unit of a subscription TV system. The cable at the left carries standard broadcast TV signals, and a plurality of secure TV channels (each modulated on to a respective carrier) and a command carrier. A multi-bit address followed by an operation bit and command bits may be modulated on to the command carrier using a tone in split phase mark fashion, viz. a transition between presence and absence of the tone at each bit cell boundary and such a transition in the middle of each "1" bit cell. The address, operation and command bits are amplified and detected, with A.G.C., at 20, 29, 35 to feed the tone signals to logic circuitry 30 (see below) which, if it recognizes the address as being that of this converter-tuner, decodes the remaining bits to specify for each secure TV channel whether it may be received. A diode switch 10 is used to pass standard or secure channel TV signals to the TV receiver. Assuming that one of the secure channels is selected by a selector switch 38 and reception of it is permitted by the logic circuitry 30, the signals for all the secure channels, passed by a band-pass filter 40, go to a varactor tuned filter which selects the required secure channel (under control of the selector switch 38) for mixing in a double balanced mixer 60 with a frequency (lower than that of the channel carrier) from a local oscillator. The local oscillator uses a common transistor controlled by one of a plurality of crystals (one per channel) selected by diode switches controlled by the selector switch 38. The output of mixer 60 goes via a channel 12 amplifier 90 and filter 80 to the receiver (via diode switch 10). Local oscillator frequency harmonics which are close to a secure channel carrier frequency are cancelled by a resonant circuit providing anti-phase feedback from filter 50 to filter 40. Details of logic circuitry 30 (including address recognition).-The tone sequence representing the address, operation and command bits passes to a monostable tone burst detector 100 followed by an edge detector 110 and a data and clock converter 120 which supplies data pulses and a bit clock. The bit clock drives a counter 140 which addresses a read-only memory 150. During the address reception, memory 150 enables a compare (EX-OR) gate 160 and a data change latch 190, and supplies the address of the unit to compare gate 160 serially-by-bit for comparison with the address received. Any mismatch resets the counter 140, except that this is inhibited by the data change latch if the address is all zero (which addresses all the tunerconverter units). If the counter is not reset, then for command bit reception, the memory 150 in conjunction with the operation bit sets an operation bit latch 200 to partially enable a latch 210, 220 for each channel, these being also partially enabled in turn by memory 150 directly, to receive respective command bits. The outputs of these latches go via capacitor storage to the selector switch which can select one of them. Resetting at the end of the message is performed by a monostable data presence detector 130 responsive to the edge detector 110.