GB1445914A - Apparatus for producing graphical data descriptive of an integrated circuit design - Google Patents

Apparatus for producing graphical data descriptive of an integrated circuit design

Info

Publication number
GB1445914A
GB1445914A GB3795374A GB3795374A GB1445914A GB 1445914 A GB1445914 A GB 1445914A GB 3795374 A GB3795374 A GB 3795374A GB 3795374 A GB3795374 A GB 3795374A GB 1445914 A GB1445914 A GB 1445914A
Authority
GB
United Kingdom
Prior art keywords
information
data
design
circuit
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3795374A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1445914A publication Critical patent/GB1445914A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1445914 Integrated circuit design INTERNATIONAL BUSINESS MACHINES CORP 30 Aug 1974 [27 Sept 1973] 37953/74 Heading G4A Apparatus for producing graphical data descriptive of an integrated circuit design includes means for storing graphical description of free form designs, means for storing topological data and electrical characteristics of rules restricted designs, means for entering information for correlating a free form design with a rules restricted design and means for merging the generated graphical description of the rules restricted design with the stored free form design. Initially the designer produces a lay-out in block form of the logical functions to be included in the chip. Next he selects a chip image (as in Fig. 3, not shown) and assigns logic functions to different areas of the chip (by using X, Y co-ordinates). From this, information in the form of the required logic and possible placement of it is fed in to an FET automated design system 16 (Fig. 2), this comprising a series of programs for execution on a general purpose computer. From the input information and information from a library 18 (which is a file describing the electrical characteristics of circircuits, topology thereof and images) the system generates a chip image (38, Fig. 4, not shown). Next the device sizes required for each circuit to meet its specified performance are calculated (42), information relating to (1) the input wave form and/or loading present at input/output pads (44) (in the form given in Fig. 5d, not shown), (2) the connections necessary to implement the logic (48) (in the form given in Fig. 5c, not shown), (3) circuit data information (46) (in the form given in Fig. 5a, not shown) and (4) free from data (50) (in the form given in Fig. 5b, not shown) being fed in. The next step (52) is the calculation of the circuit locations from the output of the previous step (42) and circuit data with relative co-ordinates included (54). From this information a wire list (56) is produced indicating the co-ordinates for each LST from which the designer derives data (of the form given in Fig. 5e, not shown), a wire routing operation being effected using this data and the output of the previous step (52) to interconnect all the circuit LSTs and I/O pads. A check is made on for example critical spacing and net continuity. The output of the system 16 is used to obtain from the library 18 the free form description with which it is merged to form a total chip description (11) from which photographic masks may be made to produce a LSI device.
GB3795374A 1973-09-27 1974-08-30 Apparatus for producing graphical data descriptive of an integrated circuit design Expired GB1445914A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US40130373A 1973-09-27 1973-09-27

Publications (1)

Publication Number Publication Date
GB1445914A true GB1445914A (en) 1976-08-11

Family

ID=23587182

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3795374A Expired GB1445914A (en) 1973-09-27 1974-08-30 Apparatus for producing graphical data descriptive of an integrated circuit design

Country Status (4)

Country Link
JP (1) JPS5061989A (en)
DE (1) DE2442850A1 (en)
FR (1) FR2245984B1 (en)
GB (1) GB1445914A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791593A (en) * 1985-03-08 1988-12-13 Bernard Hennion System for the simulation of an electronic circuit
US4803636A (en) * 1985-09-27 1989-02-07 Hitachi Ltd. Circuit translator
US4922432A (en) * 1988-01-13 1990-05-01 International Chip Corporation Knowledge based method and apparatus for designing integrated circuits using functional specifications
US5095441A (en) * 1986-09-12 1992-03-10 Digital Equipment Corporation Rule inference and localization during synthesis of logic circuit designs
US5150308A (en) * 1986-09-12 1992-09-22 Digital Equipment Corporation Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs
US5151867A (en) * 1986-09-12 1992-09-29 Digital Equipment Corporation Method of minimizing sum-of-product cases in a heterogeneous data base environment for circuit synthesis
GB2255661A (en) * 1991-04-30 1992-11-11 Tecnocad Limited Design of articles having inter-related parts
US5175696A (en) * 1986-09-12 1992-12-29 Digital Equipment Corporation Rule structure in a procedure for synthesis of logic circuits
US5212650A (en) * 1986-09-12 1993-05-18 Digital Equipment Corporation Procedure and data structure for synthesis and transformation of logic circuit designs
US5222029A (en) * 1986-09-12 1993-06-22 Digital Equipment Corporation Bitwise implementation mechanism for a circuit design synthesis procedure
US5267175A (en) * 1986-09-12 1993-11-30 Digital Equipment Corporation Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design
US5299137A (en) * 1990-04-05 1994-03-29 Vlsi Technology, Inc. Behavioral synthesis of circuits including high impedance buffers
US5452226A (en) * 1986-09-12 1995-09-19 Digital Equipment Corporation Rule structure for insertion of new elements in a circuit design synthesis procedure
US5617327A (en) * 1993-07-30 1997-04-01 Xilinx, Inc. Method for entering state flow diagrams using schematic editor programs
CN117574851A (en) * 2024-01-11 2024-02-20 上海合见工业软件集团有限公司 Method, device and storage medium for reconstructing circuit schematic diagram in EDA tool

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961944A (en) * 1982-09-30 1984-04-09 Fujitsu Ltd Manufacture of master slice integrated circuit
JP2954223B2 (en) * 1988-11-08 1999-09-27 富士通株式会社 Method for manufacturing semiconductor device
EP0385013B1 (en) * 1989-03-03 1999-06-16 Trw Inc. Production of precision patterns on curved surfaces

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791593A (en) * 1985-03-08 1988-12-13 Bernard Hennion System for the simulation of an electronic circuit
US4803636A (en) * 1985-09-27 1989-02-07 Hitachi Ltd. Circuit translator
US5212650A (en) * 1986-09-12 1993-05-18 Digital Equipment Corporation Procedure and data structure for synthesis and transformation of logic circuit designs
US5452226A (en) * 1986-09-12 1995-09-19 Digital Equipment Corporation Rule structure for insertion of new elements in a circuit design synthesis procedure
US5150308A (en) * 1986-09-12 1992-09-22 Digital Equipment Corporation Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs
US5151867A (en) * 1986-09-12 1992-09-29 Digital Equipment Corporation Method of minimizing sum-of-product cases in a heterogeneous data base environment for circuit synthesis
US5095441A (en) * 1986-09-12 1992-03-10 Digital Equipment Corporation Rule inference and localization during synthesis of logic circuit designs
US5175696A (en) * 1986-09-12 1992-12-29 Digital Equipment Corporation Rule structure in a procedure for synthesis of logic circuits
US5267175A (en) * 1986-09-12 1993-11-30 Digital Equipment Corporation Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design
US5222029A (en) * 1986-09-12 1993-06-22 Digital Equipment Corporation Bitwise implementation mechanism for a circuit design synthesis procedure
US4922432A (en) * 1988-01-13 1990-05-01 International Chip Corporation Knowledge based method and apparatus for designing integrated circuits using functional specifications
US5299137A (en) * 1990-04-05 1994-03-29 Vlsi Technology, Inc. Behavioral synthesis of circuits including high impedance buffers
GB2255661A (en) * 1991-04-30 1992-11-11 Tecnocad Limited Design of articles having inter-related parts
US5617327A (en) * 1993-07-30 1997-04-01 Xilinx, Inc. Method for entering state flow diagrams using schematic editor programs
US5691912A (en) * 1993-07-30 1997-11-25 Xilinx, Inc. Method for entering state flow diagrams using schematic editor programs
US5894420A (en) * 1993-07-30 1999-04-13 Xilinx, Inc. Method for spawning two independent states in a state flow diagram
CN117574851A (en) * 2024-01-11 2024-02-20 上海合见工业软件集团有限公司 Method, device and storage medium for reconstructing circuit schematic diagram in EDA tool
CN117574851B (en) * 2024-01-11 2024-04-19 上海合见工业软件集团有限公司 Method, device and storage medium for reconstructing circuit schematic diagram in EDA tool

Also Published As

Publication number Publication date
DE2442850A1 (en) 1975-04-10
FR2245984A1 (en) 1975-04-25
JPS5061989A (en) 1975-05-27
FR2245984B1 (en) 1977-03-18

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee